CN120936135A - Back contact battery, manufacturing method thereof and photovoltaic module - Google Patents

Abstract

The invention discloses a back contact battery, a manufacturing method thereof and a photovoltaic module, and relates to the technical field of photovoltaics, so as to reduce the carrier recombination rate of the edge part of a first doped semiconductor part close to a third region and improve the conversion efficiency of the back contact battery. The back contact cell includes a semiconductor substrate, a first doped semiconductor portion, a second doped semiconductor portion, and a dielectric barrier layer. The first side of the semiconductor substrate includes a first region, a second region, and a third region. The first doped semiconductor portion is disposed in the first region and the third region. The dielectric barrier layer is disposed on at least a portion of the first side surface proximate to the third region. The second doped semiconductor portion is disposed on the second region, and at least part of the second doped semiconductor portion extends to cover the dielectric barrier layer and the first doped semiconductor portion in the third region. The second doped semiconductor portion and the first doped semiconductor portion are opposite in doping type, and in the third region, the second doped semiconductor portion and the first doped semiconductor portion are electrically connected.

Description

Back contact battery, manufacturing method thereof and photovoltaic module

Technical Field

The invention relates to the technical field of photovoltaics, in particular to a back contact battery, a manufacturing method thereof and a photovoltaic module.

Background

The back contact battery is a solar battery with the second surface of the battery piece being electrodeless, and the positive electrode and the negative electrode are arranged on one side of the backlight surface of the battery piece, so that shielding of the battery piece by the electrodes can be reduced, short-circuit current of the battery piece is increased, and energy conversion efficiency of the battery piece is improved.

However, the carrier recombination rate at the back side of the existing back contact battery is high, which is not beneficial to improving the conversion efficiency of the back contact battery.

Disclosure of Invention

The invention aims to provide a back contact battery, a manufacturing method thereof and a photovoltaic module, which are used for reducing the carrier recombination rate of the edge part of a first doped semiconductor part, which is close to a third area, so as to be beneficial to improving the conversion efficiency of the back contact battery in a forward voltage area.

In order to achieve the above object, in a first aspect, the present invention provides a back contact battery including a semiconductor substrate, a first doped semiconductor portion, a second doped semiconductor portion, and a dielectric barrier layer. The semiconductor substrate includes opposing first and second sides. The first face includes first and second regions alternately spaced apart and a third region located between the first and second regions. The bottom surface of the second region is smaller than the surface heights of the first region and the third region along the direction from the second surface to the first surface, and a first side surface for connection is arranged between the second region and the third region. The first doped semiconductor portion is disposed in the first region and the third region. The dielectric barrier layer is disposed on at least a portion of the first side surface proximate to the third region. The second doped semiconductor portion is disposed on the second region, and at least part of the second doped semiconductor portion extends to cover the dielectric barrier layer and the first doped semiconductor portion in the third region. The second doped semiconductor portion and the first doped semiconductor portion are opposite in doping type, and in the third region, the second doped semiconductor portion and the first doped semiconductor portion are electrically connected.

Under the condition of adopting the technical scheme, in the back contact battery provided by the invention, the surface height of the second region provided with the second doped semiconductor part is smaller than the surface heights of the first region and the third region provided with the first doped semiconductor part, so that the surfaces of the first region and the third region and the surface of the second region can be staggered along the thickness direction of the semiconductor substrate, at the moment, in the process of actually manufacturing the back contact battery, after the patterning treatment is carried out on the first doped semiconductor part arranged on the whole layer, the first doped semiconductor part positioned in the second region is completely removed, the carrier recombination rate of the second region is reduced, meanwhile, the second doped semiconductor part has higher carrier collection efficiency, and the back contact battery has higher conversion efficiency in a forward voltage region.

In addition, the second doped semiconductor portion is not only disposed on the second region, but at least a portion of the second doped semiconductor portion is also disposed to extend over the dielectric barrier layer and the first doped semiconductor portion in the third region. In addition, in the third region, the second doped semiconductor part and the first doped semiconductor part with opposite conductivity types can be electrically connected to form a diode structure with lower reverse breakdown voltage, so that the reverse breakdown voltage of the back contact battery under the shielding condition is reduced, the hot spot risk of the back contact battery is reduced, and the burning resistance of the back contact battery is improved. At the same time, the second doped semiconductor portion also extends over a dielectric barrier layer disposed at least between the third region and the second region. The dielectric barrier layer has a certain diffusion barrier effect. Based on this, even in the actual manufacturing process, when the doping treatment is performed on the second doped semiconductor portion provided on the whole layer, the dopant can continue to diffuse downward into the dielectric barrier layer through the second doped semiconductor portion, but under the barrier of the dielectric barrier layer, the diffusion of the dopant into the portion of the semiconductor substrate near the edge of the first doped semiconductor portion can be reduced or even prevented, the carrier recombination rate at the portion of the semiconductor substrate near the edge of the first doped semiconductor portion is reduced, and at the same time, the edge portion of the first doped semiconductor portion is made to have a higher carrier collection efficiency. In addition, the existence of the dielectric barrier layer can reduce the magnitude of reverse leakage current, balance the conversion efficiency and the burnout resistance of the back contact battery and improve the working performance of the back contact battery.

As a possible implementation, the dielectric barrier layer also extends between a part of the first doped semiconductor portion and a part of the second doped semiconductor portion located in the third region in a direction away from the second region. Under the condition, the dielectric barrier layer can be ensured to cover the part, close to the third area, of the first side surface, the difficulty in patterning the dielectric barrier layer is reduced, the size of reverse leakage current is further reduced, and the conversion efficiency of the back contact battery in a forward voltage area is improved.

As a possible implementation, the ratio of the width of the dielectric barrier layer located on the third region to the width of the third region is greater than or equal to 0.1 and less than or equal to 0.8, and/or the width of the dielectric barrier layer located on the third region is greater than or equal to 20 μm and less than or equal to 400 μm.

Under the condition of adopting the technical scheme, the ratio of the width of the dielectric barrier layer positioned on the third region to the width of the third region is in the range, so that the difficulty of patterning the dielectric barrier layer is prevented from being higher due to the smaller ratio, and the yield of the back contact battery is improved. And the reverse leakage current between the first doped semiconductor part and the second doped semiconductor part is prevented from flowing little when the back contact battery is shielded due to the overlarge ratio, so that the burning resistance of the back contact battery is improved. As for the application principle of the beneficial effects that the width of the dielectric barrier layer located on the third region is 20 μm or more and 400 μm or less, reference may be made to the application principle of the beneficial effects that the ratio of the width of the dielectric barrier layer located on the third region to the width of the third region is 0.1 or more and 0.8 or less, which is described above, and will not be repeated here.

As a possible implementation, the dielectric barrier layer is an insulating dielectric layer. Under the condition, the dopant in the second doped semiconductor part can be prevented from diffusing to the part of the semiconductor substrate close to the edge of the first doped semiconductor part through the dielectric barrier layer, the part of the semiconductor substrate close to the edge of the first doped semiconductor part can be electrically insulated from the second doped semiconductor part through the dielectric barrier layer, leakage current is prevented from being formed between the part of the semiconductor substrate close to the edge of the first doped semiconductor part and the second doped semiconductor part, the carrier recombination rate is reduced to a large extent, and the conversion efficiency of the back contact battery in a forward voltage region is improved.

As a possible implementation, the second doped semiconductor portions are intermittently distributed along the length direction of the third region and over the third region. In this case, it is advantageous to reduce the magnitude of the reverse leakage current. Meanwhile, the conversion efficiency and the burnout resistance of the back contact battery can be balanced through the duty ratio of the continuous area and the discontinuous area of the second doped semiconductor part filled on the third area, and the applicability of the back contact battery in different application scenes is improved.

As a possible implementation, the second region comprises a first sub-region and a second sub-region. The first sub-region is adjacent to the discontinuous region of the second doped semiconductor portion in the third region, and the region of the second region other than the first sub-region is the second sub-region. The first sub-region is not provided with a second doped semiconductor portion, and the second sub-region is provided with a second doped semiconductor portion.

Under the condition of adopting the technical scheme, the second doped semiconductor part is not arranged on the first sub-zone adjacent to the discontinuous zone, so that the carrier recombination rate at the junction of the second zone and the third zone can be further reduced, and the conversion efficiency of the back contact battery in the forward voltage zone can be improved.

As a possible implementation, the bottom surface height of the first sub-zone is smaller than the bottom surface height of the second sub-zone in the direction from the second face to the first face. In this case, a groove may be disposed in a region (i.e., the first sub-region) where the first doped semiconductor portion and the second doped semiconductor portion are not directly electrically contacted, and the first sub-region and the second doped semiconductor portion are separated by the groove, so that a carrier recombination rate at a junction of the first sub-region and the third region may be further increased, which is beneficial to improving a conversion efficiency of the back contact battery in a forward voltage region.

As a possible implementation, in the width direction of the third region, the first side includes a first connection region, a land region, and a second connection region sequentially and continuously distributed in a direction approaching the second region. The surface of the mesa region is substantially perpendicular to the thickness direction of the semiconductor substrate. The surface of the first connection region and/or the second connection region is arranged vertically or obliquely with respect to the surface of the platform region.

Under the condition of adopting the technical scheme, the first side surface not only comprises the first connecting area and the second connecting area which are parallel to or obliquely arranged in the thickness direction of the semiconductor substrate, but also comprises the platform area which is approximately perpendicular to the thickness direction of the semiconductor substrate, and the existence of the platform area is beneficial to increasing the light absorption area of the first side surface, and can be matched with the edge part of the first doped semiconductor part to change the transmission path of light, so that more light is refracted into the semiconductor substrate, and the double-sided rate of the back contact battery is improved. In addition, the existence of the platform region is favorable for playing a role in highly buffering in the process of forming the surface passivation layer on one side of the first surface, improving the coating of the surface passivation layer on the first side, improving the passivation effect of the surface passivation layer on the first side, reducing the carrier recombination rate and being favorable for improving the photoelectric conversion efficiency of the back contact battery in a forward voltage region.

As a possible implementation, the height of the first connection region is H in the thickness direction of the semiconductor substrate. The width of the land area is W along the width direction of the third area. Wherein H is 0.1 μm or more and 5 μm or less, and/or W is 0.1 μm or more and 8 μm or less, and/or a difference between H and W is 0 μm or more and 3 μm or less.

Under the condition of adopting the technical scheme, the height H of the first connecting region is in the range, so that the formation range of the dielectric barrier layer on the first side surface is prevented from being smaller due to the fact that H is too small, the carrier recombination rate of the semiconductor substrate at the part close to the edge of the first doped semiconductor part is further reduced, in addition, the situation that the part, corresponding to the second region, of the semiconductor substrate is excessively etched due to the fact that the height of the first connecting region is too large can be prevented, the parts of the semiconductor substrate have larger light absorption depth, the light utilization rate of the semiconductor substrate is improved, and the conversion efficiency of the back contact battery is improved.

In addition, the width W of the mesa region is in the above range, which can prevent the weak high buffer effect and the small light absorption area of the mesa region due to the small width of the mesa region, further improve the coating of the surface passivation layer on the first side surface, and improve the double-sided rate of the back contact battery. Second, when the dielectric barrier layer is further disposed on the mesa region, it is also possible to prevent the formation range of the dielectric barrier layer from being small due to the small width W of the mesa region, and reduce the carrier recombination rate at the portion of the semiconductor substrate near the edge of the first doped semiconductor portion. In addition, the widths W of the platform region are larger, so that the widths of the first region and the second region which are positioned at one side of the first surface are smaller, the first doped semiconductor part and/or the second doped semiconductor part and the semiconductor substrate have larger passivation contact area, the collection of carriers is facilitated, and the recombination rate of the carriers is reduced.

As a possible implementation, the surface height of the land area is substantially the same as the surface height of the second area in the direction from the second face to the first face.

Under the condition of adopting the technical scheme, in the actual manufacturing process, after the first doped semiconductor part is formed in the first region, a deposition process is needed to form a dielectric barrier layer which is covered in the whole layer, and then, the dielectric barrier layer is selectively etched to expose at least a second region for manufacturing the second doped semiconductor part. Then, a second doped semiconductor portion is formed. Based on the above, when the surface height of the mesa region is approximately the same as the surface height of the second region, it is indicated that after the dielectric barrier layer is selectively etched, the etchant does not further etch the semiconductor substrate downward, so that a portion of the semiconductor substrate corresponding to the second region has a larger light absorption depth, which is beneficial to improving the light utilization rate of the semiconductor substrate.

As a possible implementation, the dielectric barrier layer is disposed on the first connection region and extends over at least part of the mesa region. In this case, the dielectric barrier layer is formed over a larger range on the first side surface, which is advantageous in reducing the carrier recombination rate at a portion of the semiconductor substrate near the edge of the first doped semiconductor portion.

As a possible implementation, the second connection region is not provided with a dielectric barrier. In this case, it is indicated that the portion corresponding to the second connection region is etched at the portion of the semiconductor substrate in the first sub-region when the second doped semiconductor portion is patterned, which is favorable for completely removing the portion of the second doped semiconductor portion located in the first sub-region, and reducing the carrier recombination rate at the junction between the third region and the first sub-region.

As a possible implementation, the back contact cell further comprises an interface passivation layer. The interface passivation layer is arranged between the second doped semiconductor part, the semiconductor substrate, the dielectric barrier layer and the first doped semiconductor part respectively. The thickness of the dielectric barrier layer is greater than that of the interface passivation layer. Under the condition, the dielectric barrier layer has higher diffusion barrier effect and electrical isolation property, the carrier recombination rate between the part of the semiconductor substrate close to the edge of the first doped semiconductor part and the second doped semiconductor part is reduced, and the conversion efficiency of the back contact battery in a forward voltage region is improved.

As a possible implementation, the dielectric barrier layer comprises a first sub-layer, and a second sub-layer arranged on a side of the first sub-layer facing away from the semiconductor substrate. The second sub-layer and the interface passivation layer are integrally continuous.

Under the condition of adopting the technical scheme, the dielectric barrier layer not only comprises a second sub-layer which is integrally continuous with the interface passivation layer, but also additionally comprises a first sub-layer, thereby being beneficial to enhancing the diffusion barrier effect and the electrical isolation characteristic of the dielectric barrier layer. Meanwhile, the second sub-layer also has a certain electric isolation effect, which is beneficial to reducing the leakage current between the edge part of the first doped semiconductor part and the second doped semiconductor part remained on the first side surface and improving the conversion efficiency of the back contact battery in a forward voltage area.

As a possible implementation, the interface passivation layer is a tunneling oxide layer. In this case, during the process of doping the second doped semiconductor portion located on the interface passivation layer, the dopant will not only diffuse into the interface passivation layer, but also continue to diffuse down into the semiconductor substrate, so that the second doped semiconductor portion has a higher doping concentration and field passivation effect. Based on the above, when the second doped semiconductor part is doped, the dopant can be prevented from entering the part of the semiconductor substrate close to the edge of the first doped semiconductor part (the part is exposed outside) through the second doped semiconductor part and the interface passivation layer, so that the carrier recombination rate of the part of the semiconductor substrate close to the edge of the first doped semiconductor part is reduced, and meanwhile, the edge part of the first doped semiconductor part has higher carrier collection efficiency, thereby being beneficial to improving the conversion efficiency of the back contact battery in a forward voltage region.

As a possible implementation, the surfaces of the first and third regions are textured.

As a possible implementation, at least part of the area surface of the second region is planar.

As a possible implementation, the thickness of the portion of the interface passivation layer located on the third region is smaller than the thickness of the portion of the interface passivation layer located on the second region. In this case, the electrical isolation effect of the interface passivation layer at the portion of the third region is reduced, the magnitude of the reverse leakage current between the first doped semiconductor portion and the second doped semiconductor portion is increased, and the burnout resistance of the back contact battery is improved.

As a possible implementation, in the width direction of the third region, the first doped semiconductor portion further extends in a direction close to the second region and is disposed in a suspended manner above a portion of the second region.

Under the condition of adopting the technical scheme, when the back contact battery provided by the invention is in a working state, light rays are refracted into the semiconductor substrate from one side of the second surface along the direction from the second surface to the first surface. The semiconductor substrate may generate electrons and holes after absorbing photon energy. And, the electron and the hole move towards the direction of the first doped semiconductor part and the second doped semiconductor part respectively, and finally are led out by the corresponding electrode to form photocurrent. The light entering the semiconductor substrate is not completely absorbed and utilized by the semiconductor substrate, and part of the light is refracted out from the first surface side of the semiconductor substrate. In this case, the first doped semiconductor portion located on the first side of the semiconductor substrate further extends in a direction approaching the second region and is suspended above a portion of the second region. At this time, part of light rays refracted out from one side of the first surface of the semiconductor substrate can return to the semiconductor substrate under the reflection action of the end part of the first doped semiconductor part, which is adjacent to the second region and is arranged in a suspending manner, and the light rays are absorbed and utilized by the semiconductor substrate, so that the utilization rate of the back contact battery to the light rays can be increased, and the photoelectric conversion efficiency of the back contact battery in a forward voltage region can be improved.

In a second aspect, the invention provides a photovoltaic module comprising a battery string and an encapsulation layer. The battery string is formed from a plurality of back contact battery electrical connections as provided in the first aspect and various implementations thereof. The encapsulation layer covers the surface of the battery string.

The advantages of the second aspect and various implementations of the present invention may be referred to for analysis of the advantages of the first aspect and various implementations of the first aspect, and will not be described here again.

In a third aspect, the present invention provides a method of manufacturing a back contact battery, the method comprising first providing a semiconductor substrate. The semiconductor substrate includes opposing first and second sides. The first face includes first and second regions alternately spaced apart and a third region located between the first and second regions. And etching the portion of the semiconductor substrate corresponding to the second region so that the bottom surface height of the second region is smaller than the surface heights of the first region and the third region along the direction from the second surface to the first surface. A first side for connection is provided between the third zone and the second zone. Next, a dielectric barrier layer is formed on at least a portion of the first side adjacent to the third region. Next, a second doped semiconductor portion is formed on the first face. The second doped semiconductor portion is disposed on the second region, and at least part of the second doped semiconductor portion extends to cover the dielectric barrier layer and the first doped semiconductor portion in the third region. The second doped semiconductor portion and the first doped semiconductor portion are opposite in doping type, and in the third region, the second doped semiconductor portion and the first doped semiconductor portion are electrically connected.

The advantages of the third aspect and various implementations of the present invention may be referred to for analysis of the advantages of the first aspect and various implementations of the first aspect, and will not be described here again.

Drawings

The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the invention and do not constitute a limitation on the invention. In the drawings:

Fig. 1 is a schematic longitudinal sectional view of a first structure of a back contact battery according to an embodiment of the present invention;

fig. 2 is a schematic longitudinal sectional view of a second structure of a back contact battery according to an embodiment of the present invention;

Fig. 3 is an enlarged schematic view of a structure of a back contact battery at a first side according to an embodiment of the present invention;

fig. 4 is a schematic longitudinal sectional view of a third structure of a back contact battery according to an embodiment of the present invention;

fig. 5 is a schematic longitudinal sectional view of a fourth structure of a back contact battery according to an embodiment of the present invention;

fig. 6 is a schematic diagram showing a distribution of a first doped semiconductor portion and a second doped semiconductor portion in a back contact battery according to an embodiment of the present invention;

Fig. 7 is a schematic longitudinal sectional view of a fifth structure of a back contact battery according to an embodiment of the present invention;

Fig. 8 is a schematic longitudinal sectional view of a sixth structure of a back contact battery according to an embodiment of the present invention;

fig. 9 is a schematic longitudinal sectional view of a seventh structure of a back contact battery according to an embodiment of the present invention;

Fig. 10 is a schematic diagram showing an enlarged structure of a back contact battery at a first side according to an embodiment of the present invention;

Fig. 11 is an enlarged schematic view of a back contact battery at a first side according to an embodiment of the present invention;

fig. 12 is an enlarged schematic view of a structure of a back contact battery at a first side according to an embodiment of the present invention;

fig. 13 is a schematic longitudinal sectional view of an eighth structure of a back contact battery according to an embodiment of the present invention;

fig. 14 is a schematic structural diagram of a back contact battery in a manufacturing process according to an embodiment of the present invention;

Fig. 15 is a schematic diagram of a second structure of a back contact battery in a manufacturing process according to an embodiment of the present invention;

fig. 16 is a schematic diagram III of a structure of a back contact battery in a manufacturing process according to an embodiment of the present invention;

fig. 17 is a schematic diagram showing a structure of a back contact battery in a manufacturing process according to an embodiment of the present invention;

fig. 18 is a schematic diagram showing a structure of a back contact battery in a manufacturing process according to an embodiment of the present invention;

Fig. 19 is a schematic diagram showing a structure of a back contact battery in a manufacturing process according to an embodiment of the present invention;

Fig. 20 is a schematic diagram of a back contact battery according to an embodiment of the present invention in a manufacturing process.

Reference numeral 11 denotes a semiconductor substrate, 12 denotes a first region, 13 denotes a second region, 14 denotes a third region, 15 denotes a first side, 16 denotes a first doped semiconductor portion, 17 denotes a dielectric barrier layer, 18 denotes a second doped semiconductor portion, 19 denotes an interface passivation layer, 20 denotes a first sub-layer, 21 denotes a second sub-layer, 22 denotes a first connection region, 23 denotes a mesa region, 24 denotes a second connection region, 25 denotes a first sub-region, and 26 denotes a second sub-region.

Detailed Description

Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. It should be understood that the description is only illustrative and is not intended to limit the scope of the invention. In addition, in the following description, descriptions of well-known structures and techniques are omitted so as not to unnecessarily obscure the present invention.

Various structural schematic diagrams according to embodiments of the present invention are shown in the accompanying drawings. The figures are not drawn to scale, wherein certain details may have been exaggerated for the purpose of clarity and some details may have been omitted. The shapes of the various regions, layers and relative sizes, positional relationships between them shown in the drawings are merely exemplary, may in practice deviate due to manufacturing tolerances or technical limitations, and one skilled in the art may additionally design regions/layers having different shapes, sizes, relative positions as actually required.

In the context of the present invention, when a layer/element is referred to as being "on" another layer/element, it can be directly on the other layer/element or intervening layers/elements may be present therebetween. In addition, if one layer/element is located "on" another layer/element in one orientation, that layer/element may be located "under" the other layer/element when the orientation is turned. In order to make the technical problems, technical schemes and beneficial effects to be solved more clear, the invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.

Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present invention, the meaning of "a plurality" is two or more, unless explicitly defined otherwise. The meaning of "a number" is one or more than one unless specifically defined otherwise.

In the description of the present invention, unless explicitly stated or limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected, mechanically connected, electrically connected, directly connected, indirectly connected via an intervening medium, or in communication between two elements or in an interaction relationship between two elements. The specific meaning of the above terms in the present invention can be understood by those of ordinary skill in the art according to the specific circumstances.

Currently, solar cells are increasingly used as new energy alternatives. Among them, a photovoltaic solar cell is a device that converts solar light energy into electric energy. Specifically, the solar cell generates carriers by utilizing the photovoltaic principle, and then the carriers are led out by using the electrodes, so that the electric energy can be effectively utilized. When the positive electrode and the negative electrode of the solar cell are positioned on the back of the solar cell, the solar cell is a back contact cell. The front surface of the back contact battery has no influence of shielding by a metal electrode, so the back contact battery has higher short-circuit current I _sc, and is one of the technical directions for realizing the high-efficiency crystalline silicon battery at present.

Specifically, the conventional back contact battery includes at least a semiconductor substrate, and a first doped semiconductor portion and a second doped semiconductor portion formed on partial regions of a back surface side of the semiconductor substrate, respectively. The first doped semiconductor portion and the second doped semiconductor portion are of opposite doping types.

In the actual manufacturing process of the back contact battery, it is necessary to form a first doped semiconductor portion disposed in an entire layer on the back side of the semiconductor substrate, and selectively remove the first doped semiconductor portion in a back partial region. To completely remove the first doped semiconductor portion of the back side portion region, the etching down of the portion of the semiconductor substrate exposed outside the first doped semiconductor portion is continued. After etching, the part of the semiconductor substrate close to the edge of the first doped semiconductor part is directly exposed. In the subsequent process of doping the second doped semiconductor part arranged on the whole layer, the dopant in the second doped semiconductor part is easy to diffuse to the part of the semiconductor substrate close to the edge of the first doped semiconductor part, so that the carrier recombination rate is higher, and the carrier collection efficiency of the edge part of the first doped semiconductor part can be influenced.

In addition, because the first doped semiconductor part is doped with impurities, an etching rate difference exists between the first doped semiconductor part and the semiconductor substrate, and finally, the edge part of the first doped semiconductor part is suspended on the semiconductor substrate after selective etching. In this case, after the first doped semiconductor portion is formed, in the process of forming the second doped semiconductor portion, a second doped semiconductor material layer is formed on the back surface side of the semiconductor substrate, and then the second doped semiconductor material layer located on the first doped semiconductor portion and the back surface partial region is selectively removed, so as to obtain the second doped semiconductor portion. However, the second doped semiconductor material layer filled between the edge portion of the suspended first doped semiconductor portion and the semiconductor substrate is difficult to remove, and the remaining second doped semiconductor material at least electrically connects with the sidewall of the first doped semiconductor portion (or a portion of the semiconductor substrate near the edge of the first doped semiconductor portion), resulting in a higher carrier recombination rate on the back side of the conventional back contact battery, which is not beneficial to improving the conversion efficiency of the back contact battery in the forward voltage region.

In order to solve the technical problems described above, in a first aspect, an embodiment of the present invention provides a back contact battery. As shown in fig. 1, the back contact cell includes a semiconductor substrate 11, a first doped semiconductor portion 16, a second doped semiconductor portion 18, and a dielectric barrier layer 17. The semiconductor substrate 11 includes opposite first and second faces. The first face comprises first and second regions 12, 13 alternately spaced apart, and a third region 14 located between the first and second regions 12, 13. The bottom surface of the second zone 13 is smaller in height than the surfaces of the first zone 12 and the third zone 14 in the direction from the second face to the first face, and a first side 15 for connection is provided between the second zone 13 and the third zone 14. The first doped semiconductor portion 16 is disposed within the first region 12 and the third region 14. A dielectric barrier 17 is provided on at least a portion of the first side 15 adjacent to the third region 14. The second doped semiconductor portion 18 is disposed on the second region 13, and at least a portion of the second doped semiconductor portion 18 extends over the dielectric barrier 17 and the first doped semiconductor portion 16 in the third region 14. The second doped semiconductor portion 18 and the first doped semiconductor portion 16 are of opposite doping types, and in the third region 14, the second doped semiconductor portion 18 and the first doped semiconductor portion 16 are electrically connected.

In the case of adopting the above technical solution, as shown in fig. 1, in the back contact battery provided by the embodiment of the present invention, the surface height of the second region 13 provided with the second doped semiconductor portion 18 is smaller than the surface heights of the first region 12 and the third region 14 provided with the first doped semiconductor portion 16, so that the surfaces of the first region 12 and the third region 14 and the surface of the second region 13 can be staggered along the thickness direction of the semiconductor substrate 11, at this time, in the actual process of manufacturing the back contact battery, after the patterning process is performed on the first doped semiconductor portion 16 provided in the whole layer, it is beneficial to completely remove the first doped semiconductor portion 16 located in the second region 13, so that the second doped semiconductor portion 18 has higher carrier collection efficiency while reducing the carrier recombination rate of the second region 13, and the back contact battery has higher conversion efficiency in the forward voltage region. In addition, the second doped semiconductor portion 18 is not only provided on the second region 13, but at least part of the second doped semiconductor portion 18 is also provided extending over the dielectric barrier 17 and the first doped semiconductor portion 16 located in the third region 14. In addition, in the third region 14, the second doped semiconductor portion 18 and the first doped semiconductor portion 16 with opposite conductivity types may be electrically connected to form a diode structure with a lower reverse breakdown voltage, so as to reduce the reverse breakdown voltage of the back contact battery under the shielding condition, reduce the hot spot risk of the back contact battery, and improve the burnout resistance of the back contact battery. At the same time, the second doped semiconductor portion 18 also extends over a dielectric barrier layer 17 arranged at least between the third region 14 and the second region 13. The dielectric barrier 17 has a certain diffusion barrier effect. Based on this, even in the actual manufacturing process, when the doping treatment is performed on the second doped semiconductor portion 18 provided entirely, the dopant can continue to diffuse downward into the dielectric barrier layer 17 through the second doped semiconductor portion 18, but with the obstruction of the dielectric barrier layer 17, the diffusion of the dopant into the portion of the semiconductor substrate 11 near the edge of the first doped semiconductor portion 16 can be reduced or even prevented, the carrier recombination rate at the portion of the semiconductor substrate 11 near the edge of the first doped semiconductor portion 16 is reduced, and at the same time, the edge portion of the first doped semiconductor portion 16 is made to have a higher carrier collection efficiency. In addition, the existence of the dielectric barrier layer 17 can reduce the magnitude of reverse leakage current, balance the conversion efficiency and the burnout resistance of the back contact battery and improve the working performance of the back contact battery.

In practical application, the material and doping type of the semiconductor substrate in the embodiment of the invention are not particularly limited. The semiconductor substrate may be a silicon substrate, for example. Alternatively, the semiconductor substrate may be a substrate made of any semiconductor material such as a germanium-silicon substrate, a germanium substrate, or a gallium arsenide substrate.

The semiconductor substrate may be a P-type substrate, an N-type substrate, or an intrinsic type substrate in terms of doping type.

In addition, the first surface of the semiconductor substrate corresponds to the backlight surface of the back contact cell, and the second surface of the semiconductor substrate corresponds to the light-facing surface (light-direct irradiation surface) of the back contact cell. Wherein the first surface includes the first region, the second region, and the third region, and the distribution of the first surface may be determined according to the distribution of the first doped semiconductor portion and the second doped semiconductor portion formed at one side of the first surface. Specifically, since the first doped semiconductor portion included in the back contact battery is disposed in the first region and the third region, a distribution range of the first region and the third region on the first surface can be determined according to a distribution requirement of the first doped semiconductor portion in an actual application scene. Since the surface of the second region is recessed into the semiconductor substrate relative to the surfaces of the first and third regions, after the first and third regions are defined, the extent of the second region on the first side can be defined based on the first side of the third region adjacent to the second region as a boundary.

It is understood that the first region generally corresponds to the first emitter region and the second region generally corresponds to the second emitter region, one of the first region and the second region being generally a P region and the other being generally an N region. And at least part of the third area is PN overlapping area.

The second face may be planar in terms of surface topography. Or the second surface of the semiconductor substrate can also be a suede surface so as to improve the light trapping effect of the semiconductor substrate and improve the photoelectric conversion efficiency of the back contact battery. In this case, the shape of the pile structure on the second surface is not particularly limited in the embodiment of the present invention, and may be a pyramid-shaped pile structure, a V-shaped groove-shaped pile structure, or a hole-shaped pile structure.

As for the first side, as shown in fig. 1, the surfaces of the first and third regions 12 and 14 may be textured. In this case, the textured structures are disposed in the respective areas of the surfaces of the first region 12 and the third region 14, which is beneficial to making the first region 12 and the third region 14 have a higher light trapping effect and improving the double-sided rate of the back contact cell. In this case, the surface areas of the first region 12 and the third region 14 may each have substantially the same surface reflectivity.

Or the surfaces of the first and third regions may be planar. In this case, it is advantageous to improve the formation quality and the field passivation effect of the surface passivation layer formed on the side of the first doped semiconductor portion facing away from the semiconductor substrate.

In addition, in the case where the surfaces of the second face, the first region, and the third region are all textured, as shown in fig. 1, the surface reflectivity of the second face may be less than or equal to the surface reflectivity of the first region 12 and the third region 14. For example, in the case where the first region 12, the third region 14, and the second face each have a pyramidal pile structure, the first region 12 and the third region 14 have a one-dimensional size (e.g., bottom side length or diagonal length, side length or height) and/or distribution density that is less than the one-dimensional size and/or distribution density, respectively, of the pyramidal pile structures of the second face.

As for the second region, as shown in fig. 1, at least a partial area surface of the second region 13 may be a plane. In this case, it is advantageous to improve the formation quality and the field passivation effect of the second doped semiconductor portion 18 on the second region 13, and to reduce the carrier recombination rate.

Alternatively, as shown in fig. 2, at least a part of the surface of the second region may be textured to increase the contact area between the second doped semiconductor portion disposed on the second region and the electrode structure, thereby improving the contact performance.

The surface topography of each portion of the second region may be set according to the formation range of the second doped semiconductor portion on the second region and actual requirements, which are not particularly limited herein.

As for the first side, it may be planar or a pile structure may be provided thereon. In addition, at least a part of the region of the first side surface may be parallel to the thickness direction of the semiconductor substrate, or may be inclined to the thickness direction of the semiconductor substrate (the inclination angle may be set according to actual requirements). The angle between the surfaces of the different regions in the first side surface and the thickness direction of the semiconductor substrate may be substantially the same.

Or as shown in fig. 2 and 3, the first side 15 includes a first connection region 22, a land region 23, and a second connection region 24 sequentially and continuously distributed in a direction approaching the second region 13 in the width direction of the third region 14. The surface of the mesa region 23 is substantially perpendicular to the thickness direction of the semiconductor substrate 11. The surface of the first connection region 22 and/or the second connection region 24 is arranged perpendicularly or obliquely with respect to the surface of the land region 23. In this case, the first side 15 includes not only the first connection region 22 and the second connection region 24 disposed parallel or inclined to the thickness direction of the semiconductor substrate 11, but also a mesa region 23 substantially perpendicular to the thickness direction of the semiconductor substrate 11, and the presence of the mesa region 23 is not only beneficial to increasing the light absorption area of the first side 15, but also beneficial to refracting more light into the semiconductor substrate 11 by changing the light transmission path in cooperation with the edge portion of the first doped semiconductor portion 16, thereby improving the double-sided rate of the back contact cell. In addition, the platform region 23 is beneficial to playing a role in highly buffering in the process of forming the surface passivation layer on the first side, improving the coating of the surface passivation layer on the first side 15, improving the passivation effect of the surface passivation layer on the first side 15, reducing the carrier recombination rate and being beneficial to improving the photoelectric conversion efficiency of the back contact battery in a forward voltage region.

Specifically, the included angles between the first connection region and the second connection region and the thickness direction of the semiconductor substrate may be equal or unequal. In addition, the surfaces of the first connection region and the second connection region may be flat surfaces, or the surfaces of the first connection region may be cambered surfaces or the like. The inclination angles and the surface topography of the first connection region and the second connection region may be set according to actual requirements, and are not particularly limited herein.

In addition, it can be understood that the heights of the first connection region and the second connection region in the first side surface, and the angles between the first connection region and the second connection region and the thickness direction of the semiconductor substrate respectively affect the surface height of the second region, and further affect the carrier recombination rate of the edge portion of the first doped semiconductor portion. And secondly, the dielectric barrier layer at least covers the part of the first side surface close to the third area, and the first connecting area and the platform area in the first side surface are closer to the third area, so that the height of the first connecting area, the included angle between the first connecting area and the thickness direction of the semiconductor substrate and the width of the platform area influence the surface area of the first side surface close to the third area and the arrangement range of the dielectric barrier layer, and further influence the carrier recombination of the edge part of the first doped semiconductor part, and therefore, the height of the first connecting area and the second connecting area in the first side surface, the included angle between the first connecting area and the second connecting area and the thickness direction of the semiconductor substrate and the width of the platform area can be determined according to the requirements of the on-flowing recombination rate on the first side surface in the actual application scene, and the method is not particularly limited.

The first connection region is defined to have a height H along a thickness direction of the semiconductor substrate. The width of the land area is W along the width direction of the third area.

Illustratively, H may be 0.1 μm or more and 5 μm or less. For example, H may be 0.1 μm, 0.5 μm, 1 μm, 1.5 μm, 2 μm, 2.5 μm, 3 μm, 3.5 μm, 4 μm, 4.5 μm, or 5 μm, etc. In this case, the height H of the first connection region is within the above-mentioned range, which is advantageous for preventing the formation range of the dielectric barrier layer on the first side surface from being small due to too small H, further reducing the carrier recombination rate at the portion of the semiconductor substrate near the edge of the first doped semiconductor portion, and in addition, it is also possible to prevent the portion of the semiconductor substrate corresponding to the second region from being excessively etched due to too large height of the first connection region, so that each portion of the semiconductor substrate has a larger light absorption depth, improving the light utilization rate of the semiconductor substrate, and being advantageous for improving the conversion efficiency of the back contact battery.

For example, W may be 0.1 μm or more and 8 μm or less. For example, W may be 0.1 μm, 0.5 μm, 1 μm, 1.5 μm, 2 μm, 2.5 μm, 3 μm, 3.5 μm, 4 μm, 4.5 μm,5 μm, 5.5 μm, 6 μm, 7 μm or 8 μm, etc. In this case, the width W of the mesa region is within the above range, so that the mesa region can be prevented from having a weak high buffer effect and a small light absorption area due to the small width of the mesa region, the cladding of the surface passivation layer on the first side surface can be further improved, and the double-sided rate of the back contact battery can be improved. Second, when the dielectric barrier layer is further disposed on the mesa region, it is also possible to prevent the formation range of the dielectric barrier layer from being small due to the small width W of the mesa region, and reduce the carrier recombination rate at the portion of the semiconductor substrate near the edge of the first doped semiconductor portion. In addition, the widths W of the platform region are larger, so that the widths of the first region and the second region which are positioned at one side of the first surface are smaller, the first doped semiconductor part and/or the second doped semiconductor part and the semiconductor substrate have larger passivation contact area, the collection of carriers is facilitated, and the recombination rate of the carriers is reduced.

For example, the difference between H and W may be 0 or more and 3 μm or less. For example, the difference between H and W may be 0, 0.2 μm, 0.5 μm, 1 μm, 1.5 μm, 2 μm, 2.5 μm, 2.8 μm, 3 μm, etc. The principle of application of the beneficial effects in this case may refer to the principle of application of the beneficial effects that H may be 0.1 μm or more and 5 μm or less and W may be 0.1 μm or more and 8 μm or less, which are described above, and will not be repeated here.

In terms of the surface setting height, as shown in fig. 1, the surface height of the second region 13 is smaller than the surface heights of the first region 12 and the third region 14 in the direction from the second face to the first face. The difference in height between the second region 13 and the first region 12 and the third region 14, respectively, may be determined according to the carrier recombination rate for the second region 13, the carrier collection efficiency for the second doped semiconductor portion 18, and the requirements of the light absorption depth of the semiconductor substrate 11 at the second region 13 portion in the practical application scenario, and is not particularly limited herein.

For example, in the case where the first side includes the above-described first connection region, land region, and second connection region, the surface height of the land region may be substantially the same as the surface height of the second region in the direction from the second face to the first face.

Alternatively, as shown in fig. 2, the surface height of the land area may be substantially the same as the surface height of the second area 13 in the direction from the second face to the first face. In this case, in an actual manufacturing process, after the first doped semiconductor portion 16 is formed in the first region 12, a deposition process is required to form an overall layer of the dielectric barrier layer 17, and then, the dielectric barrier layer 17 is selectively etched to expose at least the second region 13 for manufacturing the second doped semiconductor portion 18. Next, the second doped semiconductor portion 18 is formed. Based on this, when the surface height of the mesa region is substantially the same as the surface height of the second region 13, it is shown that after the selective etching of the dielectric barrier layer 17, the etchant does not further etch down the semiconductor substrate 11, so that a portion of the semiconductor substrate 11 corresponding to the second region 13 has a larger light absorption depth, which is beneficial to improving the light utilization rate of the semiconductor substrate 11.

For the first doped semiconductor portion, the doping type of the first doped semiconductor portion may be N-type, and the doping type of the second doped semiconductor portion may be P-type. Or the doping type of the first doped semiconductor part can be P type, and the doping type of the second doped semiconductor part is N type.

In terms of the arrangement position, as shown in fig. 1, the first doped semiconductor portion 16 may be arranged only in the first region 12 and the third region 14.

Alternatively, as shown in fig. 4, in the width direction of the third region 14, the first doped semiconductor portion 16 may also extend in a direction approaching the second region 13 and be disposed in a suspended manner above a portion of the second region 13. In this case, in the working state of the back contact battery provided in the embodiment of the present invention, light is refracted into the semiconductor substrate 11 from the side of the second surface along the direction from the second surface to the first surface. The semiconductor substrate 11 may generate electrons and holes after absorbing photon energy. The electrons and holes move in the directions of the first doped semiconductor portion 16 and the second doped semiconductor portion 18, respectively, and are finally guided out by the corresponding electrodes, thereby forming photocurrents. The light entering the semiconductor substrate 11 is not completely absorbed and utilized by the semiconductor substrate 11, and some light is refracted out from the first surface side of the semiconductor substrate 11. In this case, the first doped semiconductor portion 16, which is located on the first surface side of the semiconductor substrate 11, also extends in a direction approaching the second region 13 and is disposed in a suspended manner above a portion of the second region 13. At this time, part of the light refracted out from the first surface side of the semiconductor substrate 11 can be returned to the semiconductor substrate 11 under the reflection effect of the end portion of the first doped semiconductor portion 16 adjacent to the second region 13 and suspended, and absorbed and utilized by the semiconductor substrate 11, so that the light utilization rate of the back contact battery can be increased, and the photoelectric conversion efficiency of the back contact battery in the forward voltage region can be improved.

The length of the portion of the first doped semiconductor portion extending and suspended above the portion of the second region may be set according to practical requirements, which is not specifically limited herein.

For the second doped semiconductor portion, the material of the second doped semiconductor portion may include any semiconductor material such as silicon, silicon germanium, or gallium arsenide. The crystal phase of the second doped semiconductor portion may be amorphous, microcrystalline, nanocrystalline, monocrystalline, polycrystalline, or the like in terms of the arrangement form of the substances.

In terms of the arrangement position, the second doped semiconductor portion may be formed directly on the second region of the semiconductor substrate, as well as the dielectric barrier layer and the first doped semiconductor portion located in the third region. Alternatively, as shown in fig. 5, the back contact cell further comprises an interface passivation layer 19. The interface passivation layer 19 is disposed between the second doped semiconductor portion 18, the semiconductor substrate 11, the dielectric barrier layer 17 and the first doped semiconductor portion 16, respectively. The thickness of the dielectric barrier layer 17 is greater than the thickness of the interface passivation layer 19. In this case, the dielectric barrier layer 17 has higher diffusion barrier effect and electrical isolation property, so that the carrier recombination rate between the part of the semiconductor substrate 11 near the edge of the first doped semiconductor portion 16 and the second doped semiconductor portion 18 is reduced, and the conversion efficiency of the back contact battery in the forward voltage region is improved.

Specifically, the material of the interface passivation layer may be determined according to the material of the second doped semiconductor portion and the kind of the selective contact structure formed by the interface passivation layer and the second doped semiconductor portion in the actual application scenario, which is not specifically limited herein.

For example, when the second doped semiconductor portion is a doped polysilicon layer, the interface passivation layer is a tunneling passivation layer. The tunneling passivation layer may be made of silicon oxide, aluminum oxide, titanium oxide, or the like.

For another example, when the material of the second doped semiconductor portion may include at least one of doped amorphous silicon layer, doped nanocrystalline silicon, and doped microcrystalline silicon, the material of the interface passivation layer may include at least one of intrinsic amorphous silicon, intrinsic nanocrystalline silicon, and intrinsic microcrystalline silicon.

Optionally, the first doped semiconductor portion is a P-type doped region disposed in the first region. The second doped semiconductor portion is an N-type doped polysilicon layer disposed on the second region, and the interface passivation layer is a tunnel oxide layer.

Additionally, the thickness of portions of the interface passivation layer may optionally be approximately the same. Or the thickness of the portion of the interface passivation layer located on the third region may be smaller than the thickness of the portion of the interface passivation layer located on the second region. In this case, the electrical isolation effect of the interface passivation layer at the portion of the third region is reduced, the magnitude of the reverse leakage current between the first doped semiconductor portion and the second doped semiconductor portion is increased, and the burnout resistance of the back contact battery is improved.

As for the specific coverage of the second doped semiconductor portion on the first surface, the specific coverage may be determined according to the conversion efficiency and the hot spot risk of the back contact battery in the practical application scenario, and is not specifically limited herein.

The second doped semiconductor portions may be continuously distributed along the length direction of the third region and over the third region. Alternatively, as shown in fig. 6, the second doped semiconductor portions 18 may be intermittently distributed along the length of the third region 14 and over the third region 14. At this time, on the third region 14, the second doped semiconductor portion 18 includes a continuous region and a discontinuous region. In this case, it is advantageous to reduce the magnitude of the reverse leakage current. Meanwhile, the conversion efficiency and the burnout resistance of the back contact battery can be balanced by filling the duty ratio of the continuous area and the discontinuous area of the second doped semiconductor part 18 on the third area 14, so that the applicability of the back contact battery in different application scenes can be improved.

When the second doped semiconductor portions are intermittently distributed along the length direction of the third region and over the third region, the second region is defined to include a first sub-region and a second sub-region. The first sub-region is adjacent to the discontinuous region of the second doped semiconductor portion in the third region, and the region of the second region other than the first sub-region is the second sub-region. Wherein, as shown in fig. 7, the first sub-region 25 and the second sub-region 26 may each be provided with the second doped semiconductor portion 18. Or as shown in fig. 4, the second doped semiconductor portion 18 is not provided on the first sub-region 25, and the second doped semiconductor portion 18 is provided on the second sub-region 26.

It is noted that the second doped semiconductor portion is not arranged on the first sub-region adjacent to the discontinuous region, so that the carrier recombination rate at the junction of the second region and the third region can be further reduced, and the conversion efficiency of the back contact battery in the forward voltage region can be improved.

When the second doped semiconductor portion is not disposed on the first sub-region, as shown in fig. 8 and 9, the surface of the first sub-region 25 may be flush with the surface of the second sub-region 26, and then the dielectric barrier layer 17, or the dielectric barrier layer 17 and the interface passivation layer 19, may be disposed on the first sub-region 25.

Alternatively, as shown in fig. 4, the bottom surface of the first sub-area 25 may have a height smaller than the bottom surface of the second sub-area 26 in the direction from the second face to the first face. In this case, a groove may be disposed in a region (i.e., the first sub-region 25) where the first doped semiconductor portion 16 and the second doped semiconductor portion 18 are not directly electrically contacted, and the first sub-region 25 and the second sub-region 14 are separated by the groove, so that the carrier recombination rate at the junction of the first sub-region 25 and the third region 14 can be further increased, which is beneficial to improving the conversion efficiency of the back contact battery in the forward voltage region. In this case, the bottom surface of the first sub-area 25 may be a flat surface or a textured surface.

Wherein, in the case that the first region, the third region and the first sub-region are pile surfaces, the one-dimensional dimensions of the pile structures in the first region and the third region may be the same as or different from the one-dimensional dimensions of the pile structures in the first sub-region.

Optionally, the size uniformity and/or distribution uniformity of the pile structures in the first and third regions may be greater than the size uniformity and/or distribution uniformity of the pile structures in the first sub-region. And/or the surface reflectivity of the pile areas in the first and third areas may be smaller than the surface reflectivity of the first sub-area. And/or the lateral dimensions of the pile structures in the first and third regions (the lateral dimensions being substantially perpendicular to the thickness direction of the semiconductor substrate; for example, when the pile structures are pyramid-shaped pile structures, the lateral dimensions may be the bottom side or diagonal length) may be smaller than the lateral dimensions of the pile structures in the first sub-region. Under the condition, the etching degree of etching liquid for implementing the texturing treatment is higher in the first subarea corresponding to the semiconductor substrate, so that the carrier recombination rate is further reduced, and the conversion efficiency of the back contact battery in a forward voltage area can be improved.

In addition, in the case where both the second face and the first sub-area are pile faces, the one-dimensional size of the pile structures in the second face and the one-dimensional size of the pile structures in the first sub-area may be the same or different.

Optionally, the size uniformity and/or distribution uniformity of the pile structures in the second face may be greater than the size uniformity and/or distribution uniformity of the pile structures in the first sub-zone. And/or the surface reflectivity of the pile area in the second face may be smaller than the surface reflectivity of the first sub-area. And/or the lateral dimension of the pile structures in the second face (the lateral dimension being substantially perpendicular to the thickness direction of the semiconductor substrate) may be smaller than the lateral dimension of the pile structures in the first sub-region. The advantages in this case are referred to above and will not be described here.

For the dielectric barrier layer, the material and thickness of the dielectric barrier layer are not particularly limited, so long as the dielectric barrier layer has a diffusion barrier function. The dielectric barrier layer may have a single-layer structure, and may have a stacked structure formed of a plurality of materials.

For example, as shown in fig. 10, in case the back contact cell further comprises an interface passivation layer 19, the dielectric barrier layer 17 may comprise a first sub-layer 20, and a second sub-layer 21 arranged on a side of the first sub-layer 20 facing away from the semiconductor substrate 11. The second sub-layer 21 and the interface passivation layer 19 are integrally continuous. In this case, the dielectric barrier layer 17 includes not only the second sub-layer 21 integrally continuous with the interface passivation layer 19, but also the first sub-layer 20 in addition, which is advantageous in enhancing its diffusion barrier effect and electrical isolation characteristics. In addition, the dielectric barrier layer 17 comprises a passivated second sub-layer 21, which can at least reduce the carrier recombination rate at the part of the first side surface 15 near the third region 14, and meanwhile, the second sub-layer 21 has a certain electric isolation effect, which is beneficial to reducing the leakage current between the edge part of the first doped semiconductor part 16 and the second doped semiconductor part 18 remained on the first side surface 15 and improving the conversion efficiency of the back contact battery in the forward voltage region.

As regards the material and thickness of the first sub-layer, this may be set according to practical requirements. The material of the first sub-layer may be the same as or different from the material of the second sub-layer.

In addition, the dielectric barrier layer may be an insulating dielectric layer. Under the condition, the dopant in the second doped semiconductor part can be prevented from diffusing to the part of the semiconductor substrate close to the edge of the first doped semiconductor part through the dielectric barrier layer, the part of the semiconductor substrate close to the edge of the first doped semiconductor part can be electrically insulated from the second doped semiconductor part through the dielectric barrier layer, leakage current is prevented from being formed between the part of the semiconductor substrate close to the edge of the first doped semiconductor part and the second doped semiconductor part, the carrier recombination rate is reduced to a large extent, and the conversion efficiency of the back contact battery in a forward voltage region is improved.

Or the dielectric barrier layer may be a semi-insulating dielectric layer having only a diffusion barrier effect.

Illustratively, the dielectric barrier layer may include a silicon oxide layer and/or a silicon nitride layer, etc.

In addition, the formation range of the dielectric barrier layer on the first side surface may be determined according to the morphology of the first side surface and the requirement of the carrier recombination rate of the edge portion of the first doped semiconductor portion in the practical application scenario, which is not specifically limited herein.

Alternatively, as shown in fig. 1, the dielectric barrier 17 may be provided only on a portion of the first side 15 adjacent to the third region 14.

For example, in the case where the first side includes a first connection region, a mesa region, and a second connection region, as shown in fig. 10, the dielectric barrier 17 may be disposed only on the first connection region 22. Alternatively, as shown in fig. 11, the dielectric barrier 17 may be disposed only on the mesa region 23. As shown in fig. 12, the dielectric barrier 17 is disposed on the first connection region 22 and extends to cover at least a portion of the mesa region 23. In this case, the formation range of the dielectric barrier layer 17 on the first side face 15 is made larger, which is advantageous in reducing the carrier recombination rate at the portion of the semiconductor substrate 11 near the edge of the first doped semiconductor portion 16.

In addition, optionally, as shown in fig. 10 to 12, the dielectric barrier layer 17 is not disposed on the second connection region 24. In this case, it is shown that the portion of the second connection region 24 corresponding to the portion of the semiconductor substrate 11 at the first sub-region 25 is etched during the patterning of the second doped semiconductor portion 18, which is advantageous for completely removing the portion of the second doped semiconductor portion 18 at the first sub-region 25, and reducing the carrier recombination rate at the interface between the third region 14 and the first sub-region 25

Alternatively, as shown in fig. 13, the dielectric barrier 17 may also extend between a portion of the first doped semiconductor portion 16 and a portion of the second doped semiconductor portion 18 located in the third region 14 in a direction away from the second region 13. In this case, it is ensured that the dielectric barrier layer 17 can cover the portion of the first side surface 15 near the third region 14, so that the difficulty in patterning the dielectric barrier layer 17 is reduced, and meanwhile, the magnitude of the reverse leakage current can be further reduced, and the conversion efficiency of the back contact battery in the forward voltage region is improved. In this case, the width of the dielectric barrier layer 17 on the third region 14 may be determined according to the accuracy of patterning process and the requirements for the conversion efficiency and the risk of hot spots of the back contact cell, and is not particularly limited herein.

Illustratively, the ratio of the width of the dielectric barrier layer located on the third region to the width of the third region may be greater than or equal to 0.1 and less than or equal to 0.8. In this case, the ratio of the width of the dielectric barrier layer located on the third region to the width of the third region is within the above range, so that the difficulty in patterning the dielectric barrier layer due to the smaller ratio can be prevented, and the yield of the back contact battery can be improved. And the reverse leakage current between the first doped semiconductor part and the second doped semiconductor part is prevented from flowing little when the back contact battery is shielded due to the overlarge ratio, so that the burning resistance of the back contact battery is improved.

Illustratively, the dielectric barrier layer on the third region may have a width of 20 μm or more and 400 μm or less. For example, the width of the dielectric barrier layer located on the third region may be 20 μm, 50 μm, 80 μm, 100 μm, 120 μm, 150 μm, 200 μm, 300 μm, 400 μm, or the like. The application principle of the beneficial effects in this case may refer to the application principle of the beneficial effects that the ratio of the width of the dielectric barrier layer located on the third region to the width of the third region is greater than or equal to 0.1 and less than or equal to 0.8, which is not described herein.

In a second aspect, an embodiment of the invention provides a photovoltaic module comprising a battery string and an encapsulation layer. The battery string is formed from a plurality of back contact battery electrical connections as provided in the first aspect and various implementations thereof. The encapsulation layer covers the surface of the battery string.

The beneficial effects of the second aspect and various implementations of the embodiments of the present invention may refer to the beneficial effect analysis in the first aspect and various implementations of the first aspect, which are not described herein.

In a third aspect, embodiments of the present invention provide a method for manufacturing a back contact battery. Hereinafter, a manufacturing process will be described based on cross-sectional views of the operations shown in fig. 14 to 20. Specifically, the manufacturing method of the back contact battery comprises the following steps:

First, a semiconductor substrate is provided. The semiconductor substrate includes opposing first and second sides. The first face includes first and second regions alternately spaced apart and a third region located between the first and second regions.

The material of the semiconductor substrate and the distribution ranges of the first region, the second region and the third region in the first surface may be referred to the foregoing, and will not be repeated herein.

It will be appreciated that the surface topography of the first region may be different and the process of forming the first doped semiconductor portion in the first region and the third region of the semiconductor substrate may be different.

For example, if the first region is planar, after providing the semiconductor substrate with the first plane, a subsequent formation operation of the first doped semiconductor portion may be directly performed.

For example, as shown in fig. 14, if the first region 12 and the third region 14 are textured, at least the first surface side of the semiconductor substrate 11 may be subjected to a texturing process before the first doped semiconductor portion 16 is formed.

Next, as shown in fig. 15 and 16, a first doped semiconductor portion 16 is formed in the first region 12 and the third region 14, and a portion of the semiconductor substrate 11 corresponding to the second region 13 is etched so that a surface height of the second region 13 is smaller than a surface height of the first region 12 and the third region 14 in a second face-to-first face direction. A first side 15 for connection is provided between the third zone 14 and the second zone 13.

In the actual manufacturing process, as shown in fig. 15, the first surface may be doped by a doping process such as diffusion or ion implantation, and the first doped semiconductor portion 16 may be formed on the first surface. Next, as shown in fig. 16, the first doped semiconductor portion 16 located in the second region 13 may be selectively removed using a wet etching or a laser etching or the like. Specifically, the mask layer used in the selective etching process may be a doped silicon glass layer formed by performing a heat treatment on the portion of the doped silicon glass layer located in the second region 13 during the doping treatment on the first doped semiconductor portion 16, so that the compactness of the doped silicon glass layer located in the second region 13 is degraded, the corrosion resistance is poor, and the portions of the doped silicon glass layer located in the first region 12 and the third region 14 form the mask layer. Alternatively, after the doped silicon glass layer is removed, or a mask layer is additionally formed directly on the doped silicon glass layer, at least the mask layer may be subjected to patterning treatment to expose the first doped semiconductor portion 16 located in the second region 13.

After the selective etching is performed on the first doped semiconductor portion, the second region of the semiconductor substrate may be continuously etched under the protection of the same mask layer, so that the surface height of the second region is smaller than the surface heights of the first region and the third region along the direction from the second surface to the first surface. It should be noted that, since the first doped semiconductor portion is doped with the dopant, the etching rate of the first doped semiconductor portion and the etching rate of the semiconductor substrate by the etchant may be different, and thus after etching the portions of the first doped semiconductor portion and the semiconductor substrate located in the second region, the edge portion of the first doped semiconductor portion may overhang a portion of the second region.

Next, as shown in fig. 17 and 18, a dielectric barrier layer 17 is formed which is provided at least on a portion of the first side surface 15 near the third region 14.

In the actual manufacturing process, physical vapor deposition can be adopted to form a dielectric barrier layer which is arranged in a whole layer. A laser etch or the like may then be used to remove the dielectric barrier layer over the first region, at least a portion of the second region, and at least a portion of the third region. The range of the dielectric barrier layer can be determined according to the precision of the etching process in the practical application scene, and the forming range and the electrical connection relation of the first doped semiconductor portion and the second doped semiconductor portion, which are not particularly limited herein.

Next, as shown in fig. 19, the second doped semiconductor portion 18 is formed. The second doped semiconductor portion 18 is disposed on the second region 13, and at least a portion of the second doped semiconductor portion 18 extends over the dielectric barrier 17 and the first doped semiconductor portion 16 in the third region 14. The second doped semiconductor portion 18 and the first doped semiconductor portion 16 are of opposite doping types, and in the third region 14, the second doped semiconductor portion 18 and the first doped semiconductor portion 16 are electrically connected.

In an actual manufacturing process, a physical vapor deposition process or the like may be used to form the entire layer of the disposed and second doped semiconductor portion. Then, as shown in fig. 19, an etching process is used to selectively remove at least the second doped semiconductor portion 18 located on the first region 12. Since the dielectric barrier layer 17 is formed before the second doped semiconductor portion 18 is formed. The dielectric barrier 17 formed in advance can prevent the etchant from entering into the portion of the semiconductor substrate 11 around the edge of the third region 14 during the process of manufacturing the second doped semiconductor portion 18, and can isolate the second doped semiconductor portion 18 from the portion of the semiconductor substrate 11 around the edge of the third region 14 after the second doped semiconductor portion 18 is formed, thereby reducing the carrier recombination rate. For the specific formation range of the second doped semiconductor portion 18, reference is made to the foregoing, and no further description is given here.

In the case where the back contact battery further includes an interface passivation layer, the interface passivation layer is formed by a thermal oxidation or chemical vapor deposition process before the second doped semiconductor portion is formed.

Next, as shown in fig. 20, if the second doped semiconductor portion is not disposed on the first sub-region 25 and the surface height of the first sub-region 25 is smaller than the surface height of the second sub-region 26, a wet etching process is used to etch a portion of the first sub-region 25 of the semiconductor substrate 11, so that the surface of the first sub-region 25 is recessed into the semiconductor substrate 11 relative to the surface of the second sub-region 26, respectively.

The beneficial effects of the third aspect and various implementations of the embodiments of the present invention may refer to the beneficial effect analysis in the first aspect and various implementations thereof, which are not described herein.

In the above description, technical details of patterning, etching, and the like of each layer are not described in detail. Those skilled in the art will appreciate that layers, regions, etc. of the desired shape may be formed by a variety of techniques. In addition, to form the same structure, those skilled in the art can also devise methods that are not exactly the same as those described above. In addition, although the embodiments are described above separately, this does not mean that the measures in the embodiments cannot be used advantageously in combination.

The embodiments of the present invention are described above. These examples are for illustrative purposes only and are not intended to limit the scope of the present invention. The scope of the invention is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be made by those skilled in the art without departing from the scope of the invention, and such alternatives and modifications are intended to fall within the scope of the invention.

Claims (17)

1. A back contact battery, characterized in that it comprises: A semiconductor substrate includes a first surface and a second surface opposite to each other; the first surface includes an alternately spaced first region and a second region, and a third region located between the first region and the second region; along the direction from the second surface to the first surface, the bottom surface height of the second region is less than the surface height of the first region and the third region, and a first side surface for connection is provided between the second region and the third region; A first doped semiconductor portion is disposed within the first region and the third region; A dielectric barrier layer is disposed at least on the portion of the first side near the third region; A second doped semiconductor portion is disposed on the second region, and at least a portion of the second doped semiconductor portion extends and covers the dielectric barrier layer and the first doped semiconductor portion located in the third region; the doping types of the second doped semiconductor portion and the first doped semiconductor portion are opposite, and in the third region, the second doped semiconductor portion and the first doped semiconductor portion are electrically connected. 2. The back contact battery according to claim 1, wherein, along a direction away from the second region, the dielectric barrier layer further extends between a portion of the first doped semiconductor portion and a portion of the second doped semiconductor portion located in the third region. 3. The back contact battery according to claim 2, wherein the ratio of the width of the dielectric barrier layer located on the third region to the width of the third region is greater than or equal to 0.1 and less than or equal to 0.8; And/or, the width of the dielectric barrier layer located on the third region is greater than or equal to 20 μm and less than or equal to 400 μm. 4. The back contact battery according to claim 1, wherein the dielectric barrier layer is an insulating dielectric layer. 5. The back contact battery according to claim 1, characterized in that, along the length direction of the third region, and on the third region, the second doped semiconductor portion is discontinuously distributed. 6. The back contact battery according to claim 5, wherein the second region comprises a first sub-region and a second sub-region; the first sub-region is adjacent to the discontinuity region of the second doped semiconductor portion located in the third region, and the region in the second region other than the first sub-region is the second sub-region; The first sub-region does not have the second doped semiconductor portion, while the second sub-region has the second doped semiconductor portion. 7. The back contact battery according to claim 6, wherein, along the direction from the second surface to the first surface, the bottom surface height of the first sub-region is less than the bottom surface height of the second sub-region. 8. The back contact battery according to any one of claims 1 to 7, characterized in that, in the width direction of the third region, the first side surface includes a first connection region, a platform region, and a second connection region that are sequentially and continuously distributed along the direction close to the second region; the surface of the platform region is substantially perpendicular to the thickness direction of the semiconductor substrate; the surfaces of the first connection region and/or the second connection region are arranged perpendicularly or obliquely relative to the surface of the platform region. 9. The back contact battery according to claim 8, characterized in that, along the thickness direction of the semiconductor substrate, the height of the first connection region is H; along the width direction of the third region, the width of the platform region is W; wherein, H is greater than or equal to 0.1 μm and less than or equal to 5 μm; and/or, W is greater than or equal to 0.1 μm and less than or equal to 8 μm; and/or, the difference between H and W is greater than or equal to 0 and less than or equal to 3 μm; And/or, along the direction from the second surface to the first surface, the surface height of the platform area is approximately the same as the surface height of the second area. 10. The back contact battery according to claim 8, wherein the dielectric barrier layer is disposed on the first connection region and extends to cover at least a portion of the platform region; And/or, the second connection area is not provided with the aforementioned medium barrier layer. 11. The back contact battery according to claim 1, wherein the back contact battery further comprises an interface passivation layer; the interface passivation layer is disposed in a second doped semiconductor portion, which is located between the semiconductor substrate, the dielectric barrier layer and the first doped semiconductor portion; The thickness of the dielectric barrier layer is greater than the thickness of the interface passivation layer. 12. The back contact battery according to claim 11, wherein the dielectric barrier layer comprises a first sub-layer and a second sub-layer disposed on the side of the first sub-layer facing away from the semiconductor substrate; The second sub-layer and the interface passivation layer are integral and continuous. 13. The back contact battery according to claim 11, wherein the interface passivation layer is a tunneling oxide layer. 14. The back contact battery according to claim 11, wherein the surfaces of the first region and the third region are textured; And/or, at least a portion of the surface of the second region is planar; And/or, the thickness of the portion of the interface passivation layer located on the third region is less than the thickness of the portion of the interface passivation layer located on the second region. 15. The back contact battery according to claim 1, wherein, in the width direction of the third region, the first doped semiconductor portion extends further along a direction close to the second region and is suspended above a portion of the second region. 16. A photovoltaic module, characterized in that it comprises: A battery string, wherein the battery string is formed by electrically connecting a plurality of back-contact batteries as described in any one of claims 1 to 15; And an encapsulation layer that covers the surface of the battery string. 17. A method for manufacturing a back contact battery, characterized in that it comprises: A semiconductor substrate is provided; the semiconductor substrate includes a first surface and a second surface opposite to each other; the first surface includes a first region and a second region that are alternately distributed, and a third region located between the first region and the second region; A first doped semiconductor portion is formed in the first region and the third region; and the portion of the semiconductor substrate corresponding to the second region is etched so that the bottom surface height of the second region is less than the surface height of the first region and the third region along the direction from the second surface to the first surface; a first side surface for connection is provided between the third region and the second region; A dielectric barrier layer is formed at least on the portion of the first side near the third region; A second doped semiconductor portion is formed on a first surface; the second doped semiconductor portion is disposed on the second region, and at least a portion of the second doped semiconductor portion extends to cover the dielectric barrier layer and the first doped semiconductor portion located in the third region; the doping types of the second doped semiconductor portion and the first doped semiconductor portion are opposite, and in the third region, the second doped semiconductor portion and the first doped semiconductor portion are electrically connected.