CN120915265A - Resonator with induced charge trapping defect structure and preparation method thereof - Google Patents
Resonator with induced charge trapping defect structure and preparation method thereofInfo
- Publication number
- CN120915265A CN120915265A CN202511430987.5A CN202511430987A CN120915265A CN 120915265 A CN120915265 A CN 120915265A CN 202511430987 A CN202511430987 A CN 202511430987A CN 120915265 A CN120915265 A CN 120915265A
- Authority
- CN
- China
- Prior art keywords
- layer
- defect
- depositing
- defect structure
- etching
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Piezo-Electric Or Mechanical Vibrators, Or Delay Or Filter Circuits (AREA)
Abstract
本发明公开了一种具有感应电荷捕获缺陷结构的谐振器及制备方法，具体涉及第三代半导体技术与射频前端器件技术领域，采用多步骤清洗去除污染与氧化层，沉积多层缺陷梯度结构控制电荷迁移，构建牺牲层形成空腔基础，沉积支撑层提升结构稳定性，叠加高导电电极与优质压电层，精准刻蚀释放空腔结构；本发明，通过高纯度预处理去除有机物和氧化残留，增强沉积层与衬底结合，构建多层缺陷梯度硅结构抑制感应电荷迁移，引入稳定支撑层防止结构塌陷，沉积高导电与高压电复合层提升激发效率与频率响应，协同匹配层厚与缺陷密度增强能量转化效率，采用高选择性腐蚀体系释放空腔，实现高频下损耗抑制与品质因数提升。
This invention discloses a resonator with an induced charge trapping defect structure and its fabrication method, specifically relating to the fields of third-generation semiconductor technology and radio frequency front-end device technology. The method employs a multi-step cleaning process to remove contaminants and oxide layers, deposits a multi-layer defect gradient structure to control charge migration, constructs a sacrificial layer to form a cavity base, deposits a support layer to improve structural stability, superimposes a highly conductive electrode and a high-quality piezoelectric layer, and precisely etches to release the cavity structure. This invention removes organic matter and oxide residues through high-purity pretreatment, enhances the bonding between the deposited layer and the substrate, constructs a multi-layer defect gradient silicon structure to suppress induced charge migration, introduces a stable support layer to prevent structural collapse, deposits a highly conductive and high-voltage composite layer to improve excitation efficiency and frequency response, synergistically matches layer thickness and defect density to enhance energy conversion efficiency, and uses a highly selective etching system to release the cavity, achieving loss suppression and quality factor improvement at high frequencies.
Description
Technical Field
The invention relates to the technical field of third-generation semiconductor technology and radio frequency front-end devices, in particular to a resonator with an induced charge trapping defect structure and a preparation method thereof.
Background
With the extension of the fifth generation mobile communication technology to a high frequency band, the evolution of an intelligent radar system to high-precision detection and the large-scale deployment of terminal equipment of the internet of things, the radio frequency front-end device is facing unprecedented performance challenges. The transmission of high-frequency signals puts near-severe demands on the energy conversion efficiency of the device, and how to effectively control the energy loss while maintaining the high-frequency stability of the traditional bulk acoustic wave device has become a key bottleneck for restricting the development of the industry. Particularly in the emerging application scenes such as millimeter wave communication, internet of vehicles sensing and the like, the device needs to realize low insertion loss, high power bearing and excellent thermal stability in a complex electromagnetic environment, and the device brings higher dimensional technical requirements to material interface engineering.
The current mainstream film bulk acoustic resonators expose significant physical limitations under high frequency conditions, with core contradictions focused on interface defect effects between the piezoelectric layer and the substrate. Because of the inherent lattice adaptation difference between heterogeneous materials, dislocation networks formed during epitaxial growth become active channels of parasitic charges, and these defect states induce multiple energy dissipation mechanisms under the action of high-frequency alternating electric fields. More seriously, the prior defect control technology often falls into the dilemma of performance compromise, namely, the buffer layer structure can improve the interface quality, but introduces an additional dielectric loss path, and the surface passivation treatment can inhibit charge migration, but can cause nonlinear degradation of piezoelectric response. This technical paradox severely limits the feasibility of the new generation communication system to expand to higher frequency bands;
In the prior art, interface defects are easily caused by residual pollution in the cleaning of a substrate, a charge migration path is uncontrolled, the induced loss is aggravated, the insertion loss and the Q value are aggravated, the thickness of a supporting layer and a sacrificial layer are difficult to control, the boundary of a release cavity is easy to damage, the differential pressure electric response of electrode conductivity is insufficient, high-frequency signal distortion is serious, the etching scheme has poor selectivity, the damage rate of a microstructure is high, the consistency and the packaging stability of a device are affected, the frequency drift is obviously increased, and the service life is shortened to limit high-frequency application.
Disclosure of Invention
The main objective of the present invention is to provide a resonator with induced charge trapping defect structure and a method for manufacturing the same, which can effectively solve the problems involved in the above-mentioned background art.
In order to achieve the above purpose, the technical scheme adopted by the invention is as follows:
a method for preparing a resonator with an induced charge trapping defect structure, wherein the film body is applied to an acoustic wave resonator or a filter, and comprises the following steps:
S1, cleaning a substrate, namely selecting a surface silicon wafer as a silicon substrate, firstly cleaning the silicon substrate by using acetone to remove organic pollutants on the surface of the silicon substrate, then rinsing the silicon substrate by using isopropanol or deionized water, then removing a surface natural oxide layer by using hydrofluoric acid solution, thoroughly flushing the silicon substrate by using deionized water after washing, and drying the silicon substrate by using nitrogen;
s2, depositing a multi-layer defect structure, namely sequentially depositing the multi-layer defect structure on the silicon substrate cleaned in the step S1, wherein the defect densities of the multi-layer defect structure are different, so that the defect densities of the multi-layer defect structure form gradient distribution;
S3, depositing a sacrificial layer, and depositing the sacrificial layer on the surface of the multi-layer defect structure;
S4, cavity etching is released, the sacrificial layer is removed in a dry etching mode and a wet etching mode to form a cavity structure, and etching gas is chlorine or fluorine halide;
s5, depositing a supporting layer, and depositing the supporting layer on the surface of the sacrificial layer;
S6, depositing an electrode and a piezoelectric material, and sequentially depositing a bottom electrode, a piezoelectric material layer and a top electrode on the supporting layer.
Preferably, the multi-layered defect structure comprises 3 to 5 silicon-based thin films, and the total thickness of the multi-layered defect structure is 0.1 μm to 2 μm.
Preferably, in the defect structure, the defect density of the first layer located near the silicon substrate side is the lowest, the defect density of the uppermost layer located near the device active region side is the highest, and the thickness of each defect structure is 50nm to 300nm.
Preferably, the supporting layer is used for preventing the structure above the cavity from collapsing due to external force and stress, and the thickness of the supporting layer is 0.05 μm to 3 μm.
Preferably, the sacrificial layer is formed by low temperature deposition, including LPCVD, PECVD and PVD deposition processes, and the deposition thickness of the sacrificial layer is 0.5-4 μm.
Preferably, the etching mode is gas-phase HF dry etching and Cl 2/Ar plasma etching.
Preferably, the top electrode and the bottom electrode are made of Mo, the piezoelectric material is made of AlN, the thicknesses of the bottom electrode and the top electrode are respectively 0.05-0.5 μm, and the thickness of the piezoelectric material is 0.5-2 μm.
Preferably, the defect structure is formed by ion implantation, doping control, polysilicon or amorphous silicon deposition.
Preferably, the ion implantation of the defect structure uses phosphorus, boron and argon as ion species.
In addition, the invention also provides a resonator with an induced charge trapping defect structure, which comprises a silicon substrate, a gradient defect structure layer, a supporting layer, a bottom electrode, an AlN piezoelectric layer and a top electrode which are sequentially arranged from bottom to top, wherein a cavity structure generated by etching a sacrificial layer is formed between the supporting layer and the gradient defect structure layer, and the gradient defect structure layer comprises 3-5 layers of silicon-based films with gradient distribution of defect density.
Compared with the prior art, the invention has the following beneficial effects:
In the invention, organic matters and oxidation residues are removed through high-purity pretreatment, the combination of a deposition layer and a substrate is enhanced, a multi-layer defect gradient silicon structure is constructed to inhibit induced charge migration, a stable supporting layer is introduced to prevent structural collapse, a high-conductivity and high-voltage composite layer is deposited to improve excitation efficiency and frequency response, the energy conversion efficiency is enhanced by cooperative matching of layer thickness and defect density, a cavity is released by adopting a high-selectivity corrosion system, boundary integrity and tension balance are ensured, and loss inhibition and quality factor improvement under high frequency are realized.
Drawings
FIG. 1 is a block diagram of a preparation flow of the present invention;
FIG. 2 is a flow chart of the substrate cleaning of the present invention;
FIG. 3 is a flow chart of the deposition of the multi-layer defect structure of the present invention;
FIG. 4 is a flow chart of sacrificial layer deposition according to the present invention;
FIG. 5 is a flow chart of the cavity etch release of the present invention;
FIG. 6 is a flow chart of the support layer deposition of the present invention;
FIG. 7 is a flow chart of the electrode and piezoelectric material deposition of the present invention;
FIG. 8 is a schematic diagram of a resonator according to the present invention;
FIG. 9 is a schematic diagram of the preparation process of the present invention.
In the figure, 101, a surface silicon wafer substrate, 102, a defect structure, 103, a cavity structure, 104, a supporting layer, 105, a bottom electrode, 106, a piezoelectric material, 107, a top electrode, 108 and a sacrificial layer SiO 2.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the technical solutions in the embodiments of the present invention will be clearly and completely described in the following in conjunction with the embodiments of the present invention. It will be apparent to those skilled in the art that the examples are merely to aid in understanding the invention and should not be construed as limiting the invention in any way. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention. The process parameters for the specific conditions not noted in the examples below are generally as usual.
Example one, preparation of a Standard film bulk Acoustic resonator
S1, cleaning a substrate, namely selecting a surface silicon wafer substrate 101, firstly cleaning the surface of the substrate by using acetone to remove organic matters, then removing a surface silicon oxide layer by using hydrofluoric acid solution, and finally thoroughly cleaning by using deionized water (DIwater), and finally drying the substrate to ensure that no moisture remains on the surface, wherein the cleanliness of the substrate meets the requirements of the subsequent process.
S2, depositing a multi-layer defect structure 102, sequentially depositing three layers of silicon-based films on a surface silicon wafer substrate 101 by adopting a Chemical Vapor Deposition (CVD) method, wherein the first layer is a low-doped silicon film with the thickness of 100nm, the second layer is a medium-doped silicon film with the thickness of 100nm, the third layer is a high-doped silicon film with the thickness of 100nm, the defect density gradually increases from a bottom layer to a top layer, the effective capture of induced charges is ensured, the deposition temperature is 550 ℃, and the gas flow is controlled within the range of a standard CVD process so as to ensure the quality and uniformity of each layer of film.
S3, depositing and flattening the sacrificial layer, namely depositing a sacrificial layer SiO 2 on the surface of the multi-layer defect structure 102 by adopting a PECVD technology, wherein the thickness is 1 mu m, the PECVD deposition temperature is 300 ℃, the deposition rate is controlled to be 5nm/min, the surface flattening of the sacrificial layer is ensured, and after the completion, the surface flattening treatment is carried out by adopting a Chemical Mechanical Polishing (CMP) process, so that an uneven layer generated in the deposition process is removed, and the flatness of the subsequent structure is ensured.
S4, releasing cavity etching, removing the sacrificial layer through a gas-phase HF dry etching technology to form a cavity structure 103, wherein etching gas is chlorine gas, etching time is controlled within 30 minutes, the sacrificial layer is ensured to be completely removed, the cavity structure 103 is clear, and in the etching process, mixed gas of gas-phase HF and oxygen is used to reduce etching rate and improve etching precision.
S5, depositing a supporting layer 104, depositing a Si 3N4 supporting layer 104 with the thickness of 0.2 mu m on the surface of the sacrificial layer, adopting an LPCVD method, wherein the LPCVD deposition temperature is 800 ℃, the deposition gases are SiH 4 and NH 3, the deposition rate is controlled to be 15nm/min, the Si 3N4 supporting layer 104 has good mechanical strength, the collapse of the cavity structure 103 can be effectively prevented, and the structural stability of the resonator is improved.
S6, depositing an electrode and a piezoelectric layer, sequentially depositing a bottom electrode 105, an AlN piezoelectric material 106 layer with the thickness of 1 mu m and a top electrode 107 on a supporting layer 104 by using a PVD technology, wherein the bottom electrode 105 and the top electrode 107 are made of molybdenum (Mo) materials, the deposition thickness is 0.3 mu m, the magnetron sputtering method is adopted to finish the deposition, the piezoelectric material 106 is AlN, the reactive sputtering (RFsputtering) deposition method is adopted, the deposition temperature is controlled at 300 ℃, the nitrogen flow is 20sccm, and the deposition rate is 0.5 mu m/h.
The three-layer gradient doped defect structure 102 is constructed through standard CVD and PECVD processes, and the sacrificial layer SiO 2 and the Si 3N4 support layer 104 are adopted, so that the method has good process compatibility and manufacturing stability, is suitable for manufacturing conventional communication devices, and is convenient for mass production.
Embodiment two, high-frequency optimized preparation of film bulk acoustic resonator
S1, cleaning a substrate, namely selecting a surface silicon wafer substrate 101, cleaning the surface silicon wafer substrate 101 for multiple times by using pure water and deionized water, and then removing surface organic matters and residual pollutants by adopting UV-ozone treatment to ensure that the surface of the surface silicon wafer substrate 101 is smooth and clean and has no pollution.
S2, depositing a multi-layer defect structure 102, wherein three layers of silicon films with different doping concentrations are deposited on a silicon substrate by adopting a Chemical Vapor Deposition (CVD) method, the thickness of each layer is respectively 80nm, 120nm and 200nm, the doping concentration is sequentially increased to form a gradient structure with gradually increased defect density, the doping element is boron (B), the doping concentration is adjusted by adopting an ion implantation method, the deposition temperature is controlled at 550 ℃, and the doping gas flow is 10sccm.
S3, depositing and flattening the sacrificial layer, namely depositing the Si 3N4 sacrificial layer with the thickness of 2 mu m by adopting PECVD, controlling the deposition temperature at 350 ℃, and flattening the surface by adopting CMP after the deposition of SiH 4 and N 2 O and the deposition rate of 3nm/min, thereby ensuring the uniformity and good contact of the subsequent structure.
S4, cavity etching is released, the sacrificial layer is removed by using Cl 2/Ar plasma etching, etching gas is hydrogen chloride (Cl 2) and argon (Ar) are mixed, etching time is 20 minutes, and fine control and stability of the cavity structure 103 are ensured by accurately controlling the etching time and the gas proportion.
S5, depositing a supporting layer 104, depositing a Si 3N4 supporting layer 104 with the thickness of 0.5 mu m, controlling the gas flow to 5sccm by adopting an LPCVD process, and ensuring that the depositing temperature is 800 ℃, wherein the Si 3N4 layer has higher mechanical strength and is suitable for the requirement of structural stability in high-frequency application.
S6, depositing an electrode and a piezoelectric layer, sequentially depositing a gold (Au) bottom electrode 105 and a top electrode 107 on a supporting layer 104 by adopting a PVD technology, wherein the thickness of each bottom electrode 105 and the thickness of each top electrode 107 are 0.5 mu m, depositing an intermediate piezoelectric layer which is AlN by adopting a magnetron sputtering method, wherein the thickness of each intermediate piezoelectric layer is 1 mu m, and depositing by adopting an RF sputtering technology, wherein the deposition temperature is 300 ℃, the nitrogen flow is 15sccm, and the sputtering power is 200W.
By further fine-tuning the doping concentration and layer thickness on the defect structure 102, the Au electrode and the high-quality AlN piezoelectric material 106 are used, so that the high-frequency response performance is greatly optimized, the in-band insertion loss is reduced, the device is particularly suitable for 5G communication and high-speed radio frequency application, and the high-sensitivity and high-Q-value characteristics of the device are reflected.
Embodiment three, high reliability fabrication of thin film bulk acoustic resonators
S1, cleaning a substrate, namely selecting a surface silicon wafer substrate 101, cleaning by using acetone, isopropanol and hydrofluoric acid to remove organic matters and oxides, then thoroughly cleaning by using deionized water, and finally drying the surface of the surface silicon wafer substrate 101 by adopting nitrogen gas flow.
S2, depositing a multi-layer defect structure 102, namely depositing four layers of silicon films by adopting a CVD technology, wherein the thickness of each layer is 50nm, the total thickness is 200nm, the doping concentration of each layer is sequentially increased, and the doping concentration of the layers is regulated and controlled by ion implantation from the lowest doping concentration at one side of the substrate to the highest doping concentration near the active region of the device, so that a defect density increasing structure is ensured.
S3, depositing and flattening the sacrificial layer, depositing a 1-mu m-thick sacrificial layer SiO 2, adopting a PECVD process, wherein the deposition temperature is 250 ℃, flattening the surface through a CMP process after the deposition is finished, and ensuring the uniformity of the subsequent layers.
S4, cavity etching is released, the sacrificial layer is removed through a hydrogen fluoride gas phase etching technology (HFDRYETCHING), the etching time is 35 minutes, the fluorine gas concentration is 60%, and high etching precision and stability of the cavity structure 103 are guaranteed.
S5, depositing the support layer 104, and depositing the SiC support layer 104 by adopting an LPCVD process, wherein the thickness is 0.3 mu m. The SiC material has higher hardness and temperature resistance, and can ensure the long-term stability of the device under severe environment.
S6, depositing an electrode and a piezoelectric layer, wherein the bottom electrode 105 is made of platinum (Pt), the top electrode 107 is made of aluminum (Al), the thickness of the bottom electrode is 0.3 mu m, the piezoelectric material 106 is made of Al xGa1₋x N, the thickness of the bottom electrode is 1.5 mu m, the deposition temperature is 350 ℃, the nitrogen flow is 20sccm, and the sputtering power is 250W.
By outstanding reliability in terms of material selection and structural strength, the four layers of boron-doped silicon defect structure 102 and SiC support layer 104 are employed with excellent structural stability and long-term reliability in high temperature or severe environments.
Based on the above three examples, each of which is different in material selection, structural design and manufacturing process, resulting in their difference in performance, the following table summarizes the key technical parameters of each example and their characteristics, and performs a comparative analysis on them to facilitate selection of the best examples, and the results are shown in table 1;
TABLE 1 comparative examples
| Examples | Number of film layers | Each layer thickness | Sacrificial layer material | Support layer material | Piezoelectric material | Electrode material | Main characteristics of |
| Example 1 | Layer 3 | 100nm | SiO2 | Si3N4 | AlN | Mo | Standard process, suitable for basic application |
| Example two | Layer 3 | 80-200nm | Si3N4 | Si3N4 | AlN | Au | High frequency optimization suitable for 5G communication |
| Example III | 4 Layers | 50nm | SiO2 | SiC | AlxGa1₋xN | Pt/Al | High reliability, suitable for high temperature environment |
Implementing two-phase other embodiments according to the table above has several advantages:
1. High frequency performance optimization
The second embodiment has the core advantage that the high-frequency performance of the device is optimized, gold (Au) is adopted as an electrode material, and compared with the molybdenum electrode used in the first embodiment, the gold electrode has lower resistance and better conductivity, so that the insertion loss is lower in a high-frequency working state, and the transmission of high-speed signals such as 5G can be supported.
Compared with the AlN material of the first embodiment, the AlN (aluminum nitride) is adopted as the piezoelectric material 106, has better piezoelectric performance, and can keep higher resonance frequency and Q value at higher frequency, so that the second embodiment is particularly suitable for applications requiring high frequency and low insertion loss, such as 5G, wi-Fi.
2. Optimization of materials and structures
The silicon film of the second embodiment adopts the gradient defect structure 102 (boron doped silicon), the defect density of each layer is gradually increased, and the induced charges can be effectively captured by the regulation and control of the defect density, so that the induced loss is restrained, and the device can keep lower power loss and higher working efficiency in the working state of high-frequency signals.
By means of the defect density gradient regulation mode, the standard silicon film structure in the two-phase embodiment in the first embodiment can effectively reduce insertion loss caused by charge migration at high frequency.
3. High adaptability
The choice of materials and layer structures of the second embodiment makes the second embodiment have strong adaptability in high-frequency, low-power consumption and high-efficiency application, and is particularly suitable for the modern communication fields, such as 5G communication, radar systems and the like, and the second embodiment just meets the requirements of accurate frequency response, low insertion loss and good stability.
Compared to the first embodiment, the second embodiment provides higher operating frequency support, and at the same time, better stability in high frequency applications.
4. And (3) process optimization:
The sacrificial layer used in the second embodiment is Si 3N4, which further optimizes the overall structure of the device while providing a strong mechanical stability.
The choice of Au electrode is critical to improve the high frequency performance of the device, which is less relevant in the first (molybdenum electrode) and third (platinum electrode) embodiments.
4. Comparison with other embodiments:
in one embodiment, although the underlying process and materials are common, the electrical conductivity of the molybdenum electrode is less than that of the gold electrode in high frequency applications, and the piezoelectric material 106 and defect structure 102 are not designed for high frequency optimization, so it is not suitable for providing optimal performance in 5G and higher frequency applications.
In the third embodiment, the SiC support layer 104 provides strong high temperature resistance, but in the high frequency communication field, the high frequency optimization design (such as AlN piezoelectric layer and Au electrode) of embodiment 2 provides advantages in terms of high frequency performance and low insertion loss.
The second embodiment is particularly suitable for high frequency communication applications, especially in the 5G and other high speed signal transmission fields, by carefully optimizing the electrode material, the piezoelectric material 106 and the defect structure 102, and the performance thereof is significantly better than those of the first and third embodiments, so the second embodiment is the most recommended embodiment in the present invention.
The foregoing has shown and described the basic principles and main features of the present invention and the advantages of the present invention. It will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, and that the above embodiments and descriptions are merely illustrative of the principles of the present invention, and various changes and modifications may be made without departing from the spirit and scope of the invention, which is defined in the appended claims. The scope of the invention is defined by the appended claims and equivalents thereof.
Claims (10)
1. A method of fabricating a resonator having an induced charge trapping defect structure, comprising the steps of:
S1, cleaning a substrate, namely selecting a surface silicon wafer as a silicon substrate, firstly cleaning the silicon substrate by using acetone to remove organic pollutants on the surface of the silicon substrate, then rinsing the silicon substrate by using isopropanol or deionized water, then removing a surface natural oxide layer by using hydrofluoric acid solution, thoroughly flushing the silicon substrate by using deionized water after washing, and drying the silicon substrate by using nitrogen;
s2, depositing a multi-layer defect structure, namely sequentially depositing the multi-layer defect structure on the silicon substrate cleaned in the step S1, wherein the defect densities of the multi-layer defect structure are different, so that the defect densities of the multi-layer defect structure form gradient distribution;
S3, depositing a sacrificial layer, and depositing the sacrificial layer on the surface of the multi-layer defect structure;
S4, cavity etching is released, the sacrificial layer is removed in a dry etching mode and a wet etching mode to form a cavity structure, and etching gas is chlorine or fluorine halide;
s5, depositing a supporting layer, and depositing the supporting layer on the surface of the sacrificial layer;
S6, depositing an electrode and a piezoelectric material, and sequentially depositing a bottom electrode, a piezoelectric material layer and a top electrode on the supporting layer.
2. The method of claim 1, wherein the multi-layered defect structure comprises 3 to 5 silicon-based films, and the total thickness of the multi-layered defect structure is 0.1 μm to 2. Mu.m.
3. The method of claim 1, wherein the defect structures have a first layer with a lowest defect density near the silicon substrate side and a highest defect density near the device active region side, and each of the defect structures has a thickness of 50nm to 300nm.
4. The method of claim 1, wherein the support layer is configured to prevent collapse of the structure above the cavity due to external forces and stresses, and wherein the support layer has a thickness of 0.05 μm to 3 μm.
5. The method of claim 1, wherein the sacrificial layer is formed by low temperature deposition, including LPCVD, PECVD and PVD deposition processes, and the sacrificial layer is deposited to a thickness of 0.5 μm to 4 μm.
6. The method of claim 1, wherein the etching mode is gas phase HF dry etching and Cl 2/Ar plasma etching.
7. The method of claim 1, wherein the top and bottom electrodes are made of Mo, the piezoelectric material is made of AlN, the thicknesses of the bottom and top electrodes are respectively 0.05-0.5 μm, and the thickness of the piezoelectric material is 0.5-2 μm.
8. The method of claim 1, wherein the defect structure is formed by ion implantation, doping control, polysilicon or amorphous silicon deposition.
9. The method of claim 1, wherein the defect structure is implanted with ion species selected from the group consisting of phosphorus, boron and argon.
10. A resonator with induced charge trapping defect structure, based on the method of any one of claims 1-9, characterized in that it comprises a planar silicon wafer substrate (101), a defect structure (102), a support layer (104), a bottom electrode (105), a piezoelectric material (106) and a top electrode (107) sequentially arranged from bottom to top, wherein a cavity structure (103) generated by etching a sacrificial layer SiO 2 (108) is formed between the support layer (104) and the defect structure (102), and the defect structure (102) comprises a silicon-based film with 3-5 layers of defect density gradient distribution.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202511430987.5A CN120915265A (en) | 2025-10-09 | 2025-10-09 | Resonator with induced charge trapping defect structure and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202511430987.5A CN120915265A (en) | 2025-10-09 | 2025-10-09 | Resonator with induced charge trapping defect structure and preparation method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN120915265A true CN120915265A (en) | 2025-11-07 |
Family
ID=97542740
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202511430987.5A Pending CN120915265A (en) | 2025-10-09 | 2025-10-09 | Resonator with induced charge trapping defect structure and preparation method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN120915265A (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090134513A1 (en) * | 2007-07-23 | 2009-05-28 | Jin Qiu | Method and structures for fabricating mems devices on compliant layers |
| CN114142821A (en) * | 2021-12-02 | 2022-03-04 | 南通大学 | Silicon substrate structure and aluminum nitride piezoelectric resonant device and preparation method thereof |
| CN115333497A (en) * | 2022-06-28 | 2022-11-11 | 广州市艾佛光通科技有限公司 | Preparation method of film cavity acoustic wave resonator and film cavity acoustic wave resonator |
| CN119093900A (en) * | 2024-08-15 | 2024-12-06 | 西安电子科技大学 | A composite groove type FBAR filter and its preparation method |
-
2025
- 2025-10-09 CN CN202511430987.5A patent/CN120915265A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090134513A1 (en) * | 2007-07-23 | 2009-05-28 | Jin Qiu | Method and structures for fabricating mems devices on compliant layers |
| CN114142821A (en) * | 2021-12-02 | 2022-03-04 | 南通大学 | Silicon substrate structure and aluminum nitride piezoelectric resonant device and preparation method thereof |
| CN115333497A (en) * | 2022-06-28 | 2022-11-11 | 广州市艾佛光通科技有限公司 | Preparation method of film cavity acoustic wave resonator and film cavity acoustic wave resonator |
| CN119093900A (en) * | 2024-08-15 | 2024-12-06 | 西安电子科技大学 | A composite groove type FBAR filter and its preparation method |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TWI694559B (en) | Thermally stable charge trapping layer for use in manufacture of semiconductor-on-insulator structures | |
| CN103119727B (en) | Manufacturing method of photoelectric conversion device | |
| CN101548395B (en) | Method of manufacturing crystalline silicon solar cells with improved surface passivation | |
| CN111262543A (en) | Scandium-doped aluminum nitride lamb wave resonator and preparation method thereof | |
| CN105261657A (en) | Manufacturing process for MIS thin-film capacitors | |
| WO2013002212A1 (en) | Composite substrate and process for producing same | |
| CN110310997B (en) | A High Capacitance Density MIS Chip Capacitor | |
| CN115050842B (en) | A gallium oxide Schottky diode with reduced reverse leakage and a preparation method thereof | |
| US20250341020A1 (en) | Silicon carbide epitaxial wafer, and preparation method therefor and use thereof | |
| CN113594037B (en) | GaN MISHEMT device and manufacturing method thereof | |
| CN106920847A (en) | A kind of top-gated graphene field effect transistor and preparation method thereof | |
| CN109786510B (en) | Method for preparing a quaternary detector and indium gallium arsenide bismuth quaternary detector obtained therefrom | |
| CN112953448A (en) | Film bulk acoustic resonator with novel structure and preparation method thereof | |
| CN120915265A (en) | Resonator with induced charge trapping defect structure and preparation method thereof | |
| CN212163290U (en) | Scandium-doped aluminum nitride lamb wave resonator | |
| JP2002277605A (en) | Method of forming antireflection film | |
| CN109346405B (en) | Preparation method of GaN-based SBD flip chip | |
| CN107513723B (en) | Method for reducing opening potential of photoelectrochemical decomposed water of Ni/n-Si photoanode | |
| CN120836202A (en) | Epitaxial wafer, SOI wafer and method for manufacturing the same | |
| JPH09102594A (en) | Semiconductor substrate and manufacturing method thereof | |
| JP4575745B2 (en) | Manufacturing method of semiconductor device in which upper layer is laminated on GaN-based semiconductor layer | |
| CN117133661A (en) | Diamond composite substrate structure, manufacturing method and chip with diamond composite substrate structure | |
| CN113643970A (en) | Manufacturing method of silicon carbide semiconductor device | |
| CN113437159B (en) | A kind of N-type TOPCon battery with quantum well structure and its manufacturing method | |
| CN107546112B (en) | SiC ohmic contact structure and manufacturing method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |