CN1208827C - Method for improving reliability of non-volatile memory cell and structure thereof - Google Patents
Method for improving reliability of non-volatile memory cell and structure thereof Download PDFInfo
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- CN1208827C CN1208827C CN02106106.8A CN02106106A CN1208827C CN 1208827 C CN1208827 C CN 1208827C CN 02106106 A CN02106106 A CN 02106106A CN 1208827 C CN1208827 C CN 1208827C
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- clearance wall
- volatile memory
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- 238000000034 method Methods 0.000 title claims abstract description 36
- 239000000758 substrate Substances 0.000 claims description 43
- 238000006396 nitration reaction Methods 0.000 claims description 42
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 12
- 230000003647 oxidation Effects 0.000 claims description 11
- 238000007254 oxidation reaction Methods 0.000 claims description 11
- 229910052710 silicon Inorganic materials 0.000 claims description 9
- 239000010703 silicon Substances 0.000 claims description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 8
- 230000008569 process Effects 0.000 claims description 7
- 238000004062 sedimentation Methods 0.000 claims description 6
- 239000000377 silicon dioxide Substances 0.000 claims description 6
- 230000001590 oxidative effect Effects 0.000 claims description 3
- 235000012239 silicon dioxide Nutrition 0.000 claims 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims 2
- 150000002500 ions Chemical class 0.000 abstract description 22
- 150000004767 nitrides Chemical class 0.000 abstract 2
- 239000010410 layer Substances 0.000 description 52
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 10
- 229910004298 SiO 2 Inorganic materials 0.000 description 9
- 238000004519 manufacturing process Methods 0.000 description 6
- 239000011229 interlayer Substances 0.000 description 5
- 229910052751 metal Inorganic materials 0.000 description 5
- 239000002184 metal Substances 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 4
- 230000000903 blocking effect Effects 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 239000011734 sodium Substances 0.000 description 4
- 230000008901 benefit Effects 0.000 description 3
- 239000000428 dust Substances 0.000 description 3
- 238000002474 experimental method Methods 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- 240000001439 Opuntia Species 0.000 description 1
- NPYPAHLBTDXSSS-UHFFFAOYSA-N Potassium ion Chemical compound [K+] NPYPAHLBTDXSSS-UHFFFAOYSA-N 0.000 description 1
- FKNQFGJONOIPTF-UHFFFAOYSA-N Sodium cation Chemical group [Na+] FKNQFGJONOIPTF-UHFFFAOYSA-N 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 230000008676 import Effects 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 229910001414 potassium ion Inorganic materials 0.000 description 1
- 150000003376 silicon Chemical class 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 229910001415 sodium ion Inorganic materials 0.000 description 1
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- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
Abstract
The present invention relates to a method for improving the reliability of a non-volatile memory cell and a structure thereof. In the method for improving the reliability of a non-volatile memory cell, a pad oxide layer interval wall with the thickness of about 100 angstroms, a nitride layer interval wall with the thickness of about 200 angstroms and an oxide layer interval wall with the thickness of about 2000 angstroms are orderly formed on the side wall of a grid structure of a memory cell. Therefore, because the nitride layer interval wall can reduce the probability for mobile ions to be adjacent to the memory cell, stored charge in the memory cell can not be lost, and the reliability of a subassembly is raised.
Description
Technical field
The present invention relates to a kind of method for making semiconductor and structure, particularly a kind of method and structure thereof of improving the non-volatile memory cells reliability, promptly a kind of manufacture method and structure that reduces store charge loss in the non-volatile memory cells.
Background technology
Internal memory can be divided into volatile ram and Nonvolatile memory two big classes, wherein, the characteristic of Nonvolatile memory is its function with memory, that is to say, after even power supply is turned off, data stored in the Nonvolatile memory still can be preserved, for example: mask read-only memory (maskROM), disposable programmable read-only memory (OTP ROM), can erase and programmable read only memory (EPROM), can electricity remove and programmable read only memory (EEPROM), internal memory (flashmemory), multiple programmable read-only memory (MTP ROM) or the like.
In the traditional fabrication process, often with boron-phosphorosilicate glass (BPSG) as inner layer dielectric layer (inter-layer dielectric; ILD), in order to isolated gate zone (gate regions) and the first metal layer (metal 1), and with inner metal dielectric layer (inter-metal dielectric; IMD) separate each layer metal.Yet; in process through a series of deposition, photoetching; it for example is sodium ion, potassium ion that regular meeting imports some ... Deng the micropollution of free ion (mobile ion); these free ions can interact with store charge in the memory subassembly, cause charge loss and reduce reliability of products.This situation is at deep-sub-micrometer from generation to generation under (deep sub-micron generation), especially one of the semiconductor industry big problem.
See also Fig. 1.The generalized section of the existing flash memory unit structure of Fig. 1.
Fig. 1 is the structure of existing flash memory unit structure 100, includes:
One silicon substrate 110 has a grid structure 120 on it;
Silicon monoxide clearance wall (spacer) 130 is positioned on the sidewall of this grid structure 120; And
140 and one drain region 150, one source pole zone lays respectively in the substrate of these grid structure 120 both sides.
Wherein this grid structure 120 also includes:
One tunnel oxidation (tunnel oxide) layer 122 is positioned on this substrate 110 of part;
One floating grid (floating gate) 124 is positioned on this grid oxic horizon 122;
One gate dielectric layer (inter-gate dielectric layer) 126 is positioned on this floating grid 124; And
One control grid (control gate) 128 is positioned on this gate dielectric layer 126.
Yet above-mentioned free ion (mobile ions) still can penetrate this silica clearance wall (spacer) 130 and near this grid structure 120, makes to be stored in the charge loss in this floating grid 124 and to reduce the reliability (reliability) of product.
Summary of the invention
In view of this, in order to address the above problem, main purpose of the present invention is to provide a kind of method of improving the non-volatile memory cells reliability, reduces store charge loss in the non-volatile memory cells.
Another object of the present invention is to provide a kind of structure of non-volatile memory cells.
The object of the present invention is achieved like this:
The present invention discloses a kind of method of improving the non-volatile memory cells reliability, and its step comprises: a substrate (a) is provided; (b) form at least one grid structure on this substrate; (c) form a doped region respectively in this substrate of these grid structure both sides; (d) form the pad oxide of a compliance (conformal) on this grid structure and this substrate; (e) form the nitration case of a compliance on this pad oxide and this substrate; (f) anisotropically remove this nitration case of part and this pad oxide surface up to top of exposing this grid structure and part substrate, and form a pad oxide clearance wall on the sidewall of this grid structure, and a nitration case clearance wall is on the sidewall of this pad oxide clearance wall; (g) form the oxide layer of a compliance on this pad oxide clearance wall, this nitration case clearance wall, this grid structure and this substrate; And (h) anisotropically remove this oxide layer of part up to the surface of top of exposing this grid structure and part substrate, and form an oxide layer clearance wall on the sidewall of this nitration case clearance wall.
The present invention also discloses a kind of structure of non-volatile memory cells, comprising: a substrate has a grid structure on this substrate; One pad oxide clearance wall is positioned on the sidewall of this grid structure; One nitration case clearance wall is positioned on the sidewall of this pad oxide clearance wall; One oxide layer clearance wall is positioned on the sidewall of this nitration case clearance wall; And an one source pole and a drain region, lay respectively in this substrate of these grid structure both sides.
Wherein, about 100 dusts of the preferred thickness of this pad oxide clearance wall.
Wherein, about 200 dusts of the preferred thickness of this nitration case clearance wall.
Wherein, about 2000 dusts of the preferred thickness of this oxide layer clearance wall.
Therefore according to the present invention, make that the store charge in this memory cell can not run off, and can reduce free ion (mobile ion) near this memory cell, lifting subassembly reliability.And the thickness of this nitration case clearance wall has only 200 dusts approximately, so also can not influence the etching process that forms interlayer hole (via) in the future.
For above-mentioned purpose of the present invention, feature and advantage can be become apparent, preferred embodiment cited below particularly, and conjunction with figs. is described in detail below:
Description of drawings
Fig. 1 shows the profile of existing non-volatile memory cell structure;
Fig. 2--7 show according to manufacture method profile of the present invention;
Fig. 8 shows according to manufacture method advantage key diagram of the present invention;
Fig. 9 a shows test SiO
2Layer is to the profile of the test piece of free ion blocking capability;
The SIMS qualitative test curve chart of the test piece of Fig. 9 b displayed map 9a;
Figure 10 a shows the profile of test SiN layer to the test piece of free ion blocking capability; And
The SIMS qualitative test curve chart of the test piece of Figure 10 b displayed map 10a.
Among the figure:
Existing flash memory unit structure-100; Silicon substrate-110; Grid structure-120; Tunnel oxidation layer-122; Floating grid-124; Gate dielectric layer-126; Control grid-128; Silica clearance wall-130; Source region-140; Drain region-150; Semiconductor substrate-200; Grid structure-210; Tunnel oxidation layer-211; Floating grid-212; Gate dielectric layer-213; Control grid-214; Source region-215; Drain region-216; Pad oxide-310; Nitration case-410; Pad oxide clearance wall-510; Nitration case clearance wall-520; Oxide layer-610; Oxide layer clearance wall-710;
Flash memory unit structure of the present invention-720; Dielectric layer (ILD)--810; Interlayer hole (via)--820; Silicon substrate-900; SiO
2Layer-910; Silicon substrate-1000; SiO
2Layer-1010; SiN layer-1020; SiO
2Layer-1030.
Embodiment
Please refer to Fig. 2-7.Fig. 2--7 show according to manufacture method profile of the present invention.At first, please refer to Fig. 2, semi-conductive substrate 200 is provided, wherein have at least one grid structure 210 of any possible Nonvolatile memory on this substrate 200, this Nonvolatile memory is for example for can erase and programmable read only memory (erasable programmable read-only memory; EPROM), can remove and programmable read only memory (electrically erasable programmable read-onlymemory by electricity; EEPROM) or flash memory (flash memory) ... or the like.Be example with a flash memory in the present embodiment.Wherein the formation earlier of the formation method of this grid structure 210 for example is SiO
2One tunnel oxidation layer 211 of layer is on this substrate 200 of part; Form a floating grid 212 as polysilicon layer then on this tunnel oxidation layer 211; Form as SiO then
2One gate dielectric layer 213 of layer or ONO layer is on this floating grid 212; And then formation is controlled grid 214 on this gate dielectric layer 213 as one of polysilicon layer.Then, forming a doped region 215,216 respectively in this substrate 200 of these grid structure 210 both sides, is 215 and one drain region 216, one source pole zone in order to be used as.
Secondly, see also Fig. 3, pad oxidation (linear oxide) layer 310 of a compliance that forms the about 50--250 dust of thickness with oxidizing process is on this grid structure 210 and this substrate 200.Wherein, this pad oxide 310 is preferably in and carries out oxidation (for example ISSG (In Situ StreamGeneration) oxidizing process) in the high temperature furnace pipe.
Secondly, see also Fig. 4, the nitration case 410 of a compliance that forms the about 100--300 dust of thickness with sedimentation is on this pad oxide 310 and this substrate 200.Wherein, this nitration case 410 is preferably by chemical vapour deposition technique, and generation SiN layer or SiON layer.
Secondly, see also Fig. 5, anisotropically remove this nitration case 410 of part and the surface of this pad oxide 310 with dry ecthing method up to top surface that exposes this grid structure 210 and part substrate 200, and form a pad oxide clearance wall 510 on the sidewall of this grid structure 210, and a nitration case clearance wall 520 is on the sidewall of this pad oxide clearance wall 510.Preferably about 100 dusts of thickness of this pad oxide clearance wall 510 of this moment, and preferably about 200 dusts of the thickness of this nitration case clearance wall 520.
Secondly, see also Fig. 6, the oxide layer 610 of a compliance that forms the about 2000--3000 dust of thickness with sedimentation is on this pad oxide clearance wall 510, this nitration case clearance wall 520, this grid structure 210 and this substrate 200.Wherein, this oxide layer 610 is preferably by chemical vapour deposition technique, and generation TEOS--SiO
2Layer.
Secondly, see also Fig. 7, anisotropically remove the surface of this oxide layer 610 of part with dry ecthing method up to top surface that exposes this grid structure 210 and part substrate 200, and form an oxide layer clearance wall 710 on the sidewall of this nitration case clearance wall 520, preferably about 2000 dusts of thickness of this oxide layer clearance wall 710 of this moment, so, promptly finished the structure 720 of non-volatile memory cells of the present invention.
Therefore, the structure 720 of non-volatile memory cells of the present invention includes a substrate 200, has a grid structure 210 on this substrate; One pad oxide clearance wall 510 is positioned on the sidewall of this grid structure 210; One nitration case clearance wall 520 is positioned on the sidewall of this pad oxide clearance wall 510; One oxide layer clearance wall 710 is positioned on the sidewall of this nitration case clearance wall 520; And 215 and one drain region 216, one source pole zone, lay respectively in this substrate 200 of these grid structure 210 both sides.As for the material of each layer and thickness range then as above-mentioned, repeat no more herein.
Advantage of the present invention as shown in Figure 8, is to form with sedimentation that to be used as be that a dielectric layer 810 of interlayer dielectric layer (ILD) is on this substrate 200, this oxide layer clearance wall 710 and this grid structure 210; Carry out an etching manufacture method then in order to form an interlayer hole (via) 820.Because this nitration case clearance wall 520 very thin (about 200 dusts) of non-volatile memory cell structure of the present invention, so, also can etching not stop on this nitration case clearance wall 520 even when in etching process, the misalignment situation taking place.
Also have, because this nitration case clearance wall 520 very thin (about 200 dusts) of non-volatile memory cell structure of the present invention, so the stress (stress) that this nitration case clearance wall 520 is produced is very little.
Also have, because this nitration case clearance wall 520 very thin (about 200 dusts) of non-volatile memory cell structure of the present invention, so required thermal energy is fewer and can reduce the cost (cost) when depositing duty wall 520 between this nitration case.
Also have very good of the barriering effect of 520 pairs of free ions of this nitration case clearance wall of non-volatile memory cell structure of the present invention.At this, inventor etc. confirm that with SIMS (ion microprobe) qualitative test curve chart nitration case has goodish obstruct effectiveness to free ion really.Experiment as following:
Experiment 1
Please refer to Fig. 9 a and Fig. 9 b.Fig. 9 a shows test SiO
2Layer is to the profile of the test piece of free ion blocking capability.The SIMS qualitative test curve chart of the test piece of Fig. 9 b displayed map 9a.
Wherein, the test piece among Fig. 9 a forms a SiO of about 2000 dusts of thickness
2Layer 910 is on a silicon substrate 900.From Fig. 9 b, after about 2000 dusts of the degree of depth, still have tangible free ion (Na
+, K
+) concentration curve, so free ion (Na as can be known
+, K
+) penetrable this SiO
2Layer 910 and enter in this silicon substrate 900.Therefore proved that prior art forms the oxide layer clearance wall at the grid structure sidewall and can not effectively stop free ion.
Experiment 2
Please refer to Figure 10 a and Figure 10 b.Figure 10 a shows the profile of test SiN layer to the test piece of free ion blocking capability.The SIMS qualitative test curve chart of the test piece of Figure 10 b displayed map 10a.
Wherein, the test piece among Figure 10 a forms a SiO of about 2000 dusts of thickness earlier
2Layer 1010 is on a silicon substrate 1000, and then a SiN layer 1020 of about 200 dusts of formation thickness is in this SiO
2On the layer 1010, form a SiO of about 1500 dusts of thickness afterwards again
2 Layer 1030 is on this SiN layer 1020.From Figure 10 b, after about 1700 dusts of the degree of depth, almost there is not tangible free ion (Na
+, K
+) concentration curve, this SiN layer 1020 can stop free ion (Na effectively as can be known
+, K
+) penetrate.Therefore proved that the present invention forms nitration case gap wall energy at the grid structure sidewall and effectively stops free ion, and can avoid free ion, and can promote the electrical stability of Nonvolatile memory assembly near non-volatile memory cells.
Though the present invention with preferred embodiment openly as above; right its is not in order to limiting scope of the present invention, those of ordinary skills, without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is as the criterion with claim.
Claims (19)
1. method of improving the non-volatile memory cells reliability is characterized in that step comprises:
(a) provide a substrate;
(b) form a grid structure on this substrate;
(c) form a doped region respectively in this substrate of these grid structure both sides;
(d) form the pad oxide of a compliance on this grid structure and this substrate;
(e) form the nitration case of a compliance on this pad oxide and this substrate;
(f) anisotropically remove this nitration case of part and this pad oxide, form a pad oxide clearance wall on the sidewall of this grid structure, and a nitration case clearance wall is on the sidewall of this pad oxide clearance wall;
(g) form the oxide layer of a compliance on this pad oxide clearance wall, this nitration case clearance wall, this grid structure and this substrate; And
(h) anisotropically remove this oxide layer of part, form an oxide layer clearance wall on the sidewall of this nitration case clearance wall.
2. the method for improving the non-volatile memory cells reliability as claimed in claim 1 is characterized in that, after forming this oxide layer clearance wall, also comprises:
Form a dielectric layer on this oxide layer clearance wall, this grid structure and this substrate.
3. the method for improving the non-volatile memory cells reliability as claimed in claim 1 is characterized in that, the method that forms this grid structure also comprises:
Form a tunnel oxidation layer on this substrate of part;
Form a floating grid on this tunnel oxidation layer;
Form a gate dielectric layer on this floating grid; And
Form a control grid on this gate dielectric layer.
4. the method for improving the non-volatile memory cells reliability as claimed in claim 1 is characterized in that, this pad oxide is the silicon dioxide layer that is formed by oxidizing process.
5. the method for improving the non-volatile memory cells reliability as claimed in claim 1 is characterized in that, the thickness range of this pad oxide is 50～250 dusts.
6. the method for improving the non-volatile memory cells reliability as claimed in claim 1 is characterized in that, this nitration case is by the formed silicon nitride layer of sedimentation.
7. the method for improving the non-volatile memory cells reliability as claimed in claim 1 is characterized in that, this nitration case is by the formed silicon oxynitride layer of sedimentation.
8. the method for improving the non-volatile memory cells reliability as claimed in claim 1 is characterized in that, thickness range 100～300 dusts of this nitration case.
9. the method for improving the non-volatile memory cells reliability as claimed in claim 1 is characterized in that, this oxide layer is by the formed silicon dioxide layer of sedimentation.
10. the method for improving the non-volatile memory cells reliability as claimed in claim 1 is characterized in that, this thickness of oxide layer scope is 2000～3000 dusts.
11. the structure of a non-volatile memory cells is characterized in that, this structure comprises:
(a) substrate has a grid structure on this substrate;
(b) a pad oxide clearance wall is positioned on the sidewall of this grid structure;
(c) a nitration case clearance wall is positioned on the sidewall of this pad oxide clearance wall;
(d) an oxide layer clearance wall is positioned on the sidewall of this nitration case clearance wall;
(e) one source pole and a drain region lay respectively in this substrate of these grid structure both sides; And
(f) dielectric layer is positioned on this oxide layer clearance wall, this grid structure and this substrate.
12. the structure of non-volatile memory cells as claimed in claim 11 is characterized in that, this grid structure comprises:
One tunnel oxidation layer is positioned on this substrate of part;
One floating grid is positioned on this tunnel oxidation layer;
One gate dielectric layer is positioned on this floating grid; And
One control grid is positioned on this gate dielectric layer.
13. the structure of non-volatile memory cells as claimed in claim 11 is characterized in that, this pad oxide clearance wall comprises silicon dioxide.
14. the structure of non-volatile memory cells as claimed in claim 11 is characterized in that, the thickness range of this pad oxide clearance wall is 50～250 dusts.
15. the structure of non-volatile memory cells as claimed in claim 11 is characterized in that, this nitration case clearance wall comprises silicon nitride.
16. the structure of non-volatile memory cells as claimed in claim 11 is characterized in that, this nitration case clearance wall comprises silicon oxynitride.
17. the structure of non-volatile memory cells as claimed in claim 11 is characterized in that, the thickness range of this nitration case clearance wall is 100～300 dusts.
18. the structure of non-volatile memory cells as claimed in claim 11 is characterized in that, this oxide layer clearance wall comprises silicon dioxide.
19. the structure of non-volatile memory cells as claimed in claim 11 is characterized in that, the thickness range of this oxide layer clearance wall is 2000～3000 dusts.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN02106106.8A CN1208827C (en) | 2002-04-03 | 2002-04-03 | Method for improving reliability of non-volatile memory cell and structure thereof |
| US10/390,690 US20030181053A1 (en) | 2002-03-20 | 2003-03-19 | Method of manufacturing a nonvolatile memory cell with triple spacers and the structure thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN02106106.8A CN1208827C (en) | 2002-04-03 | 2002-04-03 | Method for improving reliability of non-volatile memory cell and structure thereof |
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| Publication Number | Publication Date |
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| CN1449022A CN1449022A (en) | 2003-10-15 |
| CN1208827C true CN1208827C (en) | 2005-06-29 |
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| CN101183666B (en) * | 2007-12-13 | 2011-07-20 | 上海宏力半导体制造有限公司 | Method of manufacturing side wall of self-alignment source drain of embedded type flash memory |
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