CN120826067A

CN120826067A - Perovskite crystal silicon laminated bottom cell structure, laminated cell and preparation method

Info

Publication number: CN120826067A
Application number: CN202510983811.6A
Authority: CN
Inventors: 田梦媛
Original assignee: Chuzhou Jietai New Energy Technology Co ltd
Current assignee: Chuzhou Jietai New Energy Technology Co ltd
Priority date: 2025-07-16
Filing date: 2025-07-16
Publication date: 2025-10-21

Abstract

The present invention provides a perovskite crystalline silicon stacked bottom cell structure and a stacked cell and a preparation method. The bottom cell structure includes a semiconductor substrate layer. The first surface of the semiconductor substrate layer is provided with a boron-doped layer, a velvet, a passivation film layer and a first metal electrode in sequence from the inside to the outside. The second surface of the semiconductor substrate layer is provided with a small velvet, a tunneling oxide layer and an N-type polysilicon layer in sequence from the inside to the outside. The N-type polysilicon layer includes at least two polysilicon layers arranged alternately in the horizontal direction and having different thicknesses. The small velvet height is less than the velvet height. The N-type polysilicon layer of the present invention is configured as a polysilicon layer of different thicknesses arranged alternately, which reduces the parasitic absorption of photons, thereby improving the current output of the bottom cell. After ensuring the reduction of parasitic absorption of photons, the deposition thickness of the first polysilicon layer is increased. When the second surface is a velvet, the npoly can evenly cover the velvet to ensure the passivation level, avoid exposing defects, increase carrier recombination, and reduce battery performance.

Description

Perovskite crystal silicon laminated bottom cell structure, laminated cell and preparation method

Technical Field

The invention belongs to the technical field of perovskite solar cells, and particularly relates to a perovskite crystal silicon laminated bottom cell structure, a laminated cell and a preparation method.

Background

With the continuous increase of global energy demand and the increase of environmental awareness, solar energy is taken as a clean renewable energy source, and development and utilization of the solar energy are increasingly emphasized. In the technical field of solar cells, laminated solar cells are becoming a research hotspot because they can more effectively utilize solar spectrum and improve photoelectric conversion efficiency. Particularly, the perovskite crystal silicon laminated cell has great application potential due to the combination of the advantages of perovskite materials and crystal silicon.

Related studies have shown that the current loss increases by 0.5mA/cm ² for every 10nm of front side polysilicon thickness. This severely restricts the development of high performance bifacial TOPCon cells, and also together as a bottom cell for perovskite crystal silicon stacked cells. Thus, in perovskite crystalline silicon stacked cells, thickness control of the polysilicon layer remains a key technical challenge.

In the prior art, polysilicon layers are typically of uniform thickness. As disclosed in CN110867516a, a perovskite and crystalline silicon back passivation laminated solar cell and a method for manufacturing the same are disclosed, comprising a bottom cell and a top cell, wherein an upper electrode is fixedly connected to the top cell, an intermediate layer is arranged between the bottom cell and the top cell, the bottom cell is a crystalline silicon back passivation cell, the intermediate layer is a transparent conductive layer, and the top cell is a perovskite cell. The definition of the bottom layer battery is that the thickness of the back doped polysilicon layer is 40-450 nm, and the back doped polysilicon layer is a uniform polysilicon layer.

The technical scheme faces the dilemma that excessive parasitic absorption can be generated when the polycrystalline layer is too thick, so that the number of photons reaching the bottom battery is reduced, and the current output of the bottom battery is reduced, and on the other hand, the passivation effect of the bottom battery is influenced when the polycrystalline silicon layer is too thin, so that the carrier recombination is increased, and the battery performance is reduced. In addition, the contact area with the transparent conductive layer is limited by the existing planar polysilicon layer structure, so that the interface contact resistance and the transverse transmission resistance are increased, and the collection and the transmission of current are not facilitated.

Disclosure of Invention

The invention aims to provide a perovskite crystal silicon laminated bottom cell structure which solves the technical problems in the prior art.

The invention further aims to provide a preparation method of the perovskite crystal silicon laminated bottom cell structure, wherein the polycrystalline silicon layers are arranged into the first crystal silicon layers and the second crystal silicon layers which are alternately arranged with different thicknesses through a wet method.

The perovskite crystal silicon laminated cell provided by the invention has the advantages that the contact area of the polycrystalline silicon layer and the transparent conducting layer is increased, the interface contact resistance and the transverse transmission resistance can be reduced, the collection and the transmission of current between the bottom cell and the top cell are facilitated, the cell filling is improved, and the cell efficiency is improved.

Another object of the present invention is to provide a method for manufacturing a perovskite crystal silicon laminate cell.

Therefore, the technical scheme provided by the invention is as follows:

The utility model provides a perovskite crystalline silicon stromatolite bottom battery structure, includes the semiconductor substrate layer, the first surface of semiconductor substrate layer is equipped with the boron doping layer, passivation film layer and the first metal electrode of matte structure from interior to outward in proper order, the second surface of semiconductor substrate layer is little matte from interior to outward in proper order, tunnel oxide layer and N type polycrystalline silicon layer, N type polycrystalline silicon layer includes at least two kinds of polycrystalline silicon layers and thickness difference that arrange in turn on the horizontal direction, little matte height is less than matte structure height

The N-type polycrystalline silicon layer comprises a first polycrystalline silicon layer and a second polycrystalline silicon layer, the thickness of the first polycrystalline silicon layer is 10nm-400nm, the thickness of the second polycrystalline silicon layer is 20% -90% of that of the first polycrystalline silicon layer, and the second polycrystalline silicon layer accounts for 2% -45% of the area of the N-type polycrystalline silicon layer.

The small pile surface height is 0.5-1.2 μm.

The preparation method of the perovskite crystal silicon laminated bottom cell structure comprises the following steps:

etching by adopting alkali solution to form pyramid suede structures with uniform sizes on the two sides of the semiconductor substrate layer;

Step 2) boron diffusion, namely using BCl ₃ as a diffusion source, wherein the diffusion temperature is 500-900 ℃, and the diffusion sheet resistance is controlled to be 200-500 omega/Sq;

step 3) removing the second surface of the semiconductor substrate layer by coiling plating and polishing;

Step 4) preparing small suede by secondary texturing, namely etching by adopting alkali solution, and forming small suede with uniform small pyramid structure on the second surface of the semiconductor substrate layer;

Step 5) depositing a tunneling oxide layer and an intrinsic polysilicon layer;

Step 6) phosphorus diffusion, namely phosphorus diffusion is carried out on the intrinsic polycrystalline silicon layer by taking POCl ₃ as a diffusion source to form a phosphorus doped layer polycrystalline silicon layer and a PSG layer;

step 7) forming an alkaline washing second polysilicon layer window, namely, using laser to treat the PSG layer, ablating SiOx to form the alkaline washing second polysilicon layer window, wherein the ablation area is 1% -40%;

Step 8) removing the first surface by coiling plating;

step 9) forming a second polysilicon layer on the second surface, namely performing alkali liquor etching on a window of the second polysilicon layer through alkali washing to form the second polysilicon layer, and obtaining N-type polysilicon layers with alternately arranged first polysilicon layers and second polysilicon layers in the horizontal direction;

Step 10) depositing a passivation film layer and H ⁺ passivation, namely depositing the passivation layer on the first surface of the semiconductor substrate layer, performing hydrogen passivation on the second surface of the semiconductor substrate layer, and performing passivation film layer and H ⁺ deposition under the NH ₃ atmosphere;

and 11) printing and sintering, namely printing AgAl slurry on the first surface of the semiconductor substrate layer, and forming the front first metal electrode after sintering.

And 5) depositing a tunneling oxide layer and an intrinsic polycrystalline silicon layer in the step 5), wherein the thickness of the tunneling oxide layer is 1nm-5nm, and the thickness of the intrinsic polycrystalline silicon film is 40nm-500nm by using an LPCVD technology.

In the step 6), the phosphorus diffusion temperature is 700-900 ℃, the doping concentration is 1-5E 20cm ^-3, and the thickness of the PSG layer is 10-100 nm.

In the step 7), the output power of the laser is 10-70W, the pulse repetition frequency is 5-20 kHz, the diameter of a laser spot is 5-15 Pm, and the laser beam speed is 30-60 mm/s.

In the step 9), the alkali solution is one or the mixture of NaOH and KOH, the concentration of the alkali solution is 0.5-10wt%, and the etching time is 10-150 s.

The perovskite/TOPCon laminated cell comprises a perovskite cell, a transparent conductive oxide layer and a perovskite crystal silicon layer bottom cell structure which are sequentially arranged from top to bottom, wherein the transparent conductive oxide layer is connected with the second surface of the perovskite crystal silicon layer bottom cell structure;

the perovskite battery comprises a hole transmission layer, a perovskite film layer, an electron transmission layer, a carrier composite layer, an antireflection film layer and a second metal electrode which are sequentially arranged from inside to outside.

A method for preparing a perovskite/TOPCon laminated cell, comprising the following steps:

S1, preparing a perovskite crystalline silicon layer bottom cell structure, namely sequentially performing texturing and boron diffusion on a semiconductor substrate layer, removing a second surface, winding and plating, polishing, secondarily texturing to prepare a small textured surface of the second surface, depositing an oxide tunneling oxide layer and an intrinsic polycrystalline silicon layer, performing phosphorus diffusion, laser processing a second polycrystalline silicon layer PSG, removing the winding and plating, adding alkali for washing to form a second polycrystalline silicon layer, depositing a passivation film layer and H+ passivation, printing a first metal electrode, and sintering to obtain a bottom cell;

s2, preparing a transparent conductive oxide layer, namely preparing the transparent conductive oxide layer on the second surface of the bottom battery by PVD magnetron sputtering under the atmosphere that the air pressure is less than or equal to 1Pa and the argon-oxygen ratio is 1:0.02-0.1 and the power density is 1-3W/cm ²;

S3, preparing a hole transport layer, namely preparing a compact TiO ₂ layer at the high temperature of 400-550 ℃ by a spray pyrolysis method, wherein the thickness of the compact TiO ₂ layer is 30-100 nm;

S4, preparing a perovskite film layer, wherein the band gap width of the perovskite layer is 1.3eV-1.8eV, the perovskite material structure is ABX ₃, wherein A is any one or a mixture of a plurality of cations in methylamine, formamidine and Cs, B is Pb or Sn, X is any one or a mixture of three anions in Cl, br and I, and the thickness of the perovskite film layer is 800nm-1200nm;

s5, preparing an electron transport layer, namely preparing an electron transport layer material SnO ₂ on the perovskite film layer, wherein the thickness of the electron transport layer material is 15-40 nm;

s6, preparing a carrier composite layer, namely preparing the carrier composite layer on the electron transport layer, wherein the material is ITO, and the thickness is 30-100 nm;

S7, depositing an antireflection film layer;

and S8, printing AgAl slurry on the front surface of the laminated layer, and sintering to form a front second metal electrode to obtain the perovskite crystal silicon laminated cell.

The invention has the beneficial effects that:

According to the perovskite crystal silicon laminated bottom cell structure provided by the invention, the N-type polycrystalline silicon layers are arranged into the first crystal silicon layers and the second crystal silicon layers which are alternately arranged with different thicknesses, so that parasitic absorption of the polycrystalline silicon layers to photons is reduced, and the current output of the bottom cell is improved. After the parasitic absorption of photons is guaranteed to be reduced, the deposition thickness of the first polysilicon layer can be properly increased, so that the naply can uniformly cover the nap under the condition that the second surface is the nap, the passivation level is guaranteed, the exposure defect is avoided, the carrier recombination is increased, and the battery performance is reduced.

According to the method, the polysilicon layer and the PSG layer with uniform thickness are firstly deposited on the second surface of the bottom battery, PSG on the second polysilicon layer is firstly treated by utilizing laser according to different designed polysilicon thickness difference patterns, then part of the polysilicon layer in the second polysilicon region of the bottom battery is removed by utilizing alkali liquor, and finally the residual PSG on the first polysilicon layer is cleaned and removed by utilizing acid liquor, so that two or more polysilicon layers are alternately arranged according to the design, and the technical problems that excessive parasitic absorption is generated due to excessive thickness caused by the uniform thickness of the polysilicon layer, passivation effect of the bottom battery is influenced by excessive thickness, contact between the polysilicon layer and the transparent conductive layer is limited and the like are solved.

Drawings

FIG. 1 is a schematic structural diagram of one embodiment of a perovskite crystalline silicon laminate bottom cell structure of the invention;

FIG. 2 is a schematic structural view of one embodiment of a perovskite/TOPCon stack cell of the invention;

fig. 3 is a flow chart of the preparation of the perovskite crystalline silicon laminate bottom cell structure of the invention.

The reference numerals indicate that the semiconductor substrate layer comprises a1 type and N type polycrystalline silicon layer, a2 type semiconductor substrate layer, a3 type passivation film layer, a 4 type first polycrystalline silicon layer, a 5 type tunneling oxide layer, a 6 type boron doped layer, a 7 type first metal electrode, a 8 type second polycrystalline silicon layer, a 9 type antireflection film layer, a 10 type carrier composite layer, a 11 type electron transport layer, a 12 type perovskite film layer, a 13 type hole transport layer, a 14 type transparent conductive oxide layer, a 15 type second metal electrode, a 16 type bottom cell, a 17 type small textured surface, a 18 type textured surface structure.

Detailed Description

Further advantages and effects of the invention will become readily apparent to those skilled in the art from the present disclosure, by the following description of the embodiments of the invention with reference to the specific examples.

The exemplary embodiments of the invention will now be described with reference to the drawings, however, the invention may be embodied in many different forms and is not limited to the embodiments described herein, which are provided to disclose the invention thoroughly and completely, and to fully convey the scope of the invention to those skilled in the art. The terminology used in the exemplary embodiments illustrated in the accompanying drawings is not intended to be limiting of the invention. In the drawings, like elements/components are referred to by like reference numerals.

Unless otherwise indicated, terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art. In addition, it will be understood that terms defined in commonly used dictionaries should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense.

Example 1

The invention provides a perovskite crystal silicon laminated bottom battery structure, which comprises a semiconductor substrate layer 2, wherein a boron doped layer 6, a passivation film layer 3 and a first metal electrode 7 with a suede structure 18 are sequentially arranged on the first surface of the semiconductor substrate layer 2 from inside to outside, a small suede 17, a tunneling oxide layer 5 and an N-type polycrystalline silicon layer 1 are sequentially arranged on the second surface of the semiconductor substrate layer 2 from inside to outside, and the N-type polycrystalline silicon layer 1 comprises at least two polycrystalline silicon layers which are alternately arranged in the horizontal direction and have different thicknesses, and the height of the small suede 17 is smaller than that of the suede structure 18.

According to the perovskite crystal silicon laminated bottom cell structure provided by the invention, the N-type polycrystalline silicon layers 1 are arranged into the polycrystalline silicon layers with different thicknesses which are alternately arranged, so that parasitic absorption of the polycrystalline silicon layers to photons is reduced, and the current output of the bottom cell 16 is improved. After ensuring that the parasitic photon absorption is reduced, the deposition thickness of the first polysilicon layer 4 can be properly increased, so that the naply can uniformly cover the nap surface under the condition that the second surface is the nap surface, the passivation level is ensured, and the conditions of exposure defects, increased carrier recombination and reduced battery performance are avoided.

Example 2

On the basis of embodiment 1, this embodiment provides a perovskite crystal silicon laminated bottom cell structure, as shown in fig. 1, the N-type polysilicon layer 1 includes a first polysilicon layer 4 and a second polysilicon layer 8, the thickness of the first polysilicon layer 4 is 10nm-400nm, the thickness of the second polysilicon layer 8 is 20% -90% of the thickness of the first polysilicon layer 4, and the second polysilicon layer 8 occupies 2% -45% of the area of the N-type polysilicon layer 1.

The small suede 17 has a height of 0.5 μm to 1.2 μm.

The preparation process is as follows:

Sequentially performing texturing and boron diffusion on a monocrystalline silicon wafer (a semiconductor substrate layer 2), removing a second surface by winding plating and polishing, secondarily texturing a small textured surface 17 on the second surface, oxidizing a tunneling oxide layer 5 by LPCVD, depositing an intrinsic polycrystalline silicon layer, performing phosphorus diffusion, laser processing a second polycrystalline silicon layer 8PSG, removing a first surface by winding plating, washing the second polycrystalline silicon layer 8 by adding alkali, depositing a passivation film layer 3 and H+ passivation, printing a metal electrode and sintering to obtain the bottom battery 16.

Example 3

The embodiment provides a preparation method of a perovskite crystal silicon laminated bottom cell structure, as shown in fig. 3, comprising the following steps:

etching by adopting alkali solution to form pyramid suede structures 18 with uniform size on the two sides of the semiconductor substrate layer 2;

removing the back surface around plating by using high-concentration HF, wherein the concentration of the HF is controlled to be 5-wt wt% to 20 wt%;

Step 4) preparing small suede 17 by secondary flocking, namely etching by adopting alkali solution, and forming small suede 17 with uniform small pyramid structure on the second surface of the semiconductor substrate layer 2, wherein the height of the small suede 17 is controlled to be 0.5-1.2 mu m;

step 5) depositing a tunneling oxide layer 5 and an intrinsic polycrystalline silicon layer, depositing the tunneling oxide layer 5 by LPCVD technology to a thickness of 1-5nm, and continuing to deposit the intrinsic polycrystalline silicon film to a thickness of 40-500nm;

Step 6) phosphorus diffusion, namely phosphorus diffusion is carried out on the intrinsic polycrystalline silicon layer by taking POCl ₃ as a diffusion source to form a phosphorus doped layer polycrystalline silicon layer and a PSG layer, wherein the thickness of the phosphorus doped first polycrystalline silicon layer 4 is 10-400nm, the thickness of the PSG is 10-100nm, the diffusion temperature is 700-900 ℃, and the doping concentration is 1-5E 20cm ^-3;

step 7) forming an alkaline washing second polysilicon layer 8 window, namely processing a PSG layer by utilizing laser, ablating SiOx to form the alkaline washing second polysilicon layer 8 window, wherein the ablation area is 1% -40%, and the parameters of the laser are that the output power is 10W-70W, the pulse repetition frequency is 5-20 kHz, the diameter of a laser spot is 5 Pm-15 Pm, and the laser beam speed is 30-60 mm/s;

Step 8) removing the first surface coiling plating, namely removing the back surface coiling plating by using HF;

Step 9) forming a second polysilicon layer 8 on the second surface, namely, alkali etching is carried out on a window of the second polysilicon layer 8 through alkali washing to form the second polysilicon layer 8, and N-type polysilicon layers 1 with the first polysilicon layers 4 and the second polysilicon layers 8 alternately arranged in the horizontal direction are obtained;

The etching depth of the second polysilicon layer 8 is 10% -80% of the first polysilicon layer 4 (namely, the second polysilicon layer 8 is 20% -90% of the thickness of the first polysilicon layer 4), the area of the second polysilicon layer 8 after alkali washing is 2% -45%, wherein the alkali solution is one or mixture of NaOH or KOH, the concentration of the alkali solution is 0.5-10wt%, the etching time is 10s-150s, the silicon wafer is washed by using HF/H ₂O₂ and NH ₃/H₂O₂ cleaning solution after etching, and then the silicon wafer is dried

Step 10) depositing a passivation film layer 3 and H ⁺ for passivation, namely depositing a passivation layer on the first surface of the semiconductor substrate layer 2, carrying out hydrogen passivation on the second surface of the semiconductor substrate layer 2, depositing the passivation film layer 3 and H ⁺ under the atmosphere of NH ₃, depositing one or more of SiOx or SiNx film layers by PECVD to form passivation, wherein the flow rate of NH ₃ is controlled to be 6000ml-20000ml by PECVD;

Step 11) printing and sintering, namely printing AgAl slurry on the first surface of the semiconductor substrate layer 2, and forming the front first metal electrode 7 after sintering.

According to the method, the polysilicon layer and the PSG layer with uniform thickness are firstly deposited on the second surface of the bottom battery 16, PSG on the second polysilicon layer 8 is firstly treated by utilizing laser according to different designed polysilicon thickness difference patterns, then partial polysilicon layers in the second polysilicon region of the bottom battery 16 are removed by utilizing alkali liquor, and finally, the mask of the first polysilicon layer 4 is cleaned and removed by utilizing the acid liquor, so that two or more polysilicon layers are alternately arranged according to the design, and the technical problems that excessive parasitic absorption is generated due to excessive thickness caused by the uniform thickness of the polysilicon layers, passivation effect of the bottom battery 16 is influenced due to excessive thickness, contact between the polysilicon layers and a transparent conductive layer is limited and the like are solved.

Example 4

The embodiment provides a perovskite/TOPCon laminated cell, as shown in fig. 2, which comprises a perovskite cell, a transparent conductive oxide layer 14 and a perovskite crystal silicon layer bottom cell structure which are sequentially arranged from top to bottom, wherein the transparent conductive oxide layer is connected with the second surface of the perovskite crystal silicon layer bottom cell structure;

The perovskite battery comprises a hole transmission layer 13, a perovskite film layer 12, an electron transmission layer 11, a carrier composite layer 10, an anti-reflection film layer 9 and a second metal electrode 15 which are sequentially arranged from inside to outside.

The bottom cell 16 of the laminated cell utilizes a wet method to remove part of polysilicon to form the N-type polysilicon layers 1 with different thicknesses, wherein the first polysilicon layers 4 and the second polysilicon layers 8 are alternately arranged, so that parasitic absorption of photons by the polysilicon layers is reduced, the current output of the bottom cell 16 is improved, the contact area of the polysilicon layers and the transparent conductive layers is improved due to the polysilicon alternating structure with different thicknesses, the interface contact resistance and the transverse transmission resistance can be reduced, the collection and the transmission of current between the bottom cell 16 and the top cell are facilitated, the cell filling is improved, and the cell efficiency is improved.

Example 5

The embodiment provides a preparation method of a perovskite/TOPCon laminated cell, which comprises the following steps:

S1, preparing a perovskite crystal silicon layer bottom cell structure, namely sequentially performing texturing and boron diffusion on a semiconductor substrate layer 2, removing a second surface, winding and plating, polishing, secondarily texturing a small textured surface 17 on the second surface, depositing an oxide tunneling oxide layer 5 and an intrinsic polycrystalline silicon layer, performing phosphorus diffusion, performing laser treatment on a second polycrystalline silicon layer 8PSG, removing a positive winding, plating and alkali washing to form a second polycrystalline silicon layer 8, depositing a passivation film layer 3 and H+ passivation, printing a first metal electrode 7, and sintering to obtain a bottom cell 16;

S2, preparing a transparent conductive oxide layer 14, namely preparing the transparent conductive oxide layer 14 on the second surface of the bottom battery 16 by PVD magnetron sputtering under the atmosphere that the air pressure is less than or equal to 1Pa and the argon-oxygen ratio is 1:0.02-0.1 and the power density is 1-3W/cm ²;

S3, preparing a hole transport layer 13, namely preparing a compact TiO ₂ layer at the high temperature of 400-550 ℃ by a spray pyrolysis method, wherein the thickness is 30-100 nm;

S4, preparing a perovskite film layer 12, wherein the band gap width of the perovskite layer is 1.3eV-1.8eV, the perovskite material structure is ABX ₃, wherein A is any one or a mixture of a plurality of cations in methylamine, formamidine and Cs, B is Pb or Sn, X is any one or a mixture of three anions in Cl, br and I, and the thickness of the perovskite film layer is 800nm-1200nm;

s5, preparing an electron transport layer 11, namely preparing an electron transport layer 11 material which is SnO ₂ on the perovskite thin film layer 12, wherein the thickness of the electron transport layer 11 material is 15-40 nm;

s6, preparing a carrier composite layer 10, namely preparing the carrier composite layer 10 on the electron transport layer 11, wherein the material is ITO, and the thickness is 30-100 nm;

S7, depositing an antireflection film layer 9;

and S8, printing AgAl slurry on the front surface of the laminated layer, and sintering to form a front second metal electrode 15 to obtain the perovskite crystal silicon laminated cell.

The perovskite crystal silicon laminated cell provided by the invention improves the contact area of the polycrystalline silicon layer and the transparent conductive layer, can reduce the interface contact resistance and the transverse transmission resistance, is beneficial to the collection and transmission of current between the bottom cell 16 and the top cell, improves the cell filling and improves the cell efficiency.

Example 6

On the basis of example 5, this example provides a method for preparing a perovskite/TOPCon stacked cell, comprising the following steps:

s1, etching by adopting low-concentration alkali solution, and forming a pyramid structure with uniform size on the two sides of a semiconductor substrate layer 2 silicon wafer (N-type monocrystalline silicon wafer, wherein the resistivity range is 1.0-7.0/(omega multiplied by m), the thickness is 100-200 mu m, and the size is 182 multiplied by 183.75 mm), wherein the low-concentration alkali solution is controlled to be 1-3wt%, the etching time is controlled to be 500S, the etching temperature is controlled to be 65-75 ℃, and the height is 1.2 mu m;

S2, boron diffusion, namely, using BCl ₃ as a diffusion source to diffuse on the first surface of the silicon wafer, and lightly doping an emitter, wherein the diffusion temperature is 500 ℃, and the diffusion sheet resistance is controlled at 200 omega/Sq;

s3, removing the second surface winding plating and polishing, namely removing the second surface winding plating by using high-concentration HF, wherein the concentration of the HF is controlled to be 6wt%;

s4, preparing a second surface small suede 17 by secondary texturing, namely etching the second surface of the silicon wafer by adopting a low-concentration alkali solution, wherein the small pyramid structure is uniform in size on the second surface of the silicon wafer, and the height of the suede is controlled to be 0.7 mu m, the low-concentration alkali solution is controlled to be 2wt%, the texturing time is controlled to be 100S, and the texturing temperature is controlled to be 60 ℃;

S5, depositing a tunneling oxide layer 5 and an intrinsic polycrystalline silicon layer on the second surface by using an LPCVD technology, wherein the thickness of the tunneling oxide layer 5 is 1.5nm, and continuously depositing an intrinsic polycrystalline silicon film with the thickness of 90 nm on the tunneling oxide layer 5 to form the intrinsic polycrystalline silicon layer;

S6, phosphorus diffusion, namely performing phosphorus diffusion on the intrinsic polycrystalline silicon layer by using POCl ₃ as a diffusion source to form a phosphorus doped layer and a PSG layer, wherein the thickness of the phosphorus doped first polycrystalline silicon layer 4 is 50nm, the thickness of the PSG is 40nm, the diffusion temperature is 700 ℃, and the doping concentration is 1E20cm ^-3;

S7, laser processing the second polysilicon layer 8PSG, namely, using laser processing the PSG layer, ablating SiOx to form a window for alkaline washing the second polysilicon layer 8, wherein the ablation area is 25%, and the parameters of the laser include output power 50W, pulse repetition frequency 10kHz, diameter 10Pm of a laser spot and laser beam speed 55mm/S;

S8, removing the first surface winding plating and alkali washing the second polysilicon layer 8, namely removing the back winding plating by using high-concentration HF, forming the second polysilicon layer 8 by using alkali liquor, etching 60% of the first polysilicon layer 4 with the depth of 20nm, and the area ratio of the second polysilicon layer 8 after alkali washing is 27%, wherein the alkali liquor is NaOH, the concentration of the alkali liquor is 3wt%, the etching time is 100S, and cleaning the silicon wafer by using HF/H ₂O₂ and NH ₃/H₂O₂ cleaning liquid after etching and then drying;

S9, depositing a passivation film layer 3 and H+ passivation, namely depositing a passivation layer on the first surface of the silicon wafer, depositing a SiNx film layer with the thickness of 30nm by PECVD, performing hydrogen passivation on the second surface of the silicon wafer, passivating the silicon wafer in an NH ₃ atmosphere, providing H+ by using PECVD as an instrument, and controlling the NH ₃ flow to 10000ml;

S10, printing, namely printing AgAl slurry on the first surface of a silicon wafer, and sintering to form a first metal electrode 7, wherein the structure of the prepared bottom battery is shown in figure 2;

S11, removing the SiNx film layer on the second surface of the bottom cell 16 by using HF with the concentration of 8wt%, and then preparing a layer of 80: 80 nm thick ITO material on the second surface of the TOPCon bottom cell 16 by using PVD magnetron sputtering equipment to serve as the transparent conductive oxide layer 14;

s12, preparing 50 nm thick TiO ₂ material on the transparent conductive oxide layer 14 by a spray thermal decomposition method to serve as a hole transport layer 13;

S13, preparing a perovskite thin film layer 121000 nm on the hole transport layer 13 by adopting spin coating;

s14, preparing a layer of 30 nm-thick SnO ₂ material serving as an electron transport layer 11 on the perovskite thin film layer 12 by using a spin coating method;

S15, preparing an ITO material with the thickness of 80 nm on the electron transport layer 11 by adopting PVD magnetron sputtering as a carrier composite layer 10;

s16, depositing a SiNx film layer (reflecting layer) with the thickness of 70nm on the front side by PECVD, printing AgAl slurry on the front side of the laminated layer, and sintering to form a front second metal electrode 15 to obtain the perovskite crystal silicon laminated cell, wherein the structure of the perovskite crystal silicon laminated cell is shown in figure 3.

To further explain the effect of the present invention in detail, the perovskite/TOPCon stacked cell prepared in example 6 and comparative examples 1 to 6 were compared in electrical properties.

Comparative example 1

Comparative example 1 the manufacturing method is different from example 6 in that the first polysilicon layer 4 is too thick.

In the preparation method of the bottom cell 16, the S5 tunneling oxide layer 5 and the intrinsic polysilicon layer are formed by depositing the tunneling oxide layer 5 with the thickness of 1.5nm on the second surface by LPCVD technology, and continuously depositing the intrinsic polysilicon film with the thickness of 600 nm on the upper tunneling oxide layer 5.

S6, phosphorus diffusion, namely performing phosphorus diffusion on the intrinsic polycrystalline silicon layer by using POCl ₃ as a diffusion source to form a phosphorus doped layer and a PSG layer, wherein the thickness of the phosphorus doped first polycrystalline silicon layer 4 is 550nm, the thickness of the PSG is 50nm, the diffusion temperature is 700 ℃, and the doping concentration is 1E20cm ^-3;

S7, laser processing the second polysilicon layer 8PSG, namely, using laser processing the PSG layer, ablating SiOx to form a window for alkaline washing the second polysilicon layer 8, wherein the ablation area is 25%, and the parameters of the laser are that the output power is 50W, the pulse repetition frequency is 10kHz, the diameter of a laser spot is 10Pm, and the laser beam speed is 55mm/S;

S8, removing a first surface winding plating and alkali washing a second polysilicon layer 8, namely removing back winding plating by using high-concentration HF, forming the second polysilicon layer 8 by using alkali liquor, etching 60% of the first polysilicon layer 4 with the depth of 330nm, and the area ratio of the second polysilicon layer 8 after alkali washing is 27%, wherein the alkali liquor is NaOH, the concentration of the alkali liquor is 3wt%, the etching time is 100S, and cleaning a silicon wafer by using HF/H ₂O₂ and NH ₃/H₂O₂ cleaning liquid after etching;

the rest of the procedure was the same as in example 6.

Comparative example 2

Comparative example 2 differs from example 6 in that the first polysilicon layer 4 is too thin in thickness.

In the preparation method of the bottom cell 16, the S5 tunneling oxide layer 5 and the intrinsic polysilicon layer are formed by depositing the tunneling oxide layer 5 with the thickness of 1.5nm on the second surface by LPCVD technology, and continuously depositing the intrinsic polysilicon film with the thickness of 20nm on the upper tunneling oxide layer 5.

S6, phosphorus diffusion, namely performing phosphorus diffusion on the intrinsic polycrystalline silicon layer by using POCl ₃ as a diffusion source to form a phosphorus doped layer and a PSG layer, wherein the thickness of the phosphorus doped first polycrystalline silicon layer 4 is 10nm, the thickness of the PSG is 10nm, the diffusion temperature is 700 ℃, and the doping concentration is 1E20cm ^-3;

S7, laser processing the second polysilicon layer 8PSG, namely, using laser processing the PSG layer, ablating SiOx to form a window for alkaline washing the second polysilicon layer 8, wherein the ablation area is 25%, and the parameters of the laser are that the output power is 30W, the pulse repetition frequency is 7kHz, the diameter of a laser spot is 10Pm, and the laser beam speed is 55mm/S;

S8, removing the first surface winding plating and alkali washing the second polysilicon layer 8, namely removing the back winding plating by using high-concentration HF, forming the second polysilicon layer 8 by using alkali liquor, etching 60% of the first polysilicon layer 4 with the depth of 6nm, and the area ratio of the second polysilicon layer 8 after alkali washing is 27%, wherein the alkali liquor is NaOH, the alkali liquor concentration is 1wt%, the etching time is 10S, and cleaning the silicon wafer by using HF/H ₂O₂ and NH ₃/H₂O₂ cleaning liquid after etching, and then drying.

The rest of the procedure was the same as in example 6.

Comparative example 3

Comparative example 3 the manufacturing method is different from example 6 in that the second polysilicon layer 8 is etched too deeply.

In the preparation method of the bottom cell 16, the S5 tunneling oxide layer 5 and the intrinsic polycrystalline silicon layer are formed by depositing the tunneling oxide layer 5 with the thickness of 1.5nm on the second surface by LPCVD technology, and continuously depositing the intrinsic polycrystalline silicon film with the thickness of 90 nm on the upper tunneling oxide layer 5.

S8, removing the first surface winding plating and alkali washing the second polysilicon layer 8, namely removing the back winding plating by using high-concentration HF, forming the second polysilicon layer 8 by using alkali liquor, etching 90% of the first polysilicon layer 4 with the depth of 5nm, and the area ratio of the second polysilicon layer 8 after alkali washing is 27%, wherein the alkali liquor is NaOH, the alkali liquor concentration is 5wt%, the etching time is 400S, and cleaning the silicon wafer by using HF/H ₂O₂ and NH ₃/H₂O₂ cleaning liquid after etching, and then drying.

The rest of the procedure was the same as in example 6.

Comparative example 4

Comparative example 4 the manufacturing method is different from example 6 in that the second polysilicon layer 8 is etched too shallow in depth.

s7, laser processing the second polysilicon layer 8PSG, namely, using laser processing the PSG layer, ablating SiOx to form a window for alkaline washing the second polysilicon layer 8, wherein the ablation area is 90%, and the parameters of the laser are that the output power is 50W, the pulse repetition frequency is 10kHz, the diameter of a laser spot is 10Pm, and the laser beam speed is 55mm/S;

S8, removing the first surface winding plating and alkali washing the second polysilicon layer 8, namely removing the back winding plating by using high-concentration HF, forming the second polysilicon layer 8 by using alkali liquor, etching 6% of the first polysilicon layer 4 with the depth of 47 nm, and the area ratio of the second polysilicon layer 8 after alkali washing is 27%, wherein the alkali liquor is NaOH, the alkali liquor concentration is 1wt%, the etching time is 10S, and cleaning the silicon wafer by using HF/H ₂O₂ and NH ₃/H₂O₂ cleaning liquid after etching, and then drying.

The rest of the procedure was the same as in example 6.

Comparative example 5

Comparative example 5 differs from example 6 in the preparation method in that the second polysilicon layer 8 has an excessively large area.

S7, laser processing the second polysilicon layer 8PSG, namely, using laser processing the PSG layer, ablating SiOx to form a window for alkaline washing the second polysilicon layer 8, wherein the ablation area is 70%, and the parameters of the laser are that the output power is 50W, the pulse repetition frequency is 10kHz, the diameter of a laser spot is 10Pm, and the laser beam speed is 55mm/S;

S8, removing the first surface winding plating and alkali washing the second polysilicon layer 8, namely removing the back winding plating by using high-concentration HF, forming the second polysilicon layer 8 by using alkali liquor, etching 60% of the first polysilicon layer 4 with the depth of 20nm, and 75% of the area of the second polysilicon layer 8 after alkali washing, wherein the alkali liquor is NaOH, the concentration of the alkali liquor is 3wt%, the etching time is 100S, and cleaning the silicon wafer by using HF/H ₂O₂ and NH ₃/H₂O₂ cleaning liquid after etching, and then drying.

The rest of the procedure was the same as in example 6.

Comparative example 6

Comparative example 6 is different from example 6 in that the second polysilicon layer 8 is not structurally provided, i.e., the second polysilicon layer 8 occupies 0% of the area.

S7, not laser processing the PSG layer;

S8, removing the first surface winding plating, namely removing the back surface winding plating by using high-concentration HF, cleaning the silicon wafer by using HF/H ₂O₂ and NH ₃/H₂O₂ cleaning liquid, and drying.

The rest of the procedure was the same as in example 6.

The perovskite/TOPCon stacked cell prepared in example 6 and comparative example 1-comparative example 6 was tested for electrical performance by measuring the current-voltage (IV) characteristic curve of the solar cell or module using a steady-state light source IV sorting test system developed by combining Shanghai wess with japan under-mountain electric installation. The method is based on photoelectric effect and circuit measurement technology, combines a steady-state light source to simulate standard illumination conditions, rapidly evaluates static electrical performance of a device, comprises static parameters such as open circuit voltage (Uoc), short circuit current (Isc), conversion efficiency (Eta) and the like, and specifically refers to international photovoltaic module test specifications such as IEC 61215, IEC 61730 and the like. The results are shown in Table 1.

Table 1 test results of battery performances of example 6 and comparative examples 1 to 6

As can be seen from Table 1, the perovskite/crystalline silicon stacked cell obtained by the preparation method provided in example 6 was higher in conversion efficiency than comparative examples 1 to 6. Therefore, the perovskite/crystalline silicon laminated cell with higher conversion efficiency can be prepared by the method provided by the embodiment 6 of the invention.

As shown in table 1, comparative example 1, which defines the first polysilicon layer 4 to be too thick as compared with example 6, produced perovskite crystal silicon laminate cells having lower current and filling parameters than example 6. It can be seen that the effect of the excessive thickness of the first polysilicon layer 4 on the current is large, resulting in a reduction in the conversion efficiency of the fabricated perovskite/crystalline silicon stacked cell.

Comparative example 2 the first polysilicon layer 4 defined was too thin compared to example 6. It can be seen that too thin a first polysilicon layer 4 can result in poor passivation of the bottom cell 16, resulting in reduced on-voltage, current and fill of the perovskite stacked cell, which is primarily manifested in on-voltage, resulting in reduced conversion efficiency of the resulting perovskite/crystalline silicon stacked cell.

Comparative example 3 and comparative example 4 differ in etching depth of the second polysilicon layer 8 from example 6. The etching depth of the second polysilicon layer 8 of comparative example 3 is too deep, resulting in poor passivation of the bottom cell 16, so that the voltage of the perovskite stacked cell is significantly reduced, resulting in reduced conversion efficiency of the fabricated perovskite/crystalline silicon stacked cell, while the etching depth of the second polysilicon layer 8 of comparative example 4 is too shallow, resulting in more parasitic absorption of the second polysilicon layer 8, so that the current of the perovskite stacked cell is significantly reduced, resulting in reduced conversion efficiency of the fabricated perovskite/crystalline silicon stacked cell.

Comparative example 5 and comparative example 6 have different footprints of the second polysilicon layer 8 compared to example 6. It can be seen that when the second polysilicon layer 8 is too large in its area, it affects the passivation effect of the bottom cell 16, resulting in reduced on-voltage, current and filling, and when the second polysilicon layer 8 is not provided, the parasitic absorption of photons by the polysilicon layer is strong, resulting in a significant reduction in current, resulting in a reduction in the conversion efficiency of the fabricated perovskite/crystalline silicon laminate cell.

The foregoing examples are merely illustrative of the present invention and are not intended to limit the scope of the invention, and all designs that are the same or similar to the present invention are within the scope of the invention.

Claims

1. A perovskite crystalline silicon stacked bottom cell structure, characterized in that it includes a semiconductor substrate layer, wherein the first surface of the semiconductor substrate layer is provided with a boron-doped layer, a passivation film layer and a first metal electrode with a velvet structure from the inside to the outside, and the second surface of the semiconductor substrate layer is provided with a small velvet, a tunneling oxide layer and an N-type polysilicon layer from the inside to the outside, wherein the N-type polysilicon layer includes at least two polysilicon layers arranged alternately in the horizontal direction and having different thicknesses, and the height of the small velvet is less than the height of the velvet structure.

2. A perovskite crystalline silicon stacked bottom cell structure according to claim 1, characterized in that: the N-type polysilicon layer includes a first polysilicon layer and a second polysilicon layer, the thickness of the first polysilicon layer is 10nm-400nm, the thickness of the second polysilicon layer is 20%-90% of the thickness of the first polysilicon layer, and the second polysilicon layer occupies 2%-45% of the area of the N-type polysilicon layer.

3. The perovskite crystalline silicon stacked bottom cell structure according to claim 1, wherein the height of the small suede surface is 0.5 μm-1.2 μm.

4. A method for preparing a perovskite crystalline silicon stacked bottom cell structure according to claim 2, characterized in that it comprises the following steps:

Step 1) Texturing: using alkaline solution etching to form a pyramid texture structure of uniform size on both sides of the semiconductor substrate layer;

Step 2) Boron diffusion: Using BCl ₃ as the diffusion source, the diffusion temperature is 500 ℃-900 ℃, and the diffusion resistance is controlled at 200-500Ω/Sq;

Step 3) removing the second surface of the semiconductor substrate layer from the coating and polishing;

Step 4) Secondary texturing to prepare a small textured surface: using an alkaline solution to etch, a small textured surface with a small pyramid structure of uniform size is formed on the second surface of the semiconductor substrate layer;

Step 5) depositing a tunnel oxide layer and an intrinsic polysilicon layer;

Step 6) Phosphorus diffusion: Using POCl ₃ as a diffusion source, phosphorus is diffused in the intrinsic polysilicon layer to form a phosphorus-doped polysilicon layer and a PSG layer;

Step 7) Forming an alkali-washed second polysilicon layer window: Using laser to process the PSG layer, ablating SiOx to form an alkali-washed second polysilicon layer window, with the ablation area being 1%-40%;

Step 8) Plating the first surface;

Step 9) forming a second polysilicon layer on the second surface: alkali-washing the second polysilicon layer window and then etching with alkaline solution to form the second polysilicon layer, thereby obtaining an N-type polysilicon layer in which the first polysilicon layer and the second polysilicon layer are alternately arranged in a horizontal direction; after etching, the semiconductor substrate layer is cleaned with a cleaning solution and then dried;

Step 10) Deposition of a passivation film layer and H ⁺ passivation: Depositing a passivation layer on the first surface of the semiconductor substrate layer; Performing hydrogen passivation on the second surface of the semiconductor substrate layer, using an _NH3 atmosphere to deposit the passivation film layer and H ⁺ ;

Step 11) Printing and sintering: Printing AgAl paste on the first surface of the semiconductor substrate layer and sintering to form a front first metal electrode.

5. The method for preparing a perovskite crystalline silicon stacked bottom cell structure according to claim 4, characterized in that: in step 5), the tunneling oxide layer and the intrinsic polysilicon layer are deposited using LPCVD technology, the thickness of the deposited tunneling oxide layer is 1nm-5nm, and the thickness of the deposited intrinsic polysilicon film is 40nm-500nm.

6 . The method for preparing a perovskite crystalline silicon stacked bottom cell structure according to claim 4 , wherein the phosphorus diffusion temperature in step 6) is 700° C.-900° C., the doping concentration is 1-5E20 cm ⁻³ , and the thickness of the PSG layer is 10 nm-100 nm.

7. The method for preparing a perovskite silicon tandem bottom cell structure according to claim 4, characterized in that: in step 7), the laser output power is 10W-70W, the pulse repetition frequency is 5kHz-20kHz, the laser spot diameter is 5pm-15pm, and the laser beam speed is 30mm/s-60mm/s.

8. The method for preparing a perovskite crystalline silicon layer bottom cell structure according to claim 4, characterized in that: in step 9), the alkaline solution is NaOH or KOH or a mixture thereof, the concentration of the alkaline solution is 0.5wt%-10wt%, and the etching time is 10s-150s.

9. A perovskite/TOPCon tandem cell, comprising: a perovskite cell, a transparent conductive oxide layer, and the perovskite crystalline silicon bottom cell structure according to any one of claims 1 to 3, arranged sequentially from top to bottom, wherein the transparent conductive oxide layer is in contact with the second surface of the perovskite crystalline silicon bottom cell structure;

The perovskite battery comprises a hole transport layer, a perovskite thin film layer, an electron transport layer, a carrier recombination layer, an anti-reflection film layer and a second metal electrode, which are arranged in sequence from the inside to the outside.

10. A method for preparing a perovskite/TOPCon tandem cell according to claim 9, characterized in that it comprises the following steps:

S1, preparation of the bottom cell structure of the perovskite crystalline silicon layer: the semiconductor substrate layer is sequentially textured and boron diffused, the second surface is polished after de-plating, the second surface is textured again to form a small velvet surface, an oxide tunneling oxide layer and an intrinsic polysilicon layer are deposited, followed by phosphorus diffusion, the second polysilicon layer PSG is laser treated, the positive de-plating is performed and alkaline washing is performed to form the second polysilicon layer, a passivation film layer and H+ passivation are deposited, the first metal electrode is printed and sintered to obtain the bottom cell;

S2, preparing a transparent conductive oxide layer: using PVD magnetron sputtering to prepare a transparent conductive oxide layer on the second surface of the bottom cell under an atmosphere of a pressure of ≤1 Pa and an argon-oxygen ratio of 1:0.02-0.1 at a power density of 1-3 W/cm ² ;

S3, preparation of hole transport layer: preparation of dense _TiO2 layer with thickness of 30nm-100nm at high temperature of 400℃-550℃ by spray pyrolysis method;

S4, preparing a perovskite thin film layer: the band gap width of the perovskite layer is 1.3eV-1.8eV, the perovskite material structure is ABX ₃ , wherein A is any one of methylamine, formamidine, and Cs or a mixture of several cations, B is Pb or Sn, and X is any one of Cl, Br, and I or a mixture of three anions, and the thickness is 800nm-1200nm;

S5, preparing an electron transport layer: preparing an electron transport layer made of SnO ₂ on the perovskite film layer, with a thickness of 15nm-40nm;

S6, preparing a carrier recombination layer: preparing a carrier recombination layer on the electron transport layer, the material of which is ITO with a thickness of 30 nm to 100 nm;

S7, depositing an anti-reflection film layer;

S8, printing AgAl paste on the front side of the stack, forming the second metal electrode on the front side after sintering to obtain a perovskite crystalline silicon stacked battery.