CN120803352A - Data storage method and storage device - Google Patents

Abstract

The application relates to the technical field of memories and discloses a data storage method and a storage device, wherein the method is applied to a nonvolatile memory module, the nonvolatile memory module comprises a plurality of memory blocks, each memory block is configured with an open memory page and a reserved memory page, and when a data writing instruction to a target logical address is detected, a mapping physical address exists in response to the target logical address, and the target open memory page corresponding to the mapping physical address is determined; and storing the write data aiming at the target logic address in the target reserved storage page, and keeping the effective page count value of the target storage block unchanged. And the target memory block is prevented from frequently triggering garbage collection through the reserved memory page, so that the reading and writing efficiency is improved.

Description

Data storage method and storage device

Technical Field

The present application relates to the field of memory technologies, and in particular, to a data storage method and a storage device.

Background

Commercial grade SSD NAND (Solid STATE DRIVE, solid state disk) is a tightly associated storage technology with NAND flash memory, which is the core storage medium of SSDs) is often of inferior quality to enterprise grade SSDs, so garbage collection, wear leveling, resolution of read disturbances, data retention and bad block management require more frequent operations.

The granule characteristics determine that many invalid data are necessarily generated when the SSD is used, garbage collection needs to be frequently carried out, and after the SSD is operated for a period of time, the read-write efficiency of the SSD is obviously deteriorated due to more operations.

Disclosure of Invention

Accordingly, an object of the present application is to overcome the shortcomings of the prior art, and to provide a data storage method applied to a storage device configured with a nonvolatile memory module, the nonvolatile memory module including a plurality of memory blocks, each memory block of the nonvolatile memory module being configured with an open memory page and a reserved memory page, the method comprising:

When a data writing instruction to a target logical address is detected, determining a target open storage page corresponding to a mapping physical address in response to the existence of the mapping physical address in the target logical address;

selecting an idle target reserved storage page from a target storage block where the target open storage page is located;

storing write data for the target logical address in the target reserved memory page, and leaving a valid page count value of the target memory block unchanged.

In an embodiment, after the step of storing the write data for the target open memory page in the target reserved memory page, the method comprises:

And modifying the physical address corresponding to the target logical address in the address mapping table into the physical address corresponding to the target reserved storage page.

In an embodiment, the method further comprises:

Marking the target open storage page in a preset valid indication mapping table as invalid, and marking the target reserved storage page as valid;

and updating the use quantity of the reserved storage pages corresponding to the target storage block in a preset reserved storage page use count table.

In an embodiment, the method further comprises:

and triggering garbage collection for the target storage block in response to the valid page count value being less than a preset threshold.

In an embodiment, the method further comprises:

When triggering garbage collection of the target storage block, determining whether a non-idle reserved storage page exists in the target storage block according to a count value in the reserved storage page usage count table, and

And determining the non-idle reserved storage page based on the effective indication mapping table, performing garbage collection on data in the non-idle reserved storage page, and performing garbage collection on data in the open storage page.

In an embodiment, the method further comprises:

When a data rollback instruction aiming at a target storage page in the target storage block is detected, extracting a linked list of the target storage page from a preset storage page linked list, wherein a change chain of the storage page when data is rewritten is stored in the preset storage page linked list;

and searching target rollback data corresponding to the data rollback instruction according to the linked list of the target storage page.

In an embodiment, the method further comprises:

When the target storage block triggers garbage collection, positioning effective cold data and effective hot data stored in the target storage block according to the chain table length of each storage page of the target storage block in the preset storage page chain table;

and storing the effective cold data and the effective hot data separately when garbage is recovered.

In an embodiment, the method further comprises:

when detecting that a bad memory page exists in the target memory block, selecting a replacement reserved memory page to replace the bad memory page in the target memory block;

and recording the mapping relation between the bad memory page and the replacement reserved memory page in a preset memory page mapping table, or recording the mapping relation between the bad memory page and the replacement reserved memory page in a metadata area of the target memory block.

In an embodiment, the method further comprises:

and if the number of the reserved memory pages in the target memory block is smaller than a preset number threshold, marking the target memory block as a non-rewritable memory block.

The present application also provides an apparatus comprising:

a connection interface for connecting to a host system;

nonvolatile memory module

A memory controller connected to the connection interface and the nonvolatile memory module;

the memory controller is used for implementing the data storage method.

The embodiment of the application has the following beneficial effects:

When a data writing instruction to a target logic address is detected, a mapping physical address exists in response to the target logic address, a target open storage page corresponding to the mapping physical address is determined, an idle target reserved storage page is selected from a target storage block of the target open storage page, writing data aiming at the target logic address is stored in the target reserved storage page, and the effective page count value of the target storage block is kept unchanged. By storing the writing data in the reserved storage page, the effective page count value of the target storage block can be kept unchanged, namely the speed of reducing the available capacity of the target storage block is slowed down, and further, the frequent triggering of garbage collection is avoided, so that the reading and writing efficiency is improved.

Drawings

In order to more clearly illustrate the technical solutions of the present application, the drawings that are required for the embodiments will be briefly described, it being understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope of the present application. Other relevant drawings may be made by those of ordinary skill in the art without undue burden from these drawings.

FIG. 1 is a schematic diagram of a cache management apparatus according to the present application;

FIG. 2 is a schematic flow chart of a first embodiment provided by the present application;

FIG. 3 is a schematic diagram of a page distribution in a memory block according to the present application;

FIG. 4 is a schematic flow chart of a second embodiment provided by the present application;

FIG. 5 is a schematic flow chart of a third embodiment provided by the present application;

FIG. 6 is a schematic flow chart of a fourth embodiment provided by the present application;

FIG. 7 is a schematic flow chart of a fifth embodiment provided by the present application;

FIG. 8 is a schematic flow chart of a sixth embodiment provided by the present application;

FIG. 9 is a schematic flow chart of a seventh embodiment provided by the present application;

FIG. 10 is a diagram illustrating the memory page map provided by the present application.

Detailed Description

The following description of the embodiments of the present application will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present application, but not all embodiments.

The components of the embodiments of the present application generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the application, as presented in the figures, is not intended to limit the scope of the application, as claimed, but is merely representative of selected embodiments of the application. All other embodiments, which can be made by a person skilled in the art without making any inventive effort, are intended to be within the scope of the present application.

The terms "comprises," "comprising," "including," or any other variation thereof, are intended to cover a specific feature, number, step, operation, element, component, or combination of the foregoing, which may be used in various embodiments of the present application, and are not intended to first exclude the presence of or increase the likelihood of one or more other features, numbers, steps, operations, elements, components, or combinations of the foregoing.

Furthermore, the terms "first," "second," "third," and the like are used merely to distinguish between descriptions and should not be construed as indicating or implying relative importance.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which various embodiments of the application belong. The terms (such as those defined in commonly used dictionaries) will be interpreted as having a meaning that is the same as the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein in connection with the various embodiments of the application.

It will be appreciated that as shown in fig. 1, the present application provides a storage device, which includes a connection interface for connecting to a host system, a nonvolatile memory module, and a memory controller connected to the connection interface and the nonvolatile memory module, wherein the memory controller is configured to perform the data storage method disclosed in the present application.

Specifically, the host system is electrically connected to the storage device through the connection interface to perform data access operation. The memory controller includes a processor (also referred to as a first processor), a data management Circuit (DATA MANAGEMENT Circuit), a memory interface control Circuit (Memory Interface Control Circuit), and a buffer memory. The processor may be an integrated circuit chip with signal processing capabilities. The processor may be a general purpose processor including at least one of a central processing unit (Central Processing Unit, CPU), a network processor (Network Processor, NP), a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic device, discrete hardware components. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like that may implement or perform the methods, steps, and logic blocks disclosed in embodiments of the present application.

It is to be understood that the data storage method disclosed in the present application is applied to a storage device configured with a nonvolatile memory module.

Wherein the non-volatile memory module comprises a plurality of chips, each chip being further subdivided into a plurality of planes, and each plane in turn comprising a plurality of memory blocks. In addition, each memory block further includes a plurality of memory pages, and each memory page includes a plurality of memory cells. It should be noted that the present disclosure is not limited to the size of each memory page and logical page.

In the present embodiment, an open memory page and a reserved memory page are configured in each memory block. Specifically, the plurality of memory pages in each memory block are divided into open memory pages for performing operations such as writing and reading of data and reserved memory pages.

Some embodiments of the present application are described in detail below with reference to the accompanying drawings. The embodiments described below and features of the embodiments may be combined with each other without conflict.

Referring to fig. 2, fig. 2 is a flow chart of a first embodiment of the present application, and the method includes:

Step S101, when a data writing instruction to a target logical address is detected, a target open storage page corresponding to a mapping physical address is determined in response to the existence of the mapping physical address in the target logical address.

It should be noted that the memory controller will build an address mapping table to record mapping information between logical addresses and physical addresses. In conventional memory management, a memory controller typically establishes a Logical To PHYSICAL ADDRESS MAPPING table and a physical To Logical mapping table (Physical To Logical ADDRESS MAPPING table) for searching for physical units (e.g., physical erasure units/physical blocks/memory blocks, physical programming units/physical pages/memory pages) mapped by Logical units (e.g., logical blocks, logical pages) and for searching for Logical units mapped by physical units.

In this embodiment, when detecting a data write instruction to a target logical address, the memory controller queries the address mapping table, determines a mapped physical address corresponding to the target logical address, and determines a corresponding target open memory page according to the mapped physical address. The data write command detected by the memory controller is a second data write command to the target logical address, and at this time, the memory controller determines a mapped physical address of the last data write of the target logical address according to the mapping relationship of the target logical address in the address mapping table, and further determines a corresponding target open memory page according to the mapped physical address.

Step S102, selecting an idle target reserved storage page from the target storage block where the target open storage page is located.

In this embodiment, after determining the target open memory page, the memory controller may determine a corresponding target memory block according to the target open memory page, and then select an idle target reserved memory page from the target memory blocks. It should be noted that, the nonvolatile memory module includes a plurality of memory blocks, each memory block corresponds to a plurality of open memory pages, the nonvolatile memory module can determine the corresponding target memory block according to the physical address of the target open memory page, and the reserved memory page of each memory block is specially reserved for overwriting the open memory page in the memory block and replacing the bad memory page in the memory block, and the reserved memory page is not opened for other memory blocks.

Exemplary, as shown in fig. 3, fig. 3 is a schematic diagram of a memory page distribution in a memory block, where pages are memory pages, pages 1 to 16 are open memory pages of the memory block, and pages 17 to 24 are reserved memory pages of the memory block. When the memory controller determines that the target open memory page is page1, an idle page is arbitrarily selected from pages 17 to 24.

Step S103, storing the write data for the target logical address in the target reserved memory page.

In this embodiment, the memory controller stores the write data for the target logical address in the target reserved memory page after determining the free target reserved memory page. Illustratively, as shown in fig. 3, when the memory controller determines that the target open memory page is page1, the selected free target reserved memory page is page17, the write data for the target logical address is stored in page 17.

Step S104, keeping the effective page count value of the target storage block unchanged.

In the present embodiment, the memory controller counts the number of effective memory pages in each memory block as an effective page count value. The effective storage page is a storage page which can be used for executing operations such as data writing and reading in the current storage block, and in an initial state, the open storage page is an effective storage page, and the reserved storage page is an invalid storage page. When the data in an open memory page is invalidated, the open memory page becomes an invalid memory page, and the open memory page cannot be used for data writing and reading.

The memory controller stores the write data for the target logical address in a target reserved memory page of the target memory block, replaces the target open memory page with the target reserved memory page, and the effective page count value of the target memory block is unchanged.

The memory controller of the embodiment responds to the existence of a mapping physical address of a target logical address when detecting a data writing instruction to the target logical address, determines a target open memory page corresponding to the mapping physical address, selects an idle target reserved memory page from a target memory block of the target open memory page, stores writing data aiming at the target logical address in the target reserved memory page, and keeps the effective page count value of the target memory block unchanged. By storing the writing data in the reserved memory pages, the speed of reducing the effective memory pages of the target memory block can be slowed down, so that the frequent triggering of garbage collection is avoided, and the reading and writing efficiency is improved.

Referring to fig. 4, fig. 4 is a flowchart of a second embodiment of the present application, which is different from the first embodiment in that after the step of storing the write data for the target logical address in the target reserved memory page, the method includes:

Step S201, modifying the physical address corresponding to the target logical address in the address mapping table to the physical address corresponding to the target reserved storage page.

In this embodiment, after the memory controller stores the write data for the target logical address in the target reserved memory page, the mapped physical address corresponding to the target logical address in the address mapping table is modified to the physical address corresponding to the target reserved memory page.

For example, when data is written to the target logical address for the first time, the memory controller stores the written data in the target open memory page1, and at this time, the physical address corresponding to the target logical address recorded in the address mapping table is the physical address corresponding to page1, and when data is written to the target logical address for the second time, the memory controller stores the written data in the target reserved memory page17, and at this time, the physical address corresponding to the target logical address recorded in the address mapping table is modified from the physical address corresponding to page1 to the physical address corresponding to page 17. It will be understood that, when writing data to the target logical address for the third time, the memory controller stores the write data in the target reserved storage page18, and at this time, the physical address corresponding to the target logical address recorded in the address mapping table is modified from the physical address corresponding to the page17 to the physical address corresponding to the page18, and the physical address modification process in the address mapping table for writing data to the target logical address each time is similar, which is not repeated.

Step S202, marking the target open storage page in a preset valid indication mapping table as invalid, and marking the target reserved storage page as valid.

In this embodiment, the memory controller establishes an effective indication mapping table for each memory block, in which the availability of each memory page in the memory block is recorded. In the initial state, all open memory pages are marked as valid in the valid indication mapping table, and all reserved memory pages are marked as invalid. After the memory controller stores the write-in data aiming at the target logical address in the target reserved memory page, marking the target open memory page in the preset valid indication mapping table as invalid, and marking the target reserved memory page as valid. For example, the memory controller stores the write data in the target reserved memory page17, at this time, the corresponding physical address of the target logical address recorded in the address mapping table is modified from the physical address corresponding to the page1 to the physical address corresponding to the page17, and in the preset valid indication mapping table, the page1 is marked as invalid, and the page17 is marked as valid.

Step S203, updating the number of reserved memory pages corresponding to the target memory block in the preset reserved memory page usage count table.

In this embodiment, the memory controller establishes a reserved memory page usage count table indicating the number of reserved memory pages used in each memory block. After the writing data aiming at the target logical address is stored in the target reserved storage page, the reserved storage page use quantity corresponding to the target storage block in the preset reserved storage page use count table is updated. Illustratively, the memory controller stores the write data in the target reserved memory page17, then the reserved memory page usage of the target memory block in the table is incremented by 1. It should be noted that the number of reserved memory pages recorded in the reserved memory page usage count table is only increased or not decreased.

After the write data for the target logical address is stored in the target reserved storage page, the memory controller in this embodiment modifies the physical address corresponding to the target logical address in the address mapping table into the physical address corresponding to the target reserved storage page, marks the target open storage page in the preset valid indication mapping table as invalid, marks the reserved storage page as valid, and updates the use number of the reserved storage page corresponding to the target storage block in the preset reserved storage page use count table. The method and the device can facilitate subsequent inquiry of other operations aiming at the target logical address, avoid errors of other operations aiming at the target logical address, and reduce the risk of abnormality of the nonvolatile memory module.

Referring to fig. 5, fig. 5 is a flow chart of a third embodiment of the present application, which is different from the first embodiment to the second embodiment in that the method further includes:

in step S301, garbage collection for the target storage block is triggered in response to the valid page count value being less than a preset threshold.

In this embodiment, when detecting a data write instruction to a target logical address, the memory controller queries the address mapping table, determines a mapped physical address corresponding to the target logical address, and opens a memory page according to a target corresponding to the mapped physical address. After determining the target open memory page, the memory controller may determine a corresponding target memory block according to the target open memory page, and then select an idle target reserved memory page from the target memory blocks. After determining the free target reserved memory page, the memory controller stores the write data for the target logical address in the target reserved memory page. Since the memory controller stores the write data for the target logical address in the target reserved memory page of the target memory block, the effective page count value of the target memory block is unchanged.

It will be appreciated that when the memory controller detects a data write instruction to the target logical address, there is no free reserved page in the target memory block, write data for the target logical address is stored in the free open page in the target memory block or in another free open page in the target memory block, and the effective page count value of the target memory block is decremented by 1.

And when the memory controller detects a data erasing instruction to the target logical address, the target open memory page corresponding to the target logical address becomes an invalid memory page, and the effective page count value of the target memory block where the target open memory page is located is decremented by 1.

After a period of time, the memory controller detects that the effective page count value of the target memory block is smaller than a preset threshold value, and triggers garbage collection aiming at the target memory block. The garbage collection refers to unified transportation and storage of effective data in a target storage block into another storage block, and the storage space of the target storage block is released for storing new data.

It can be understood that after garbage collection aiming at the target storage block is triggered, effective data carrying can be directly executed on the target storage block, or the target storage block is taken as the storage block to be garbage collected, and when the storage blocks triggering garbage collection in the nonvolatile storage module meet the preset quantity, the effective data carrying is executed on all the storage blocks to be garbage collected together.

It should be noted that, the memory controller may determine the valid page count value by querying a preset valid indication mapping table, where the valid page count value refers to the number of memory pages marked as valid in the valid indication mapping table in the target memory block.

The memory controller of the embodiment responds to the fact that a mapping physical address exists in a target logical address when a data writing instruction for the target logical address is detected, a target open memory page corresponding to the mapping physical address is determined, an idle target reserved memory page is selected from a target memory block of the target open memory page, writing data for the target logical address is stored in the target reserved memory page, an effective page count value of the target memory block is kept unchanged, and garbage collection for the target memory block is triggered when the effective page count value of the target memory block is detected to be smaller than a preset threshold value. By storing the writing data in the reserved storage page, the effective page count value of the target storage block can be kept unchanged, so that frequent triggering of garbage collection is avoided, and the reading and writing efficiency is improved.

Referring to fig. 6, fig. 6 is a flow chart of a fourth embodiment of the present application, and the fourth embodiment is different from the first embodiment to the third embodiment in that the method further includes:

step S401, when triggering garbage collection of the target storage block, determining whether a non-idle reserved storage page exists in the target storage block according to a count value in the reserved storage page usage count table.

In this embodiment, when the memory controller triggers garbage collection of the target memory block, it determines whether there is a non-free reserved memory page in the target memory block according to the count value in the reserved memory page usage count table. It is understood that when none of the reserved memory pages in the target memory block is used, the count value in the reserved memory page usage count table is 0, and when the reserved memory pages in the target memory block are used, the count value in the reserved memory page usage count table is the number of reserved memory pages used in the target memory block.

Step S402, determining the non-idle reserved memory page based on the valid indication mapping table, performing garbage collection on the data in the non-idle reserved memory page, and performing garbage collection on the data in the open memory page.

In this embodiment, when determining that a non-idle reserved storage page exists in the target storage block according to the count value in the reserved storage page usage count table, the memory controller determines which reserved storage pages are non-idle reserved storage pages based on the record of the valid indication mapping table, and performs garbage collection on data in the non-idle reserved storage pages first, and then performs garbage collection on data in the open storage pages. It will be appreciated that the validity indication map stores a flag of whether each open memory page in the target memory block is valid and a flag of whether each reserved memory page is valid, and each reserved memory page marked as valid is a non-idle reserved memory page.

When triggering garbage collection on the target storage block and determining that the target storage block has a non-idle reserved storage page, the memory controller of the embodiment firstly carries out garbage collection on data in the non-idle reserved storage page and then carries out garbage collection on data in the open storage page, so that the influence of discontinuous operation between the reserved storage page and the open storage page on the garbage collection speed can be avoided, and the operation efficiency is improved.

Referring to fig. 7, fig. 7 is a flow chart of a fifth embodiment of the present application, and the fifth embodiment is different from the first embodiment to the fourth embodiment in that the method further includes:

Step S501, when a data rollback instruction for a target storage page in the target storage block is detected, extracting a linked list of the target storage page from a preset storage page linked list, where a change chain of the storage page when data is rewritten is stored.

In this embodiment, the memory controller establishes a memory page linked list for each memory block, and stores a memory page change chain of data of each open memory page in the target memory block in the overwriting process. And when the memory controller detects a data rollback instruction aiming at a target memory page in the target memory block, extracting a linked list of the target memory page from a preset memory page linked list. For example, the write data of the target logical address is stored in the open memory page1 for the first time, in the reserved memory page17 for the second time, in the reserved memory page18 for the third time, and the change chain of the memory pages in the corresponding writing process is page1, page17, page18.

Step S502, searching target rollback data corresponding to the data rollback instruction according to the linked list of the target storage page.

In this embodiment, the memory controller searches for target rollback data corresponding to the data rollback instruction according to the linked list of the target storage page. The target storage page is exemplified as an open storage page1, the corresponding linked list is page 1- & gt page 17- & gt page18, and the target rollback data corresponding to the data rollback instruction is the data of the second step, so that the memory controller takes the data stored in the page17 as the target rollback data.

When detecting a data rollback instruction for a target storage page in a target storage block, the memory controller of the embodiment extracts a linked list of the target storage page according to a storage page linked list of the target storage block, and further determines target rollback data corresponding to the data rollback instruction. Because the data rewriting of the application is the reserved memory page stored in the same memory block, the situation that whether the source data is cleared or not is not determined and the data rollback is difficult to realize can be avoided when the data is rewritten to other memory blocks, and the reliability of the data rollback is further ensured.

Referring to fig. 8, fig. 8 is a flow chart of a sixth embodiment of the present application, and the sixth embodiment is different from the first embodiment to the fifth embodiment in that the method further includes:

Step S601, when the target storage block triggers garbage collection, locating effective cold data and effective hot data stored in the target storage block according to a link table length of each storage page of the target storage block in the preset storage page link table;

In this embodiment, when the target memory block triggers garbage collection, the memory controller locates valid cold data and valid hot data stored in the target memory block according to a link table length of each memory page of the target memory block in a preset memory page link table. It will be understood that the linked list length of each storage page corresponds to the rewriting frequency of the stored data, the longer the linked list length is, the higher the rewriting frequency of the stored data is, the shorter the linked list length is, the lower the rewriting frequency of the stored data is, the memory controller compares the linked list length of each storage page with a linked list length threshold set in advance, if the linked list length is greater than the linked list length threshold, the stored data is determined to be valid hot data, and if the linked list length is not greater than the linked list length threshold, the stored data is determined to be valid cold data.

And step S602, the effective cold data and the effective hot data are stored separately when garbage collection is performed.

In this embodiment, the memory controller separately stores valid cold data and valid hot data when garbage collection is performed. It will be appreciated that the memory controller, when performing garbage collection, transfers valid hot data to other memory blocks for storing hot data and valid cold data to other memory blocks for storing cold data.

When the target storage block triggers garbage collection, the memory controller of the embodiment locates the effective cold data and the effective hot data stored in the target storage block according to the link table length of each storage page of the target storage block in the preset storage page link table, and then separately stores the effective cold data and the effective hot data. And when garbage is recovered, the effective cold data and the effective hot data are separated and stored in different storage blocks, so that write amplification in garbage recovery is reduced.

Referring to fig. 9, fig. 9 is a flow chart of a seventh embodiment of the present application, and the seventh embodiment is different from the first embodiment to the sixth embodiment in that the method further includes:

in step S701, when it is detected that there is a bad memory page in the target memory block, a replacement reserved memory page is selected in the target memory block to replace the bad memory page.

In this embodiment, when the memory controller detects that there is a bad memory page in the target memory block, the memory controller selects a replacement reserved memory page in the target memory block instead of the bad memory page. It is understood that the memory controller acquires a free reserved memory page as a replacement reserved memory page in all reserved memory blocks in the target memory block.

In step S702, a mapping relationship between the bad memory page and the replacement reserved memory page is recorded in a preset memory page mapping table, or a mapping relationship between the bad memory page and the replacement reserved memory page is recorded in a metadata area of the target memory block.

In this embodiment, the memory controller records the mapping relationship between the bad memory page and the replacement reserved memory page in a preset memory page mapping table, or records the mapping relationship between the bad memory page and the replacement reserved memory page in the metadata area of the target memory block. As shown in fig. 10, the preset memory page mapping table includes each bad memory page and its corresponding replacement reserved memory page in the target memory block, when detecting that the open memory page1 is a bad memory page and selecting the replacement reserved memory page as page20, the bad memory page1 and the corresponding replacement reserved memory page20 are recorded in the memory page mapping table, when detecting that the open memory page15 is a bad memory page and selecting the replacement reserved memory page as page23, the bad memory page15 and the corresponding replacement reserved memory page23 are recorded in the memory page mapping table.

When detecting that a bad memory page exists in a target memory block, the memory controller of the embodiment selects a replacement reserved memory page to replace the bad memory page in the target memory block, and generates a corresponding memory page mapping table. Bad page replacement is avoided across storage blocks, mapping table complexity is reduced, and suitability of a nonvolatile memory module for deployment in a small-capacity random access memory is improved.

Further, if the number of reserved memory pages in the target memory block is less than a preset number threshold, the target memory block is marked as a non-rewritable memory block. The method has the advantages that when the bad memory pages appear in the target memory block, the spare reserved memory pages can be replaced preferentially, the target memory block is prevented from being unusable due to the fact that the individual bad memory pages are unusable, and the service life of the memory collision period is prolonged.

In this embodiment, after selecting the replacement reserved memory page to replace the bad memory page in the target memory block, if it is determined that the number of reserved memory pages in the target memory block is smaller than the preset number threshold (i.e., the bad memory pages in the target memory block reach a certain number), the memory controller marks the target memory block as a non-rewritable memory block, and uses the target memory block for storing cold data.

In the nonvolatile memory module of the embodiment, when the number of bad memory pages in the target memory block reaches a certain number, the target memory block is marked as a non-rewritable memory block and is used for storing cold data, so that the utilization rate of the memory block can be improved.

In the several embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other manners. The apparatus embodiments described above are merely illustrative, for example, of the flow diagrams and block diagrams in the figures, which illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods and computer program products according to various embodiments of the present application. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

In addition, functional modules or units in various embodiments of the application may be integrated together to form a single part, or the modules may exist alone, or two or more modules may be integrated to form a single part.

The functions, if implemented in the form of software functional modules and sold or used as a stand-alone product, may be stored in a computer-readable storage medium. Based on such understanding, the technical solution of the present application may be embodied essentially or in a part contributing to the prior art or in a part of the technical solution in the form of a software product stored in a storage medium, comprising several instructions for causing a computer device (which may be a smart phone, a personal computer, a server, a network device, etc.) to perform all or part of the steps of the method according to the embodiments of the present application.

The foregoing is merely illustrative of the present application, and the present application is not limited thereto, and any person skilled in the art will readily recognize that variations or substitutions are within the scope of the present application.

Claims (10)

1. A data storage method applied to a storage device configured with a nonvolatile memory module including a plurality of memory blocks, characterized in that an open memory page and a reserved memory page are configured in each of the memory blocks of the nonvolatile memory module, the method comprising:

When a data writing instruction to a target logical address is detected, determining a target open storage page corresponding to a mapping physical address in response to the existence of the mapping physical address in the target logical address;

selecting an idle target reserved storage page from a target storage block where the target open storage page is located;

Storing write data for the target logical address in the target reserved memory page, and

The effective page count value of the target memory block is kept unchanged.

2. The data storage method according to claim 1, wherein after the step of storing the write data for the target logical address in the target reserved memory page, comprising:

And modifying the physical address corresponding to the target logical address in the address mapping table into the physical address corresponding to the target reserved storage page.

3. The data storage method of claim 1, wherein the method further comprises:

Marking the target open storage page in a preset valid indication mapping table as invalid, and marking the target reserved storage page as valid;

and updating the use quantity of the reserved storage pages corresponding to the target storage block in a preset reserved storage page use count table.

4. The data storage method of claim 1, wherein the method further comprises:

and triggering garbage collection for the target storage block in response to the valid page count value being less than a preset threshold.

5. A data storage method according to claim 3, wherein the method further comprises:

When triggering garbage collection of the target storage block, determining whether a non-idle reserved storage page exists in the target storage block according to a count value in the reserved storage page usage count table, and

And determining the non-idle reserved storage page based on the effective indication mapping table, performing garbage collection on data in the non-idle reserved storage page, and performing garbage collection on data in the open storage page.

6. The data storage method of claim 1, wherein the method further comprises:

When a data rollback instruction aiming at a target storage page in the target storage block is detected, extracting a linked list of the target storage page from a preset storage page linked list, wherein a change chain of the storage page when data is rewritten is stored in the preset storage page linked list;

and searching target rollback data corresponding to the data rollback instruction according to the linked list of the target storage page.

7. The data storage method of claim 6, wherein the method further comprises:

When the target storage block triggers garbage collection, positioning effective cold data and effective hot data stored in the target storage block according to the chain table length of each storage page of the target storage block in the preset storage page chain table;

and storing the effective cold data and the effective hot data separately when garbage is recovered.

8. The data storage method of claim 1, wherein the method further comprises:

when detecting that a bad memory page exists in the target memory block, selecting a replacement reserved memory page to replace the bad memory page in the target memory block;

and recording the mapping relation between the bad memory page and the replacement reserved memory page in a preset memory page mapping table, or recording the mapping relation between the bad memory page and the replacement reserved memory page in a metadata area of the target memory block.

9. The data storage method of claim 8, wherein the method further comprises:

and if the number of the reserved memory pages in the target memory block is smaller than a preset number threshold, marking the target memory block as a non-rewritable memory block.

10. A memory device, comprising:

a connection interface for connecting to a host system;

nonvolatile memory module

A memory controller connected to the connection interface and the nonvolatile memory module;

the memory controller is configured to implement the data storage method of any one of claims 1-9.