CN120600079A - Memory peripheral circuits and memory - Google Patents
Memory peripheral circuits and memoryInfo
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- CN120600079A CN120600079A CN202510621063.7A CN202510621063A CN120600079A CN 120600079 A CN120600079 A CN 120600079A CN 202510621063 A CN202510621063 A CN 202510621063A CN 120600079 A CN120600079 A CN 120600079A
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Abstract
本发明公开一种存储器的外围电路和存储器，存储器包括多个存储单元。外围电路包括位线解码器，位线解码器包括多个选通单元。各选通单元包括与任一存储单元的位线耦接的第一端、用于输出选中的存储单元的读取信号的第二端、耦接于第一端和第二端之间且与存储器的本地位线耦接的第三端。在对选中的存储单元进行读取操作的过程中，保持第一端和第三端之间导通，并在第二端和第三端之间断开预设时间后，将第二端和第三端之间导通。本申请使得第二端与第三端进行电荷共享后的电压偏移量增大，有助于读取信号与参考信号之间形成明显的电压差异，增强比较器的判别裕度，提升存储器读取操作的准确性和稳定性。
The present invention discloses a peripheral circuit of a memory and a memory, wherein the memory includes a plurality of memory cells. The peripheral circuit includes a bit line decoder, and the bit line decoder includes a plurality of gating units. Each gating unit includes a first end coupled to the bit line of any memory cell, a second end for outputting a read signal of the selected memory cell, and a third end coupled between the first end and the second end and coupled to the local bit line of the memory. During a read operation on the selected memory cell, the first end and the third end are kept conductive, and after a preset time period has elapsed between the second end and the third end, the second end and the third end are conductive. The present application increases the voltage offset after the second end and the third end share charge, helps to form a significant voltage difference between the read signal and the reference signal, enhances the discrimination margin of the comparator, and improves the accuracy and stability of the memory read operation.
Description
Technical Field
The present invention relates to the field of memory technologies, and in particular, to a peripheral circuit of a memory and a memory.
Background
In a memory, data is generally read by charge sharing between a Bit Line (BL) and a Data Line (DL), so as to determine the state of the memory cell. Specifically, the currently prevailing default read mode generally includes the steps of first disconnecting the selected bit line from the data line, then turning on again through the control logic, and then enabling charge sharing between the bit line and the data line. The shared voltage value is input to a comparator, compared with a preset reference voltage, and the read result is output after comparison and amplification.
However, when the memory cell is read, the voltage difference after charge sharing may be insufficient due to the deviation of parasitic capacitance in the manufacturing process, so as to affect the discrimination effect of the comparison amplifier and reduce the reading accuracy and stability.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, the present application is directed to improving the accuracy and stability of memory read operations.
In order to solve at least one technical problem set forth above, the application discloses a peripheral circuit of a memory and the memory.
According to an aspect of the present application, there is provided a peripheral circuit of a memory including a memory array including a plurality of memory cells, the peripheral circuit of the memory including:
a bit line decoder comprising:
a plurality of gating units, each of the gating units comprising:
A first terminal coupled to a bit line of any one of the memory cells;
The second end is used for outputting a reading signal of the selected storage unit;
A third terminal coupled between the first and second terminals and coupled to a local bit line of the memory;
each of the gating units is configured to:
And in the process of reading the selected memory cell, keeping conduction between the first end and the third end, and conducting between the second end and the third end after a preset time is disconnected between the second end and the third end.
Optionally, each of the gating units includes:
A first bit line switch connected between the second terminal and the third terminal;
The first bit line switch is configured to turn on after a preset time is turned off during a read operation of a selected memory cell.
Optionally, each of the gating units includes:
a second bit line switch connected between the first terminal and the third terminal;
the second bit line switch is configured to be turned on continuously during a read operation of the selected memory cell.
Optionally, the first bit line switch further comprises a first control end, the first control end is used for receiving a first control signal to control the first bit line switch to be turned on or turned off, and the second bit line switch further comprises a second control end, the second control end is used for receiving a second control signal to control the second bit line switch to be turned on or turned off.
Optionally, the second bit line switch is a transistor, and a gate terminal of the transistor is the second control terminal;
The magnitude of the second control signal is positively or negatively correlated with the magnitude of the current between the first terminal and the third terminal during a read operation of the selected memory cell.
Optionally, the system further comprises a signal controller configured to:
In the process of reading the selected memory cell, a first control signal is provided for the first control end, a second control signal is provided for the second control end, the first control signal is used for controlling the first bit line switch to be turned on after being turned off for a preset time, and the second control signal is used for controlling the second bit line switch to be continuously turned on.
Optionally, each gating unit further comprises a first control switch, one end of the first control switch is connected with the first control end, the other end of the first control switch is used for receiving a first control signal, and the first control switch is configured to be turned on after being turned off for a preset time in the process of reading the selected memory unit.
Optionally, the system further comprises a signal controller configured to:
In the process of reading the selected memory cell, a first control signal is provided for the first control end, a second control signal is provided for the second control end, a first switch signal is provided for the first control switch, the first control signal is used for controlling the first bit line switch to be continuously conducted, the second control signal is used for controlling the second bit line switch to be continuously conducted, and the first switch signal is used for controlling the first control switch to be conducted after being turned off for a preset time.
Optionally, the device also comprises a comparator, a first output terminal, a second output terminal and a first output terminal;
The first input end is used for inputting a reference signal;
the second input end is coupled with the second end and is used for receiving the reading signal;
the output end is used for outputting a comparison result of the reference signal and the reading signal.
According to a second aspect of the present application there is provided a memory comprising:
a memory array including a plurality of memory cells;
a peripheral circuit as in any preceding claim, coupled to said memory cell.
The peripheral circuit of the memory disclosed by the embodiment of the application can improve the accuracy and stability of the memory reading operation.
Specifically, the application introduces a three-terminal structure into the gating unit, and adopts a time-sharing conduction control mode in the process of reading the selected memory unit. The first end and the third end are conducted, the third end and the second end are temporarily not conducted, so that the bit line of the memory cell is conducted with the local bit line, and then the second end and the third end are conducted, so that the second end outputs a reading signal. In the process of charge sharing between the second end and the third end, the parasitic capacitance of the local bit line is introduced into the bit line side of the memory cell besides the original parasitic capacitance, so that the equivalent parasitic capacitance of the bit line is effectively increased. Therefore, the voltage offset after the second end and the third end are subjected to charge sharing is increased, obvious voltage difference is formed between the read signal and the reference signal, the judgment margin of the comparator is enhanced, and the accuracy and the stability of the memory read operation are improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to the structures shown in these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a memory according to an embodiment of the present application;
FIG. 2 is a circuit diagram of a peripheral circuit of a memory according to an embodiment of the present application;
FIG. 3 is a second circuit diagram of a peripheral circuit of the memory according to the embodiment of the present application;
FIG. 4 is a schematic diagram of a read signal of a peripheral circuit of a memory according to an embodiment of the present application;
FIG. 5 is a schematic diagram of voltage waveforms of peripheral circuits of a memory according to an embodiment of the present application during data reading;
FIG. 6 is a process diagram of the change in bit line side current over time.
Reference numerals illustrate:
1. a memory array;
2. Peripheral circuits, bit line decoders, signal controllers, memory cells, and selected memory cells, wherein the bit line decoders are respectively connected with the peripheral circuits, the bit line decoders, the signal controllers, the memory cells and the selected memory cells;
21. The gate unit 211, the first end 212, the second end 213, the third end 22, the comparator 221, the first input end 222, the second input end 223 and the output end.
The achievement of the objects, functional features and advantages of the present invention will be further described with reference to the accompanying drawings, in conjunction with the embodiments.
Detailed Description
The technical solutions of the embodiments of the present specification will be clearly and completely described below with reference to the drawings in the embodiments of the present specification, and it is apparent that the described embodiments are some of the embodiments of the present specification, but not all the embodiments. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are intended to be within the scope of the present application based on the embodiments herein.
It should be noted that the terms "first," "second," and the like in the description and the claims of the present application and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the application described herein may be implemented in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or server that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
Various exemplary embodiments, features and aspects of the disclosure will be described in detail below with reference to the drawings. In the drawings, like reference numbers indicate identical or functionally similar elements. Although various aspects of the embodiments are illustrated in the accompanying drawings, the drawings are not necessarily drawn to scale unless specifically indicated.
The word "exemplary" is used herein to mean "serving as an example, embodiment, or illustration. Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments.
The term "and/or" is used herein to describe an association relationship of associated objects, and means that there may be three relationships, for example, a and/or B, and that there may be three cases where a exists alone, while a and B exist together, and B exists alone. In addition, the term "at least one" herein means any one of a plurality or any combination of at least two of a plurality, for example, including at least one of A, B, C, may mean including any one or more elements selected from the group consisting of A, B and C.
Furthermore, numerous specific details are set forth in the following detailed description in order to provide a better understanding of the present disclosure. It will be understood by those skilled in the art that the present disclosure may be practiced without some of these specific details. In some instances, methods, means, elements, and circuits well known to those skilled in the art have not been described in detail in order not to obscure the present disclosure.
As described in the background art, when the memory cell is read, the voltage difference after charge sharing may be insufficient due to the influence of the parasitic capacitance deviation in the manufacturing process, so as to affect the discrimination effect of the comparator and reduce the accuracy and stability of reading.
In one embodiment, a memory includes a memory array including a plurality of memory cells. The peripheral circuit of the memory provided in the first embodiment includes a bit line decoder and a comparator, the bit line decoder includes a plurality of strobe units, each strobe unit includes a first end and a second end, the first end is coupled to a bit line of any memory cell, and the second end is coupled to a data line for outputting a read signal of the selected memory cell. The comparator is provided with a first input end, a second input end and an output end, wherein the first input end is used for receiving a reference signal, the second input end is coupled with the second end of the gating unit and used for receiving a reading signal of a selected storage unit, and the output end is used for outputting a comparison result of the reference signal and the reading signal.
In the first embodiment, when the selected memory cell is subjected to a read operation, the connection between the first end of the gating unit and the second end of the gating unit is disconnected, and after the first end and the second end of the gating unit are kept in the disconnected state for a preset time, the first end and the second end of the gating unit are conducted, so that the second end outputs a read signal corresponding to the memory cell.
However, due to process errors and device parameter fluctuations during actual chip fabrication, the parasitic capacitances of the bit lines and the data lines may deviate from the design values, e.g., the parasitic capacitance of the bit lines may be less than expected, while the parasitic capacitance of the data lines may be greater than expected. In this case, when the connection between the first terminal and the second terminal is disconnected and turned back on, the bit line and the data line share charges after being turned back on, and finally the voltage on the data line may be closer to the voltage of the reference signal, that is, the voltage of the read signal output by the second terminal may be too close to the voltage of the reference signal. If the voltage difference between the two is lower than the minimum resolution threshold of the comparator, the comparison result is inaccurate, and thus the reading accuracy and stability of the memory are reduced.
Therefore, in order to improve the read accuracy and stability of the memory, the second embodiment provides a peripheral circuit of the memory.
Fig. 1 is a schematic diagram of a memory according to an embodiment of the present application, and as shown in fig. 1, the memory includes a memory array 1 and a peripheral circuit 2, and the peripheral circuit 2 is coupled to the memory array 1.
The memory array 1 corresponds to at least a portion of a phase change memory, and includes a plurality of word lines WL (word lines), a plurality of Bit lines BL (Bit lines), and a plurality of memory cells 5, the memory cells 5 being located at intersections of the word lines WL and the Bit lines BL, binary data being able to be written to the memory cells 5 or binary data being able to be read from the memory cells 5.
The memory cell 5 comprises a crystalline state and an amorphous state, and the switching between the crystalline state and the amorphous state can be achieved by applying different forms of heat to the memory cell 5 corresponding to different voltage thresholds. Crystalline states are defined as 1, corresponding to lower threshold voltages, amorphous states are defined as 0, and corresponding to higher threshold voltages. The programming operation to complete writing "1" to the memory cell 5 is defined as a set operation, and the programming operation to complete writing "0" to the memory cell 5 is defined as a reset operation. By applying a threshold voltage greater than the set state and less than the reset state to the selected memory cell 6, the memory cell 5 in the crystalline state can be turned on, but the memory cell 5 in the amorphous state cannot be turned on, and thus the reading of the state of the memory cell 5 can be completed.
Fig. 2 is a circuit diagram of a peripheral circuit of a memory according to an embodiment of the present application, and as shown in fig. 2, the peripheral circuit of a memory according to a second embodiment of the present application includes a bit line decoder 3. The bit line decoder 3 includes a plurality of gating cells 21, and each gating cell 21 includes a first terminal 211, a second terminal 212, and a third terminal 213. The first terminal 211 is coupled to the bit line BL of any memory cell 5, the second terminal 212 is used for outputting the read signal of the selected memory cell 6, and the third terminal 213 is coupled between the first terminal 211 and the second terminal 212 and is coupled to the local bit line LBL of the memory. That is, a side of the first terminal 211 facing away from the second terminal 212 is coupled to the bit line BL of any memory cell 5, a local bit line LBL is coupled between the first terminal 211 and the second terminal 212, a side of the second terminal 212 facing away from the first terminal 211 is coupled to the first data line DL0, and a third terminal 213 is located between the first terminal 211 and the second terminal 212 and is coupled to the local bit line LBL.
During a read operation of the selected memory cell 6, each of the gating cells 21 is configured to maintain conduction between the first terminal 211 and the third terminal 213 and to conduct conduction between the second terminal 212 and the third terminal 213 after a preset time of disconnection between the second terminal 212 and the third terminal 213.
The application introduces a three-terminal structure into the gating unit 21, and adopts a time-sharing conduction control mode in the process of reading the selected memory unit 6. First, the first terminal 211 and the third terminal 213 are turned on, the third terminal 213 and the second terminal 212 are turned off temporarily, so that the bit line BL of the selected memory cell 6 is turned on with the local bit line LBL, and then the second terminal 212 and the third terminal 213 are turned on, so that the second terminal 212 outputs a read signal. In the process of charge sharing between the second end 212 and the third end 213, the parasitic capacitance of the local bit line LBL is introduced in addition to the original parasitic capacitance on the bit line side of the selected memory cell 6, so that the equivalent parasitic capacitance on the bit line side is effectively increased. Therefore, the voltage offset after the charge sharing between the second end 212 and the third end 213 is increased, which is conducive to forming an obvious voltage difference between the read signal and the reference signal, enhancing the discrimination margin of the comparator 22, and improving the accuracy and stability of the memory read operation.
With continued reference to fig. 2, the bit line decoder 3 of the peripheral circuit of the memory disclosed in the second embodiment of the present application further includes a comparator 22. The comparator 22 has a first input 221, a second input 222 and an output 223. The first input terminal 221 is coupled to the second data line DL1 for inputting a reference signal. The second input terminal 222 is coupled to the second terminal 212 through the first data line DL0 for receiving a read signal. The comparator 22 compares the reference signal and the read signal, and outputs the comparison result of the reference signal and the read signal through the output terminal 223.
As shown in fig. 4, when the selected memory cell 6 is read, the bit line side voltage of the selected memory cell 6 is V BL-set if the selected memory cell 6 is in the set state (indicating "read 1"), and the bit line side voltage of the selected memory cell 6 is V BL-reset if the selected memory cell 6 is in the reset state (indicating "read 0"). Before a read operation is performed on the selected memory cell 6, the second terminal 212 is coupled to the data line DL0, and the voltage at the second terminal 212 is V DL0. In the first embodiment, after the selected memory cell 6 in the set state is read, the voltage of the read signal output by the second terminal 212 is V DL0-set, and after the selected memory cell 6 in the reset state is read, the voltage of the read signal output by the second terminal 212 is V DL0-reset. In the second embodiment, after the selected memory cell 6 in the set state is read, the voltage of the read signal output by the second terminal 212 is V DL0-set', and after the selected memory cell 6 in the reset state is read, the voltage of the read signal output by the second terminal 212 is V DL0-reset'. The "first margin" and "second margin" shown in fig. 4 represent the voltage difference between the voltage of the read signal and the voltage V DL1-ref of the reference signal in the first and second embodiments, respectively. By improving in the second embodiment, the second margin is larger than the first margin, so that the margin of reading discrimination of the memory is improved.
Further, referring to fig. 5, fig. 5 is a schematic diagram of voltage waveforms of a peripheral circuit of a memory provided in an embodiment of the present application during data reading, and the difference of voltage read margin after the selected memory cell 6 is read is shown in the first embodiment and the second embodiment. Specifically, curve E represents the voltage waveform of the second terminal 212, curve F represents the voltage waveform of the first terminal 211, curve G represents the voltage waveform of the first input terminal 221, the first section is the voltage state of each terminal after reading the selected memory cell 6, Δv represents the voltage difference between the second terminal 212 and the first input terminal 221, and the voltage of the first input terminal 221 represents the reference voltage.
Specifically, in fig. 5, the ordinate of each of the graph a, the graph b, the graph c, and the graph d represents the voltage, the abscissa represents the time, and the ordinate scales of the graph a, the graph b, the graph c, and the graph d agree with each other. Both a and b in fig. 5 are read operations on the selected memory cell 6 in the set state, the a is completed by the first embodiment and the b is completed by the second embodiment, and it is obvious that Δv2 of the second embodiment is greater than Δv1 of the first embodiment in the first section. Both the graph c and the graph d in fig. 5 are the read 0 operation performed on the selected memory cell 6 in the reset state, the graph c completes the read 0 operation through the first embodiment, the graph d completes the read operation through the second embodiment, and it can be obviously found that Δv4 of the second embodiment is greater than Δv3 of the first embodiment in the first section.
As can be seen from the comparison, the improvement of the structure and the control strategy in the embodiment effectively enlarges the voltage difference between the read signal and the reference signal when reading 1 and reading 0, i.e. increases the discrimination margin of the comparator, thereby improving the reading accuracy and the reading stability of the memory under the condition of parasitic capacitance deviation.
Referring to fig. 2, in the second embodiment, each of the gate units 21 further includes a first bit line switch SW1. The first bit line switch SW1 is connected between the second terminal 212 and the third terminal 213. In the embodiment, by controlling the on/off of the first bit line switch SW1, the accurate control of the read path is realized, so as to optimize the charge sharing process and improve the voltage difference of the read signal. Specifically, the first bit line switch SW1 is configured to be turned on after being turned off for a preset time during a read operation of the selected memory cell 6, so that only the bit line BL of the selected memory cell 6 is ensured to be turned on with the local bit line LBL before the charges of the second terminal 212 and the third terminal 213 are shared, so that the parasitic capacitance of the local bit line LBL is introduced at the bit line side, the equivalent parasitic capacitance at the bit line side is effectively increased, and the voltage offset and the comparison discrimination margin are improved.
In the second embodiment, the first bit line switch SW1 has a first control terminal for receiving a first control signal to control the first bit line switch SW1 to be turned on and off. The peripheral circuit 2 of the memory further comprises a signal controller 4 for providing a first control signal to the first control terminal during a read operation of the selected memory cell 6, the first control signal being used for controlling the first bit line switch SW1 to be turned on after a preset time of turn-off.
It is noted that the first bit line switch SW1 may include, but is not limited to, a PMOS transistor, an NMOS transistor, a bipolar transistor (BJT), or other semiconductor switching devices capable of performing on/off control functions. When the first bit line switch SW1 is a PMOS transistor or an NMOS transistor, gate terminals of the PMOS transistor and the NMOS transistor form a first control terminal of the first bit line switch SW1, and when the first bit line switch SW1 is a bipolar transistor (BJT), a base terminal of the bipolar transistor (BJT) is a first control terminal of the first bit line switch SW 1.
With continued reference to FIG. 2, in some other embodiments, each gating cell 21 further includes a second bit line switch SW2. The second bit line switch SW2 is connected between the first terminal 211 and the third terminal 213. In this embodiment, by controlling the on and off of the second bit line switch SW2, precise control over the read path is achieved, so that the charge sharing process is optimized, and the voltage difference of the read signal is improved. Specifically, the second bit line switch SW2 is configured to be turned on continuously during the reading operation of the selected memory cell 6. Thereby ensuring that the bit line BL of the selected memory cell 6 is conducted with the local bit line LBL before the second end 212 and the third end 213 are in charge sharing, so that the parasitic capacitance of the local bit line LBL is introduced at the bit line side, the equivalent parasitic capacitance at the bit line side is increased, and the voltage offset and the comparison discrimination margin are improved.
In this embodiment, the second bit line switch SW2 has a second control terminal for receiving a second control signal to control the second bit line switch SW2 to be turned on and off. The signal controller 4 also provides a second control signal to the second control terminal during the read operation of the selected memory cell 6, where the second control signal is used to control the second bit line switch SW2 to be continuously turned on.
It is noted that the second bit line switch SW2 may include, but is not limited to, a PMOS transistor, an NMOS transistor, a bipolar transistor (BJT), or other semiconductor switching device capable of performing on/off control function. When the second bit line switch is a PMOS transistor or an NMOS transistor, the gate terminals of the PMOS transistor and the NMOS transistor form a second control terminal of the second bit line switch SW2, and when the second bit line switch is a bipolar transistor (BJT), the base terminal of the bipolar transistor (BJT) is the second control terminal of the second bit line switch SW 2.
When the selected memory cell 6 is read, the voltage drop rate on the bit line side is reduced after the equivalent parasitic capacitance on the bit line side is increased, resulting in an extended time for the read process. If the voltage on the bit line side changes too slowly or with an unclear voltage, it may cause the unselected memory cells 5 to discharge as well, thereby affecting their state, resulting in erroneous read results. In order to avoid the above problem, in this embodiment, the second bit line switch SW2 is a transistor (may be a PMOS transistor or an NMOS transistor). When the second bit line switch SW2 is an NMOS transistor, the magnitude of the second control signal is positively correlated with the magnitude of the current between the first terminal 211 and the third terminal 213 during the read operation of the selected memory cell 6. Specifically, when the second control signal is large, the second bit line switch SW2 has a strong conduction capability, and the current between the first terminal 211 and the third terminal 213 is large, and when the second control signal is small, the second bit line switch SW2 has a weak conduction capability, and the current between the first terminal 211 and the third terminal 213 is small. When the second bit line switch SW2 is a PMOS transistor, the magnitude of the second control signal is inversely related to the magnitude of the current between the first terminal 211 and the third terminal 213 during the read operation of the selected memory cell 6.
By setting the second bit line switch SW2 as a transistor, a suitable second control signal can be selected based on the magnitude of the equivalent parasitic capacitance, and by controlling the magnitude of the second control signal, the on time of the second bit line switch SW2 is controlled, the read disturb is reduced, and the margin of the read discrimination of the memory is improved.
Taking the second bit line switch SW2 as an NMOS transistor as an example, referring to fig. 6, fig. 6 is a process diagram of the change of the bit line side current with time. The ordinate in fig. 6 represents the current value on the bit line side, and the abscissa represents time. Specifically, curve a represents the time-dependent course of the bit line side current in the first case, curve B represents the time-dependent course of the bit line side current in the second case, curve C represents the time-dependent course of the bit line side current in the third case, and curve D represents the time-dependent course of the bit line side current in the fourth case.
In the first case, the read mode is to keep the first bit line switch SW1 on and the second bit line switch SW2 on after the predetermined time is turned off when the selected read cell is read (the read mode does not change the equivalent parasitic capacitance on the bit line side). In the second case, the reading mode is the reading mode of the present embodiment, specifically, when the selected memory cell 6 is read, the second bit line switch SW2 is kept turned on, and the first bit line switch SW1 is turned on after being turned off for a preset time. In the third case, the reading mode is the same as that in the second case. Fourth, the reading mode is the same as that of the second case. The voltage value of the second control signal in the second case is smaller than the voltage value of the second control signal in the third case, the voltage value of the second control signal in the third case is smaller than the voltage value of the second control signal in the fourth case, and the voltage value of the second control signal in the fourth case is equal to the voltage value of the second control signal in the first case.
As can be clearly understood from the curves a and D of fig. 6, in the case where the voltage values of the second control signals are equal, in the reading mode disclosed in this embodiment (when the selected reading unit is read, the second bit line switch SW2 is kept on, and the first bit line switch SW1 is turned on after the preset time is turned off) the on time of the second bit line switch SW2 is longer than that in the other reading mode (when the selected reading unit is read, the first bit line switch SW1 is kept on, and the second bit line switch SW2 is turned on after the preset time is turned off).
As can be clearly seen from the curve B, the curve C and the curve D of fig. 6, when the reading mode disclosed in the embodiment is adopted to perform the reading operation on the selected reading unit, the on time of the second bit line switch SW2 can be controlled by changing the magnitude of the second control signal, so as to reduce the read interference, and further improve the accuracy and stability of the reading operation of the memory.
Fig. 3 is a circuit diagram of a peripheral circuit of a memory according to an embodiment of the present application, and as shown in fig. 3, a peripheral circuit of a memory is also disclosed in a third embodiment of the present application. Unlike the above embodiment, the decoder 3 further includes a first control switch SW3. One end of the first control switch SW3 is connected to the first control end, and the other end is used for receiving the first control signal. The signal controller 4 is configured to provide a first control signal to the first control terminal, a second control signal to the second control terminal, and a first switching signal to the first control switch SW3 during a read operation of the selected memory cell 6. The first control signal is used for controlling the first bit line switch SW1 to be continuously turned on, the second control signal is used for controlling the second bit line switch SW2 to be continuously turned on, and the first switch signal is used for controlling the first control switch SW3 to be turned off for a preset time and then turned on. The first control switch SW3 is configured to be turned on after being turned off for a preset time during a read operation of the selected memory cell 6. The embodiment controls the first bit line switch SW1 to be turned on after being turned off for a preset time by controlling the first control switch SW3 to be turned on and off.
The embodiment of the application also discloses a memory, which comprises:
a memory array including a plurality of memory cells;
the peripheral circuit of any of the preceding claims, coupled to the memory cell.
The embodiment of the application also discloses an operation method of the memory, which comprises the following steps:
performing a read operation on the selected memory cell, comprising:
Keeping the first end and the third end on, and turning off the second end and the third end;
After the second end and the third end are disconnected for a preset time, the second end and the third end are conducted so that the second end outputs a reading signal.
The foregoing description of the embodiments of the present invention is merely an optional embodiment of the present invention, and is not intended to limit the scope of the invention, and all equivalent structural modifications made by the present invention in the light of the present invention, the description of which and the accompanying drawings, or direct/indirect application in other related technical fields are included in the scope of the invention.
Claims (10)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202510621063.7A CN120600079A (en) | 2025-05-14 | 2025-05-14 | Memory peripheral circuits and memory |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202510621063.7A CN120600079A (en) | 2025-05-14 | 2025-05-14 | Memory peripheral circuits and memory |
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| CN114913889A (en) * | 2021-04-15 | 2022-08-16 | 台湾积体电路制造股份有限公司 | Control circuit, read switch drive circuit and control method |
| CN115775571A (en) * | 2021-09-08 | 2023-03-10 | 合肥格易集成电路有限公司 | Memory and operation method of memory |
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| US20140104952A1 (en) * | 2011-05-18 | 2014-04-17 | The University Of Tokyo | Integrated circuit device |
| CN109658966A (en) * | 2017-10-11 | 2019-04-19 | 意法半导体股份有限公司 | The reading circuit and method of nonvolatile semiconductor memory member |
| CN110223725A (en) * | 2019-05-22 | 2019-09-10 | 北京航空航天大学 | A kind of non-volatile RAM data reading circuit, memory and method |
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| CN114913889A (en) * | 2021-04-15 | 2022-08-16 | 台湾积体电路制造股份有限公司 | Control circuit, read switch drive circuit and control method |
| CN115775571A (en) * | 2021-09-08 | 2023-03-10 | 合肥格易集成电路有限公司 | Memory and operation method of memory |
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