CN120600078A - Flash memory erase and write protection method, device, equipment and program product - Google Patents

Abstract

The present application relates to the field of memory, and in particular to a flash memory erase and write protection method, apparatus, device and program product. The method comprises: a write controller writes data into a cache module; in response to a power outage of an electronic device, the cache module detects whether the data cached by the cache module is a complete data block; in response to the cache module detecting that the cached data is a complete data block, the complete data is written into the flash memory and the flash memory and the cache module enter a power-off mode; in response to detecting that the cached data is not a complete data block, the cached data is prohibited from being written into the flash memory and the flash memory and the cache module enter a power-off mode. Since this method supports the cache module to judge the integrity of the data through the backup power supply when the electronic device is powered off, and writes the complete data block into the flash memory, it is beneficial to protect the integrity of the firmware data, and supports data writing and power-off through the backup power supply when the power is off, which is beneficial to protect the flash memory and increase the service life of the flash memory.

Description

Flash memory erasing protection method, device, equipment and program product

Technical Field

The present application relates to the field of memories, and in particular, to a flash memory erasure protection method, apparatus, device, and program product.

Background

Firmware is a very important component in embedded equipment, and if the firmware is damaged lightly, the equipment is abnormal in operation, and if the firmware is heavy, the equipment is completely unusable. Therefore, protection of firmware in each embedded device is very important. Under normal use, firmware is generally not easy to damage, but if an abnormality occurs in the process of Flash (Flash) erasing, such as power failure of the device, the firmware may be damaged.

In order to protect firmware damage occurring in the erasing process, a backup area is usually reserved for backing up the firmware, and when the main firmware is abnormal, the backup firmware of the backup area is copied to the main firmware area so as to repair the firmware of the main firmware area. Or the buffer area can be arranged in the flash memory, the buffer area is written first when the data is written, then the firmware area is written, if the power is cut off in the writing process, the data of the buffer area can be checked after the power is on again, and if the data of the buffer area is complete, the data of the buffer area is written into the firmware area.

Although the method can avoid firmware damage caused by writing data when power is off, if the data is erased when the power is off, the data damage can be caused, and the working voltage of a semiconductor device in the flash memory can not be protected, so that the working is disordered, irreversible damage can be generated in the erasing operation, and the service life of the flash memory is influenced.

Disclosure of Invention

In view of the above, embodiments of the present application provide a flash memory erasure protection method, apparatus, device and program product, so as to solve the problems in the prior art that when the flash memory is powered off during writing data, the data is easy to be damaged, and irreversible damage is generated to the flash memory, which affects the service life of the flash memory.

A first aspect of an embodiment of the present application provides a flash memory erasure protection method, where an electronic device where a flash memory is located includes a write controller, a cache module and a standby power supply, where the cache module is connected to the flash memory, the cache module is connected to the write controller, and the standby power supply is used to provide electric energy for the cache module and the flash memory when the electronic device is powered off, the method includes:

the write controller writes data into the cache module;

Responding to the power failure of the electronic equipment, and detecting whether the data cached by the caching module is a complete data block or not by the caching module;

And in response to the fact that the cache module detects that the cached data is a complete data block and the electronic equipment is powered off, enabling the flash memory and the cache module to enter a power-down mode after the complete data is written into the flash memory, and in response to the fact that the cached data is not the complete data block, disabling writing of the cached data into the flash memory and enabling the flash memory and the cache module to enter the power-down mode.

With reference to the first aspect, in a first possible implementation manner of the first aspect, the detecting, by the buffer module, whether data buffered by the buffer module is a complete data block includes:

the cache module detects a data state identifier included in the cached data;

under the condition that the data state identifier comprises a start identifier and an end identifier, determining that the cached data is a complete data block;

And in the case that the data state identifier does not comprise the end identifier, determining that the cached data is not a complete data block.

With reference to the first aspect, in a second possible implementation manner of the first aspect, before the writing controller writes data to the cache module, the method further includes:

determining the size of a data block according to the size of the flash memory block and the size of each parameter to be written into the flash memory;

and setting the data state identifier according to the size of the data block.

With reference to the second possible implementation manner of the first aspect, in a third possible implementation manner of the first aspect, determining, according to a size of the flash memory block, a size of the data block in combination with a size of each parameter to be written into the flash memory includes:

Determining the parameter sequence of each parameter to be written into the flash memory;

and distributing the parameters to the data blocks according to the parameter sequence, comparing the data blocks distributed with the parameters with the flash memory blocks, and determining the size of the data blocks according to the comparison result.

With reference to the third possible implementation manner of the first aspect, in a fourth possible implementation manner of the first aspect, determining a size of the data block according to a comparison result includes:

And in response to the comparison result that the data block allocated with the parameter is smaller than the flash memory block, allocating the next parameter to the data block and comparing the data block with the flash memory block until the comparison result that the data block allocated with the parameter is larger than or equal to the flash memory block, determining the size of the data block according to the state before the next parameter is allocated, and reallocating the next parameter to the next data block.

With reference to the first aspect, in a fifth possible implementation manner of the first aspect, after the writing controller writes data to the cache module, the method further includes:

Responding to the state of normal power supply of the electronic equipment, and detecting whether the data sent by the write controller is a complete data block or not by the cache module;

And writing the complete data block into the flash memory in response to the data being the complete data block.

With reference to any one of the first aspect to the fifth possible implementation manner of the first aspect, in a sixth possible implementation manner of the first aspect, the minimum power provided by the standby power supply is greater than the power consumed by the cache module to write the data of the flash memory block size into the flash memory.

A second aspect of an embodiment of the present application provides a flash memory erasure protection device, where an electronic device where a flash memory is located includes a write controller, a cache module and a standby power supply, where the cache module is connected to the flash memory, the cache module is connected to the write controller, and the standby power supply is used to provide electric energy for the cache module and the flash memory when the electronic device is powered off, where the device includes:

a data writing unit for writing data into the cache module by the write controller;

The data block detection unit is used for responding to the power failure of the electronic equipment, and the cache module is used for detecting whether the data cached by the cache module is a complete data block or not;

And the detection result response unit is used for enabling the flash memory and the cache module to enter a power-down mode after the cache module detects that the cached data is a complete data block and the electronic equipment is powered off and writes the complete data into the flash memory, and disabling the cached data from being written into the flash memory and enabling the flash memory and the cache module to enter the power-down mode after the cache module detects that the cached data is not the complete data block.

A third aspect of an embodiment of the present application provides an electronic device comprising a memory, a processor and a computer program stored in the memory and executable on the processor, when executing the computer program, causing the electronic device to implement a method as described in any one of the first aspects.

In a fourth aspect of embodiments of the present application, there is provided a computer program product which, when run on a computer, causes the computer to perform the method of the first aspect or implementations thereof.

A fifth aspect of the embodiments of the present application provides a computer readable storage medium storing a computer program which, when executed by a processor, implements the steps of the method according to any of the first aspects.

Compared with the prior art, the embodiment of the application has the beneficial effects that the buffer memory module and the standby power supply are arranged in the electronic equipment where the flash memory is located, when the electronic equipment is powered off, the standby power supply supplies power to the buffer memory module and the flash memory, so that the buffer memory module can detect the integrity of buffered data, if the data is a complete data block, the complete data block is written into the flash memory by utilizing the electric energy provided by the standby power supply, then the flash memory and the buffer memory module are enabled to enter a power-down mode, and if the data is not the complete data block, the data is not required to be written into the flash memory and the buffer memory module are enabled to enter the power-down mode. According to the method, when the electronic equipment is powered off, the data integrity judgment is carried out by the standby power supply supporting buffer module, the complete data block is written into the flash memory, so that the firmware data integrity is protected, and when the electronic equipment is powered off, the data writing and power-down are carried out by the standby power supply supporting buffer module, the flash memory is protected, and the service life of the flash memory is prolonged.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments or the description of the prior art will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a schematic diagram of an implementation scenario of flash erase protection according to an embodiment of the present application;

FIG. 2 is a schematic diagram of an implementation flow of a flash memory erasure protection method according to an embodiment of the present application;

FIG. 3 is a schematic diagram of determining a data block size according to an embodiment of the present application;

FIG. 4 is a schematic diagram of a flash memory erasure protection device according to an embodiment of the present application;

fig. 5 is a schematic diagram of an electronic device according to an embodiment of the present application.

Detailed Description

In the following description, for purposes of explanation and not limitation, specific details are set forth such as the particular system architecture, techniques, etc., in order to provide a thorough understanding of the embodiments of the present application. It will be apparent, however, to one skilled in the art that the present application may be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present application with unnecessary detail.

In order to illustrate the technical scheme of the application, the following description is made by specific examples.

The firmware is used as a core component of the embedded system, and the stability of the firmware is directly related to the normal operation of the device. If the firmware fails, the firmware may cause abnormal functions of the equipment under slight conditions, and the firmware may cause complete failure of the equipment under serious conditions. Therefore, it is important to implement an effective firmware protection mechanism in various types of embedded devices.

Under normal operating conditions, firmware generally has a high reliability. However, when performing a Flash (Flash) programming operation, if an abnormal situation such as a sudden power failure is encountered, there is a risk of firmware damage. To protect against such risks, the following protection schemes are commonly employed by the industry:

And the backup recovery mechanism is used for dividing a special backup area in the storage medium, and when the main firmware area is damaged, the system can automatically recover the complete firmware from the backup area.

And the buffer checking mechanism is used for establishing a data writing buffer area, temporarily storing new data in the buffer area, and writing the new data into the firmware area after the integrity check is confirmed to be correct. If the power is cut off in the midway, the cache data can be checked again after the power is on, and the writing safety is ensured.

It should be noted that, although the above scheme can prevent the risk of power failure in the data writing process, when the power failure occurs just in the flash memory erasing operation, not only data damage is caused, but also irreversible hardware damage may be caused due to abnormal working voltage of the semiconductor device, thereby affecting the service life of the flash memory device.

In order to solve the above-mentioned problems, an embodiment of the present application provides a flash memory erasing protection method, and fig. 1 is a schematic diagram of an electronic device in a implementation scenario of the method, where the electronic device includes a write controller 1, a cache module 2, a standby power supply 3 and a flash memory 4.

The write controller 1 may be a Central Processing Unit (CPU) of an electronic device, and the buffer module 2 may include a buffer unit 21 and a microcontroller 22, where the microcontroller 22 is configured to write data sent by the write controller into the buffer unit 21, perform integrity detection on the data written into the buffer unit 21, and send data meeting requirements to the flash memory 4. The power consumption of the microcontroller 22 is typically much smaller than the power consumption of the write controller 1.

The standby power supply 3 may be used to provide power for the buffer module 2 and the flash memory 4 through the standby power supply when the electronic device is powered off, so that the buffer module 2 can determine whether the buffered data is complete data block, if so, the buffered complete data block is written into the flash memory 4, then the flash memory 4 and the buffer module 2 are powered down, and if not, the flash memory 4 and the buffer module 2 are directly powered down. The write controller 1 is configured to write data into the buffer module 2, and during writing, add a status identifier according to a start position and an end position of a complete data block. For example, a start identifier is added at the start position of the complete data block, and an end identifier is added at the end position of the complete data block. The buffer module 2 is configured to receive data written by the write controller 1, and determine whether the written data is a complete data block, and if the written data is a complete data block, start writing the complete data block in the buffer module 2 into the flash memory 4. The standby power supply 3 may be used to provide the flash memory 4 and the buffer module 2 with the power required by the power-off protection operation, i.e. the buffer module 2 determines whether the buffered data is a complete data block, if so, the complete data block is written into the flash memory 4 and the buffer module 2 are powered down, otherwise, the flash memory 4 is not written into and the flash memory 4 and the buffer module 2 are powered down.

Fig. 2 is a schematic implementation flow chart of a flash memory erasing and writing protection method according to an embodiment of the present application, which is described in detail below:

In S201, the write controller writes data to the cache module.

The write controller in the embodiment of the application can be a chip or a module for reading and writing data, and can be a chip or a module in electronic equipment, or can be a chip or a module connected with the electronic equipment and used for performing read-write operation on a flash memory in the electronic equipment, such as a chip or a module in other equipment for performing firmware upgrade on the electronic equipment.

The cache module comprises a high-speed memory chip which can be used for receiving and storing data written by the write controller, including parameters for upgrading firmware and the like. When the write controller needs to write the firmware data into the flash memory, the firmware data is written into the buffer module, so that frequent direct read-write operation on the flash memory can be avoided, and the data writing efficiency and reliability are improved.

In the embodiment of the application, during normal read-write operation, the write controller writes data into the cache unit according to the data block, and writes the start identifier when the data block starts writing, and writes the end identifier when the data block ends writing. A complete data block may be determined based on the start identifier and the end identifier.

According to the embodiment of the application, more than two complete data blocks can be written in the cache unit according to the space size of the cache unit in the cache module and the size of the maximum complete data block. Each complete data block is marked with a different status identification. The data blocks may be marked by a combination of data block identification and status identification. For example, data block 1 may be marked by a "1+ start identification" and a "1+ end identification". When the buffer memory unit can write more than two complete data blocks, the first data block which is completely written can be written into the flash memory when the first data block is detected to be completely written, and meanwhile, the second data block which is not completely written can be synchronously written into the buffer memory unit.

The size of the data block in the embodiment of the application can be determined according to the size of the flash memory block and the size of the parameters written into the flash memory.

Flash Block (Block) sizes vary from tens of KB to several megabytes in size, depending on the technology type and manufacturing process. The size of the largest data block may be determined based on the size of the flash memory block. For example, the size of the flash block is 64KB, and the flash block is used to store data to be written into the flash memory, and the start flag and the end flag, so that the data block written into the flash memory cannot be larger than the size of the flash block, for example, cannot be larger than 64KB. The data written to the flash memory includes data written to firmware in the flash memory, such as firmware parameters.

In a possible implementation, the write controller may sequentially allocate parameters to the data blocks according to the parameter order of the parameters written to the flash memory as desired. After each parameter is allocated once, the data block allocated with the parameter is compared with the flash memory block, after the allocation is determined, the data block allocated with the parameter is compared with the flash memory block, and the size of the data block is determined according to the comparison result. If the comparison result is that the data block is still smaller than the size of the flash memory block, the next parameter can be allocated to the data block, and the size of the data block with the newly allocated parameter is continuously compared with the size of the flash memory block until the data block with the newly allocated parameter is larger than or equal to the flash memory block, the state identifier indicating that the flash memory block can not store the data block and the data block is displayed, the size of the data block before the new parameter is allocated is determined as the final size of the data block, and the newly allocated parameter is rewritten into the next data block.

As shown in fig. 3, the size of the flash block is L, data to be written into the flash is divided according to parameters, obtaining n parameters of X1, X2 and X3., xi., xn, the corresponding data sizes are L1 respectively L2, L3.. Li...ln. According to the above method, the write controller writes the data X1 into the data block, at this time, the size of the data block is L1, compares the data block with the size of the flash memory block, writes the next parameter, i.e., X2, into the data block if L1 is smaller than L, at this time, the size of the data block is L2, compares the data block with the size of the flash memory block, writes X3 into the data block if l1+l2 is still smaller than L, and further compares the sizes of the data block and the flash memory block. If after writing the parameter Xi, if the size of the data block is larger than the size of the flash memory block for the first time, l1+l2+l3.+ Li > L, the size of the data block is determined according to the state before Xi allocation, and the parameter Xi is allocated to the next data block. I.e., the size of the data block is determined to be l1+l2+l3+ & gt L (i-1).

After the size of each data block is determined according to the size of the parameter and the size of the flash memory block, the write controller can send a start identifier to the buffer module before the data block starts to be sent according to the size of the data block, and send an end identifier after the data of one data block is sent. The buffer module may determine whether the received data is a complete data block according to the received start identifier and the end identifier.

When the electronic equipment is in normal power supply, the buffer module detects the end mark, which indicates that the complete data block is received, the complete data block corresponding to the end mark can be written into the flash memory. After the writing of the complete data block into the flash memory is completed, the data block stored in the cache unit can be erased so that the write controller can write a new data block.

In S202, in response to the electronic device being powered off, the buffer module detects whether the data buffered by the buffer module is a complete data block.

After the write controller writes data into the cache module, if the electronic equipment is powered off, the write controller is powered off to stop working, and at the moment, the backup power supply supplies power for the flash memory and the cache module. The backup power source can be a farad capacitor or a lithium battery. The Faraday capacitor is charged when the electronic equipment works normally, and stores electric quantity. When the electronic equipment is powered down, the power is supplied to the cache module and the flash memory through the stored electric quantity. The lithium battery can be charged when the electronic equipment is powered on, and the power is supplied to the cache module and the flash memory when the electronic equipment is powered off.

The minimum power of the backup power supply should be larger than the power consumed by the buffer module to write the data with the size of the flash memory block into the flash memory. The minimum power is the minimum power that must be provided by the power supply when discharging to the end voltage at a predetermined rate of time under standard circumstances, and is typically not less than 97% of the rated capacity. The size of the complete data block is determined according to the size of the parameters written into the flash memory and the size of the flash memory block, and the complete data block is smaller than the size of the flash memory block, so that when the electric quantity of the backup power supply is larger than the electric quantity consumed by the cache module for writing the data with the size of the flash memory block into the flash memory, the backup power supply can effectively ensure that the cache module can successfully write the data which is required to be written into the flash memory at present.

And for the written data in the cache module, the integrity check is required to be carried out on the written data in the cache module, and whether the written data is a complete data block or not is judged.

When detecting whether the written data is a complete data block, the buffer module can detect whether the start identifier and the end identifier are received, and then determine that the data is the complete data block.

In the embodiment of the application, after the complete data block is completely written into the flash memory by the cache module, the complete data block and the state identifier in the cache module are deleted. Thus, if the buffer module newly detects the end identifier, it may be determined that a new complete data block exists in the buffer module.

In S203, in response to the cache module detecting that the cached data is a complete data block and the electronic device is powered off, after the complete data is written into the flash memory, the flash memory and the cache module enter a power-down mode, in response to detecting that the cached data is not a complete data block, the cache module is prohibited from writing the cached data into the flash memory, and the flash memory and the cache module enter the power-down mode.

When the buffer module detects the end identifier, it is determined that the buffer module receives the complete data block, and in this case, the electronic device is not powered off, and the buffer module also sends the data in the received complete data block to the flash memory. Therefore, when the electronic device is powered off, if the data buffered in the buffer module is detected to be a complete data block, the sending state of the data in the complete data block may be that a part of the data is sent to the flash memory when the electronic device is not powered off, and a part of the data is not sent to the flash memory. Or the data in the complete data block, possibly all the data is not sent to the flash memory.

When the buffer module detects that the electronic device is powered off, the sending state of the complete data block can be determined. If all the data in the complete data block are not sent to the flash memory, the data in the complete data block are sequentially sent to the flash memory from the starting position of the complete data block, and after the sending is completed, the flash memory and the buffer memory module are made to enter a power-down mode so as to avoid abnormal power down caused by the fact that the power consumption of the standby power supply is completed.

When the cache module detects that the electronic device is powered off, if a part of data in the complete data block is sent to the flash memory and the part of data in the complete data block is not sent to the flash memory, the data which is not sent to the flash memory can be determined to be sent to the flash memory continuously until all data in the complete data block are sent to the flash memory, and then the flash memory and the cache module enter a power-down mode.

If the cache module detects that the data received in the cache module is not a complete data block when the electronic equipment is powered off, in order to avoid damage to the data caused by writing the data which is not the complete data block into the flash memory, for example, the firmware cannot work normally because part of parameters cannot be written completely.

In a possible implementation manner, the cache unit in the cache module in the embodiment of the present application may be a dynamic memory (DDR) or a register. Because the DDR or the register of the dynamic memory stores data through the charge and discharge of the capacitor, the read-write process is an electronic motion process, no physical loss mechanism exists, the service life problem does not exist, and the operation can not exist even if the power is off, so the data is cached through the DDR or the register, the safe isolation protection is added for the flash memory, and the service life of the flash memory can be effectively prolonged.

It should be understood that the sequence number of each step in the foregoing embodiment does not mean that the execution sequence of each process should be determined by the function and the internal logic, and should not limit the implementation process of the embodiment of the present application.

Fig. 4 is a schematic diagram of a flash memory erasure protection device according to an embodiment of the present application, where an electronic device where a flash memory is located includes a write controller, a cache module and a standby power supply, where the cache module is connected to the flash memory, the cache module is connected to the write controller, and the standby power supply is configured to provide power for the cache module and the flash memory when the electronic device is powered off, where the device includes:

A data writing unit 401, configured to write data into the cache module by the write controller;

a data block detection unit 402, configured to detect, by the cache module, whether data cached by the cache module is a complete data block in response to power-off of the electronic device;

And the detection result response unit 403 is configured to, in response to the detection that the cache module is a complete data block and the electronic device is powered off, enable the flash memory and the cache module to enter a power-down mode after the complete data is written into the flash memory, and in response to the detection that the cached data is not the complete data block, disable writing the cached data into the flash memory and enable the flash memory and the cache module to enter the power-down mode.

The flash erasing protection device corresponds to the flash erasing protection method shown in fig. 2.

Fig. 5 is a schematic diagram of an electronic device according to an embodiment of the present application. As shown in fig. 5, the electronic device 5 of this embodiment comprises a processor 50, a memory 51 and a computer program 52, such as a flash erase-write protection program, stored in said memory 51 and executable on said processor 50. The steps of the respective flash erase and write protection method embodiments described above are implemented by the processor 50 when executing the computer program 52. Or the processor 50, when executing the computer program 52, performs the functions of the modules/units of the apparatus embodiments described above.

By way of example, the computer program 52 may be partitioned into one or more modules/units that are stored in the memory 51 and executed by the processor 50 to complete the present application. The one or more modules/units may be a series of computer program instruction segments capable of performing the specified functions, which instruction segments are used to describe the execution of the computer program 52 in the electronic device 5.

The electronic device 5 may be a computing device such as a desktop computer, a notebook computer, a palm computer, a cloud server, etc. The electronic device may include, but is not limited to, a processor 50, a memory 51. It will be appreciated by those skilled in the art that fig. 5 is merely an example of one type of electronic device 5 and is not meant to be limiting as electronic device 5, and may include more or fewer components than shown, or may combine certain components, or different components, e.g., the electronic device may also include input and output devices, network access devices, buses, etc.

The Processor 50 may include a central processing unit (Central Processing Unit, CPU), but may also be other general purpose processors, digital signal processors (DIGITAL SIGNAL Processor, DSP), application SPECIFIC INTEGRATED Circuit (ASIC), field-Programmable gate array (Field-Programmable GATE ARRAY, FPGA) or other Programmable logic device, discrete gate or transistor logic device, discrete hardware components, or the like. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like. The processor 50 may also include a microprocessor for determining whether the data in the buffer module is a complete data block and writing the data in the complete data block into the flash memory.

The memory 51 may be an internal storage unit of the electronic device 5, such as a hard disk or a memory of the electronic device 5. The memory 51 may also be an external storage device of the electronic device 5, such as a plug-in hard disk, a smart memory Card (SMART MEDIA CARD, SMC), a Secure Digital (SD) Card, a flash memory Card (flash Card) or the like, which are provided on the electronic device 5. Further, the memory 51 may also include both an internal storage unit and an external storage device of the electronic device 5. The memory 51 is used for storing the computer program and other programs and data required by the electronic device. The memory 51 may also be used to temporarily store data that has been output or is to be output.

It will be apparent to those skilled in the art that, for convenience and brevity of description, only the above-described division of the functional units and modules is illustrated, and in practical application, the above-described functional distribution may be performed by different functional units and modules according to needs, i.e. the internal structure of the apparatus is divided into different functional units or modules to perform all or part of the above-described functions. The functional units and modules in the embodiment may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit, where the integrated units may be implemented in a form of hardware or a form of a software functional unit. In addition, the specific names of the functional units and modules are only for distinguishing from each other, and are not used for limiting the protection scope of the present application. The specific working process of the units and modules in the above system may refer to the corresponding process in the foregoing method embodiment, which is not described herein again.

In the foregoing embodiments, the descriptions of the embodiments are emphasized, and in part, not described or illustrated in any particular embodiment, reference is made to the related descriptions of other embodiments.

Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.

In the embodiments provided in the present application, it should be understood that the disclosed apparatus/terminal device and method may be implemented in other manners. For example, the apparatus/terminal device embodiments described above are merely illustrative, e.g., the division of the modules or units is merely a logical function division, and there may be additional divisions in actual implementation, e.g., multiple units or components may be combined or integrated into another system, or some features may be omitted or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection via interfaces, devices or units, which may be in electrical, mechanical or other forms.

The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

In addition, each functional unit in the embodiments of the present application may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit. The integrated units may be implemented in hardware or in software functional units.

The integrated modules/units, if implemented in the form of software functional units and sold or used as stand-alone products, may be stored in a computer readable storage medium. Based on this understanding, the present application may also be implemented by implementing all or part of the procedures in the methods of the above embodiments, and the computer program may be stored in a computer readable storage medium, where the computer program when executed by a processor may implement the steps of the respective method embodiments. Wherein the computer program comprises computer program code which may be in source code form, object code form, executable file or some intermediate form etc. The computer readable medium may include any entity or device capable of carrying the computer program code, a recording medium, a U disk, a removable hard disk, a magnetic disk, an optical disk, a computer Memory, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), an electrical carrier signal, a telecommunications signal, a software distribution medium, and so forth.

In addition, the embodiment of the application also provides a computer program product, which when running on a computer, causes the computer to execute the method in each implementation manner.

The foregoing embodiments are merely illustrative of the technical solutions of the present application, and not restrictive, and although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those skilled in the art that modifications may still be made to the technical solutions described in the foregoing embodiments or equivalent substitutions of some technical features thereof, and that such modifications or substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims (10)

1. The flash memory erasing and writing protection method is characterized in that an electronic device where a flash memory is located comprises a writing controller, a cache module and a standby power supply, wherein the cache module is connected with the flash memory, the cache module is connected with the writing controller, and the standby power supply is used for providing electric energy for the cache module and the flash memory when the electronic device is powered off, and the method comprises the following steps:

the write controller writes data into the cache module;

Responding to the power failure of the electronic equipment, and detecting whether the data cached by the caching module is a complete data block or not by the caching module;

And in response to the fact that the cache module detects that the cached data is a complete data block and the electronic equipment is powered off, enabling the flash memory and the cache module to enter a power-down mode after the complete data is written into the flash memory, and in response to the fact that the cached data is not the complete data block, disabling writing of the cached data into the flash memory and enabling the flash memory and the cache module to enter the power-down mode.

2. The method of claim 1, wherein the cache module detecting whether the data cached by the cache module is a complete data block comprises:

the cache module detects a data state identifier included in the cached data;

under the condition that the data state identifier comprises a start identifier and an end identifier, determining that the cached data is a complete data block;

And in the case that the data state identifier does not comprise the end identifier, determining that the cached data is not a complete data block.

3. The method of claim 1, wherein prior to the write controller writing data to the cache module, the method further comprises:

determining the size of a data block according to the size of the flash memory block and the size of each parameter to be written into the flash memory;

and setting the data state identifier according to the size of the data block.

4. The method of claim 3, wherein determining the size of the data block based on the size of the flash block in combination with the size of the respective parameter to be written to flash comprises:

Determining the parameter sequence of each parameter to be written into the flash memory;

and distributing the parameters to the data blocks according to the parameter sequence, comparing the data blocks distributed with the parameters with the flash memory blocks, and determining the size of the data blocks according to the comparison result.

5. The method of claim 4, wherein determining the size of the data block based on the comparison result comprises:

And in response to the comparison result that the data block allocated with the parameter is smaller than the flash memory block, allocating the next parameter to the data block and comparing the data block with the flash memory block until the comparison result that the data block allocated with the parameter is larger than or equal to the flash memory block, determining the size of the data block according to the state before the next parameter is allocated, and reallocating the next parameter to the next data block.

6. The method of claim 1, wherein after the write controller writes data to the cache module, the method further comprises:

Responding to the state of normal power supply of the electronic equipment, and detecting whether the data sent by the write controller is a complete data block or not by the cache module;

And writing the complete data block into the flash memory in response to the data being the complete data block.

7. The method of any of claims 1-6, wherein the minimum amount of power provided by the backup power source is greater than an amount of power consumed by the cache module to write flash block size data to the flash memory.

8. The utility model provides a flash memory erasure protection device which characterized in that, flash memory place electronic equipment includes write controller, buffer memory module and stand-by power supply, buffer memory module with flash memory links to each other, buffer memory module with write controller links to each other, stand-by power supply is used for when electronic equipment outage for buffer memory module and flash memory provide electric energy, the device includes:

a data writing unit for writing data into the cache module by the write controller;

The data block detection unit is used for responding to the power failure of the electronic equipment, and the cache module is used for detecting whether the data cached by the cache module is a complete data block or not;

And the detection result response unit is used for enabling the flash memory and the cache module to enter a power-down mode after the cache module detects that the cached data is a complete data block and the electronic equipment is powered off and writes the complete data into the flash memory, and disabling the cached data from being written into the flash memory and enabling the flash memory and the cache module to enter the power-down mode after the cache module detects that the cached data is not the complete data block.

9. An electronic device comprising a memory, a processor and a computer program stored in the memory and executable on the processor, wherein the computer program is caused by the processor to perform the method of any one of claims 1-7.

10. A computer program product comprising computer program instructions which, when run, cause the method of any of claims 1-7 to be performed.