CN120584559A

CN120584559A - Microelectronic devices and memory devices

Info

Publication number: CN120584559A
Application number: CN202380091689.0A
Authority: CN
Inventors: F·A·席赛克-艾吉; C·G·维杜威特
Original assignee: Micron Technology Inc
Current assignee: Micron Technology Inc
Priority date: 2023-01-19
Filing date: 2023-12-21
Publication date: 2025-09-02
Also published as: WO2024155421A1; KR20250137658A

Abstract

A microelectronic device includes a peripheral circuitry region, a memory region, a control circuitry structure, and a memory array structure. The peripheral circuitry region includes a central subregion and two arm subregions extending from the central subregion in a first horizontal direction. Each of the two arm subregions has a different length than the central subregion in a second horizontal direction orthogonal to the first horizontal direction. The memory region is horizontally outside the peripheral circuitry region. The control circuitry structure includes relatively more speed-critical circuitry within the horizontal region of the peripheral circuitry region and relatively less speed-critical circuitry within the horizontal region of the memory region. The memory array structure vertically underlies the control circuitry structure and includes an array of memory cells within the horizontal region of the memory region. Additional microelectronic devices and memory devices are also described.

Description

Microelectronic device and memory device

Cross reference to related applications

The present application is in accordance with 35U.S. c 119 (e) specification claiming the benefit of U.S. provisional patent application No. 63/480,623 filed on 1 month 19 of 2023, the disclosure of which is hereby incorporated by reference in its entirety.

Technical Field

In various embodiments, the present disclosure relates generally to the field of microelectronic device design and manufacture. More particularly, the present disclosure relates to microelectronic devices, and to related memory devices and electronic systems.

Background

Microelectronic device designers often desire to increase the level or density of integration of features within a microelectronic device by reducing the size of individual features and by reducing the separation distance between adjacent features. In addition, microelectronic device designers often desire an architecture that not only provides compactness, but also provides performance advantages, and desire simplified, easier, and cheaper manufacturing designs.

One example of a microelectronic device is a memory device. Memory devices are typically provided as internal integrated circuits in a computer or other electronic device. There are many types of memory devices including, but not limited to, volatile memory devices. One type of volatile memory device is a Dynamic Random Access Memory (DRAM) device. A DRAM device may include a memory array including DRAM cells arranged in rows extending in a first horizontal direction and columns extending in a second horizontal direction. In one design configuration, individual DRAM cells include an access device (e.g., a transistor) and a storage node device (e.g., a capacitor) electrically connected to the access device. The DRAM cells of a DRAM device are electrically accessible through digital lines and word lines arranged along rows and columns of a memory array and in electrical communication with control logic devices within the underlying control logic structure of the DRAM device.

Control logic devices underlying the memory array of the DRAM device within the underlying control logic structure have been used to control operations on the DRAM cells of the DRAM device. Control logic devices of the underlying control logic structure may be provided in electrical communication with digit lines and word lines coupled to the DRAM cells through wiring and contact structures. Unfortunately, the number, size, and arrangement of the different control logic devices employed within the underlying control logic structure may also undesirably hinder a reduction in memory device size (e.g., horizontal footprint) and/or performance improvement of the DRAM device (e.g., faster memory cell on/off speed, lower threshold switching voltage requirements, faster data transfer rates, lower power consumption).

Disclosure of Invention

In some embodiments, a microelectronic device includes a peripheral circuitry region, a memory bank region, a control circuitry structure, and a memory array structure. The peripheral circuitry area includes a center sub-area and two arm sub-areas extending from the center sub-area in a first horizontal direction from the center sub-area. Each of the two arm subregions has a different length than the center subregion in a second horizontal direction orthogonal to the first horizontal direction. The memory bank region is horizontally outside the peripheral circuitry region. The control circuitry structure includes relatively more speed critical circuitry within a horizontal region of the peripheral circuitry region and relatively less speed critical circuitry within a horizontal region of the memory bank region. The memory array structure is vertically underlying the control circuitry structure and includes an array of memory cells within the horizontal region of the memory bank region.

In additional embodiments, a microelectronic device includes a peripheral circuitry region, a memory bank region, a control circuitry structure, and a memory array structure. The peripheral circuitry area includes a substantially linearly extending scribe line sub-area in a first horizontal direction and an additional scribe line sub-area that extends substantially linearly in a second horizontal direction orthogonal to the first horizontal direction. The additional scribe line subregion horizontally intersects the scribe line subregion. The memory bank regions are horizontally separated from each other by the peripheral circuitry region. The control circuitry structure includes relatively more speed critical circuitry within a horizontal region of the peripheral circuitry region and relatively less speed critical circuitry within a horizontal region of the memory bank region. The memory array structure is located vertically below the control circuitry structure and includes an array of memory cells within the horizontal region of the memory bank region.

In a further embodiment, a memory device includes a peripheral circuitry area, a bank area, a control circuitry structure, and a memory array structure. The peripheral circuitry area includes a center sub-area and at least two additional sub-areas extending horizontally from the center sub-area. The memory bank region is horizontally adjacent to the peripheral circuitry region. The control circuitry structure includes relatively more speed critical circuitry within a horizontal region of the peripheral circuitry region and relatively less speed critical circuitry within a horizontal region of the memory bank region. The memory array structure is attached to and vertically offset from the control circuitry structure. The memory array structure includes an array of memory cells within the horizontal region of the bank region.

Drawings

Fig. 1 is a simplified schematic block diagram of a microelectronic device according to some embodiments of the present disclosure.

Fig. 2A is a simplified schematic view of the microelectronic device of fig. 1 illustrating a general layout of different regions of the microelectronic device, in accordance with some embodiments of the disclosure.

Fig. 2B is a simplified schematic view of the control circuitry structure of the microelectronic device depicted in fig. 2A, showing an arrangement of various circuitry of the control circuitry structure within different regions of the microelectronic device, according to some embodiments of the disclosure.

Fig. 2C is a simplified schematic diagram of a portion of the control circuitry structure depicted in fig. 2B, illustrating the arrangement of some circuitry of the control circuitry structure within the portion, according to some embodiments of the present disclosure.

Fig. 2D is a simplified schematic view of a memory array structure of the microelectronic device depicted in fig. 2A, showing an arrangement of various circuitry of the memory array structure within different regions of the microelectronic device, according to some embodiments of the disclosure.

Fig. 2E is a simplified schematic view of a portion of the memory array structure shown in fig. 2D, illustrating the arrangement of some circuitry of the memory array structure within the portion, according to some embodiments of the present disclosure.

Fig. 3A is a simplified schematic view of a microelectronic device illustrating a general layout of different regions of the microelectronic device, according to some embodiments of the disclosure.

Fig. 3B is a simplified schematic view of the control circuitry structure of the microelectronic device depicted in fig. 3A, showing an arrangement of various circuitry of the control circuitry structure within different regions of the microelectronic device, according to some embodiments of the disclosure.

Fig. 3C is a simplified schematic view of a memory array structure of the microelectronic device depicted in fig. 3A, showing an arrangement of various circuitry of the memory array structure within different regions of the microelectronic device, according to some embodiments of the disclosure.

Fig. 4 is a simplified schematic block diagram of an electronic system according to some embodiments of the present disclosure.

Detailed Description

The following description provides specific details, such as material compositions, shapes, and sizes, to provide a thorough description of embodiments of the present disclosure. However, it will be understood by those of ordinary skill in the art that embodiments of the present disclosure may be practiced without these specific details. Indeed, embodiments of the present disclosure may be practiced in conjunction with conventional microelectronic device fabrication techniques employed in the industry. In addition, the descriptions provided below do not form a complete process flow for fabricating microelectronic devices (e.g., memory devices). The structures described below do not form a complete microelectronic device. Only those process acts and structures necessary to understand the embodiments of the present disclosure are described in detail below. Additional acts of forming a complete microelectronic device from the structure may be performed by conventional fabrication techniques.

The drawings presented herein are for illustrative purposes only and are not meant to be actual views of any particular material, component, structure, device, or system. The shapes of the illustrations as a result, for example, of variations in manufacturing techniques and/or tolerances, are to be expected. Thus, the embodiments described herein should not be construed as limited to the particular shapes or regions illustrated but are to include deviations in shapes that result, for example, from manufacturing. For example, a region illustrated or described as a box may have rough and/or nonlinear features, and a region illustrated or described as a circle may include some rough and/or linear features. Furthermore, the acute angles described may be rounded off and vice versa. Accordingly, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the precise shape of a region and are not intended to limit the scope of the claims. The figures are not necessarily drawn to scale. In addition, elements common between figures may retain the same reference numerals.

As used herein, "memory device" means and includes microelectronic devices that exhibit memory functionality, but are not necessarily limited to memory functionality. In other words, and by way of non-limiting example only, the term "memory device" includes not only conventional memory (e.g., conventional volatile memory; conventional non-volatile memory), but also Application Specific Integrated Circuits (ASICs) (e.g., system on a chip (SoC)), microelectronic devices that combine logic and memory, and Graphics Processing Units (GPUs) that incorporate memory.

As used herein, the term "configured" refers to the size, shape, material composition, orientation, and arrangement of at least one structure and one or more of at least one apparatus that facilitate operation of one or more of the structure and the apparatus in a predetermined manner.

As used herein, the terms "vertical," "longitudinal," "horizontal," and "transverse" are with respect to the principal plane of the structure and are not necessarily defined by the gravitational field of the earth. A "horizontal" or "lateral" direction is a direction that is substantially parallel to the major plane of the structure, while a "vertical" or "longitudinal" direction is a direction that is substantially perpendicular to the major plane of the structure. The major plane of the structure is defined by the surface of the structure having a relatively larger area than the other surfaces of the structure. Referring to the figures, a "horizontal" or "lateral" direction may be perpendicular to the indicated "Z" axis and may be parallel to the indicated "X" axis and/or to the indicated "Y" axis, and a "vertical" or "longitudinal" direction may be parallel to the indicated "Z" axis, may be perpendicular to the indicated "X" axis and may be perpendicular to the indicated "Y" axis.

As used herein, features (e.g., regions, structures, devices) described as being "adjacent" to each other represent and include features of the disclosed individual (or individuals) that are positioned closest (e.g., closest) to each other. Additional features (e.g., additional regions, additional structures, additional devices) of the disclosed individual (or individuals) that do not match "adjacent" features may be disposed between the "adjacent" features. In other words, the "adjacent" features may be positioned directly adjacent to each other such that no other features intervene between the "adjacent" features, or the "adjacent" features may be positioned indirectly adjacent to each other such that at least one feature having an individual different from the individual associated with the at least one "adjacent" feature is positioned between the "adjacent" features. Thus, features described as being "vertically adjacent" to each other represent and include features of the disclosed individual (or individuals) that are positioned most vertically proximate (e.g., most vertically proximate) to each other. Furthermore, features described as being "horizontally adjacent" to each other represent and include features of the disclosed individual (or individuals) that are positioned closest to each other (e.g., closest horizontally).

As used herein, the term "intersection" means and includes the location where two or more features (e.g., regions, structures, materials, devices) or alternatively two or more portions of a single feature meet. For example, the point of intersection between a first feature extending in a first direction (e.g., the X-direction) and a second feature extending in a second direction (e.g., the Y-direction) different from the first direction may be the location where the first feature meets the second feature.

As used herein, for ease of description, spatially relative terms (e.g., "under," "bottom," "above," "upper," "top," "front," "back," "left," "right," and the like) may be used to describe one element or feature's relationship to another element(s) or feature(s), as illustrated in the figures. Unless otherwise specified, spatially relative terms are intended to encompass different orientations of the material in addition to the orientation depicted in the figures. For example, if the material in the figures is inverted, elements described as "under" or "on the bottom of" other elements or features would then be oriented "over" or "on top of the other elements or features. Thus, the term "under" may encompass both an orientation above and below the term, depending on the context in which the term is used, as will be apparent to one of ordinary skill in the art. The material may be otherwise oriented (e.g., rotated 90 degrees, inverted, flipped, etc.) and the spatially relative descriptors used herein interpreted accordingly.

As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

As used herein, "and/or" includes any and all combinations of one or more of the associated listed items.

As used herein, the phrase "coupled to" refers to structures that are operably connected to each other (e.g., electrically connected through a direct ohmic connection or through an indirect connection (e.g., through another structure)).

As used herein, the term "substantially" when referring to a given parameter, property, or condition means and includes the extent to which the given parameter, property, or condition satisfies to a varying extent (e.g., within acceptable tolerances) as would be understood by one of ordinary skill in the art. For example, depending on the particular parameter, property, or condition that is substantially met, the parameter, property, or condition may be at least 90.0% met, at least 95.0% met, at least 99.0% met, at least 99.9% met, or even 100.0% met.

As used herein, "about" or "approximately" when referring to a numerical value of a particular parameter includes the numerical value and the degree of variation of the numerical value within an acceptable tolerance for the particular parameter will be understood by one of ordinary skill in the art. For example, "about" or "approximately" when referring to a numerical value may include additional numerical values ranging from 90.0% to 110.0% of the numerical value (e.g., ranging from 95.0% to 105.0% of the numerical value, ranging from 97.5% to 102.5% of the numerical value, ranging from 99.0% to 101.0% of the numerical value, ranging from 99.5% to 100.5% of the numerical value, or ranging from 99.9% to 100.1% of the numerical value).

Fig. 1 is a simplified schematic block diagram of a microelectronic device 100 (e.g., a memory device, such as a DRAM device) according to some embodiments of the present disclosure. The microelectronic device 100 may include a control circuitry structure (e.g., a control circuitry wafer) vertically overlying a memory array structure (e.g., a memory array wafer). The memory array structure may include an array of one or more memory cells (e.g., volatile memory cells, such as DRAM cells). The control circuitry structure may include control logic devices formed from and including Complementary Metal Oxide Semiconductor (CMOS) circuitry. At least a majority of the CMOS circuitry (and thus control logic devices) of the microelectronic device 100 may be located within the control circuitry structure (and thus outside of the memory array structure). In addition, at least some of the CMOS circuitry may be positioned vertically over a horizontal area of the memory cell array(s). Thus, the microelectronic device 100 may be considered to have a so-called "CMOS on array (CaA)" configuration. In some embodiments, the control circuitry structure is formed at least partially separate from the memory array structure and then the control circuitry structure is attached to the memory array structure using an oxide-oxide bond or a combination of an oxide-oxide bond and a metal-metal bond.

In fig. 1, dashed boxes are employed to identify various features (e.g., various modules, various devices, various circuitry) that may be positioned within the vertical boundaries of the control circuitry structure of the microelectronic device 100 (rather than within the vertical boundaries of the memory array structure of the microelectronic device 100). All features (e.g., all modules, all devices, all circuitry) within the horizontal region of the individual dashed box depicted in fig. 1 may be included within the control circuitry structure of the microelectronic device 100, or some features (e.g., some modules, some devices, some circuitry) within the horizontal region of the individual dashed box may be included within the control circuitry structure of the microelectronic device 100, and some features within the horizontal region of the individual dashed box may be included within the memory array structure of the microelectronic device 100. As described in further detail below, at least a bank of memory cells of the microelectronic device 100 can be included within the memory array structure, and can be in electrical communication with various control logic circuitry (e.g., CMOS circuitry) and devices included within the control circuitry structure of the microelectronic device 100.

As shown in fig. 1, the microelectronic device 100 may include an assembly of features (e.g., devices, circuitry, structures). For example, the microelectronic device 100 may include a memory array 102, a column address decoder 104, a row address decoder 106, sense amplifiers 108, word Line (WL) drivers 114, command and Address (CA) input circuitry 115, control register circuitry 122, voltage generator circuitry 134, internal clock and timing generator circuitry 136, data I/O and control circuitry 138, and data path circuitry 140.CA input circuitry 115 may include, but is not limited to, CA input buffer circuitry 116, control input buffer circuitry 118, and clock input buffer circuitry 120. Control register circuitry 122 may include, but is not limited to, CA decoder circuitry 124, mode registers 126, test Mode (TM) logic circuitry 128, self-refresh circuitry 130, and fuse circuitry 132. Data path circuitry 140 may include, but is not limited to, input/output (I/O) logic circuitry 112 and Error Correction Code (ECC) circuitry 141. The microelectronic device 100 may further include terminals in electrical communication with external circuitry. For example, the microelectronic device 100 can include, but is not limited to, a CA terminal 142, a control input terminal 144, a clock input terminal 146, a data terminal 148, a calibration terminal 150, a power terminal 152, and an alarm terminal 153. The foregoing features and additional features of the microelectronic device 100 are described in further detail below. Additionally, while fig. 2 depicts a particular configuration of the microelectronic device 100, it will be appreciated that the microelectronic device 100 may include additional features (e.g., additional devices, additional circuitry, additional structures), different features (e.g., different devices, different circuitry, different structures), and/or different arrangements of features than the features schematically depicted in fig. 1. Fig. 1 illustrates just one non-limiting example of a microelectronic device 100.

The memory array 102 may include a plurality of memory banks. Each of the banks may include a plurality of word lines extending in a first horizontal direction, a plurality of digit lines extending in a second horizontal direction orthogonal to the first horizontal direction, and a plurality of memory cells arranged at intersections of the word lines and the digit lines. A row of memory cells may be coupled to a word line and a column of memory cells may be coupled to a digit line. The memory cells of the memory array 102 may include, for example, DRAM cells, resistive Random Access Memory (RRAM) cells, conductive bridge random access memory (conductive bridge RAM) cells, magnetic Random Access Memory (MRAM) cells, phase Change Material (PCM) memory cells, phase Change Random Access Memory (PCRAM) cells, spin torque transfer random access memory (STTAM) cells, oxygen vacancy based memory cells, programmable conductor memory cells, or other types of memory cells. In some embodiments, the memory cells of the memory array 102 are DRAM cells. The memory array 102 (including word lines, digit lines, and memory cells thereof) can be positioned within a memory array structure (e.g., a memory array die) of the microelectronic device 100.

The column address decoder 104 may be configured and operative to select a particular digit line of the memory array 102 based on the column address signals 154 received thereby. Optionally, the microelectronic device 100 can also include column repair circuitry in electrical communication with the column address decoder 104 and configured and operative to replace defective columns of memory cells of the memory array 102 with spare, non-defective columns of memory cells of the memory array 102. Column repair circuitry may transform column address signals 154, which identify defective columns of memory cells, to another column address signal, which identifies spare, non-defective columns of memory cells, directed to column address decoder 104. The defective columns of memory cells may be determined, for example, using TM logic circuitry 128 of microelectronic device 100. The column address decoder 104 and column repair circuitry, if any, may be located within the control circuitry structure (e.g., control circuitry die) of the microelectronic device 100.

The sense amplifier 108 may be configured and operated to receive a digit line input from a digit line selected by the column address decoder 104 and to generate a digital data value during a read operation. The sense amplifiers 108 may be connected to respective digit lines and to respective local pairs of I/O lines of the I/O logic circuitry 112. The sense amplifier 108 may be positioned within the control circuitry structure of the microelectronic device 100.

The row address decoder 106 may be configured and operative to select a particular word line of the memory array 102 based on the row address signals 156 received thereby. Optionally, the microelectronic device 100 can also include row repair circuitry in electrical communication with the row address decoder 106 and configured and operative to replace spare, non-defective rows of memory cells of the memory array 102 with defective rows of memory cells of the memory array 102. The row repair circuitry may transform row address signals 156 identifying defective rows of memory cells to another row address signal identifying spare, non-defective rows of memory cells directed to row address decoder 106. The defective row of memory cells may be determined, for example, using TM logic circuitry 128 of microelectronic device 100. The row address decoder 106 and row repair circuitry, if any, may be located within the control circuitry structure of the microelectronic device 100.

The WL driver 114 may be in electrical communication with the row address decoder 106 and may be configured and operated to activate a word line of the memory array 102 based on a word line select command received from the row address decoder 106. The memory cell lines of the memory array 102 are accessible through an access device (e.g., transistor) of the memory cells for reading or programming by using the voltages applied on the word lines by the WL driver 114. WL driver 114 may be located within the control circuitry structure of microelectronic device 100.

As depicted in fig. 1, CA input buffer circuitry 116, control input buffer circuitry 118, and clock input buffer circuitry 120 of CA input circuitry 115 may be positioned within vertical boundaries of the control circuitry structure of microelectronic device 100. CA input buffer circuitry 116, control input buffer circuitry 118, and clock input buffer circuitry 120 are each described in further detail below. The CA input circuitry 115 may be operably associated with a CA terminal 142, a control input terminal 144, and a clock input terminal 146 of the microelectronic device 100, as also described in further detail below.

CA input buffer circuitry 116 of CA input circuitry 115 may be coupled to CA terminal 142. The CA terminal 142 may receive external address signals, but is not limited to, external command signals (collectively referred to herein as external CA signals 158) from an external memory controller. CA input buffer circuitry 116 may receive external CA signals 158 (e.g., external address signals, external command signals) from CA terminals 142 and may generate internal address signals and internal command signals (collectively referred to herein as internal CA signals 160). The internal CA signal 160 may be supplied to CA decoder circuitry 124 of the control register circuitry 122. In some embodiments, CA input buffer circuitry 116 may also be coupled to TM logic circuitry 128 of control register circuitry 122, and commands associated with various TM functions may be incorporated therein. In some such embodiments, the TM functions may be referred to as or include aspects of design test (DFT) functions, such as trim set functions (e.g., latch trim conditions without programming fuses), read/write timing functions, fuse access functions, built-in self test (BIST) functions, and connectivity test functions.

Control input buffer circuitry 118 of CA input circuitry 115 may be coupled to control input terminal 144. Control input terminal 144 may receive external control signals 162, such as, but not limited to, an external Chip Select (CS) signal, an external clock enable (CKE) signal, an external on-die termination (ODT) signal, and an external reset signal, from external circuitry. Control input buffer circuitry 118 may receive external control signals 162 (e.g., external CS signal, external CKE signal, external ODT signal, external reset signal) from control input terminal 144 and may generate associated internal control signals 164 (e.g., internal CS signal, internal CKE signal, internal ODT signal, internal reset signal). Internal control signals 164 may be supplied to control register circuitry 122 for performing memory operations. For example, the internal CS signal may be used to select the microelectronic device 100 to respond to the external CA signal 158 directed to the CA terminal 142. As another example, the internal CKE signal may be used to enable the clock input buffer circuitry 120 to receive various external clock signals that the clock input buffer circuitry 120 may then act on to generate various internal clock signals, as described in further detail below.

The clock input buffer circuitry 120 of the CA input circuitry 115 may be coupled to a clock input terminal 146. The clock input terminal 146 may receive external clock signals 166, such as, but not limited to, external Clock (CK) signals, external/CK signals, external data clock (WCK) signals, and external/WCK signals, from external circuitry. The external CK and/CK signals may be complementary, and the external WCK and/WCK signals may also be complementary. The complementary clock signals may have opposite clock levels and transition between the opposite clock levels at the same time. For example, when the clock signal is at a low clock level, the complementary clock signal is at a high level, and when the clock signal is at a high clock level, the complementary clock signal is at a low clock level. Further, when the clock signal transitions from a low clock level to a high clock level, the complementary clock signal transitions from a high clock level to a low clock level, and when the clock signal transitions from a high clock level to a low clock level, the complementary clock signal transitions from a low clock level to a high clock level. Clock input buffer circuitry 120 may receive external clock signals 166 (e.g., external CK signals, external/CK signals, external WCK signals, external/WCK signals) from clock input terminals 146 and may generate associated internal clock signals 168 (e.g., internal CK signals, internal/CK signals, internal WCK signals, internal/WCK signals), internal clock signals 168 may be supplied to internal clock circuitry to provide various phase and frequency controlled internal clock signals based on received internal clock signals 168.

Still referring to fig. 1, at least some (e.g., substantially all) of the control register circuitry 122 can be positioned within a vertical boundary of the control circuitry structure of the microelectronic device 100. For example, the CA decoder circuitry 124, mode register 126, TM logic circuitry 128, self-refresh circuitry 130, and fuse circuitry 132 of the control register circuitry 122 may be positioned within the vertical boundaries of the control circuitry structure of the microelectronic device 100.

CA decoder circuitry 124 may include circuitry configured and operative to decode internal CA signals 160 from CA input buffer circuitry 116 to generate various internal signals and commands for performing memory operations. The CA decoder circuitry 124 may be configured and operated for address decoding functionality and command decoding functionality. For example, the CA decoder circuitry 124 may receive and decode internal address signals from the CA input buffer circuitry 116, and may supply column address signals 154 (which may also be referred to as "decoded column address signals") to the column address decoder 104, and may supply row address signals 156 (which may also be referred to as "decoded row address signals") to the row address decoder 106.CA decoder circuitry 124 may also receive bank address signals and may supply the bank address signals to column address decoder 104 and row address decoder 106. As another example, CA decoder circuitry 124 may receive and decode internal command signals from CA input buffer circuitry 116, and may generate various internal signals and commands for performing memory operations, such as row command signals to select word lines and column command signals to select digit lines. The internal command signals may also include output and input activate commands, such as clock control commands.

The mode register 126 may be configured and operated to track various counts or values (e.g., a count of refresh commands received by the microelectronic device 100 or self-refresh operations performed by the microelectronic device 100). In some embodiments, some of the mode registers 126 are configured to store operating parameters to provide flexibility in performing various functions, features, and modes (e.g., TM functions).

TM logic circuitry 128 may be configured and operate to perform various TM functions defined by the manufacturer of microelectronic device 100. Such TM functionality may only be used by the manufacturer, and not by entities that subsequently obtain the microelectronic device 100 from the manufacturer. For example, manufacturers may perform connectivity tests designed to accelerate testing of electrical continuity of pin interconnects between the microelectronic device 100 and a host device (e.g., a memory controller). TM logic circuitry 128 may be coupled to one or more mode registers 126. In some embodiments, TM logic circuitry 128 reads mode register 126 to determine the particular TM function to perform based on the data stored in mode register 126. In additional embodiments, the TM logic 128 stores data in the mode register 126 such that other functional blocks in the microelectronic device 100 perform desired functions based on the data stored in the mode register 126 (e.g., data related to various TM functions and/or DFT functions).

The self-refresh circuitry 130 may be in electrical communication with the row address decoder 106 and may be configured and operated to periodically recharge data stored in the memory array 102. During a self-refresh operation, the self-refresh circuitry 130 may be activated in response to internal command signals and may generate different row address signals that may be forwarded to the row address decoder 106. The row address decoder 106 may then select a particular word line based on the different row address signals received from the self-refresh circuitry 130. The row address decoder 106 may then communicate with the WL driver 114 to activate the selected word line, and then the charge accumulated in a storage node (e.g., a capacitor) of the memory array 102 operably associated with the selected word line may be amplified by a sense amplifier and then stored again in the capacitor.

Fuse circuitry 132 may include an array of fuses that may be one-time programmable non-volatile memory elements. In some embodiments, the fuse circuitry 132 may be replaced with an array of other non-volatile memory elements (e.g., metal switches, fused capacitor devices, transistors with fused gate oxides, NAND memory cells, PCM cells, magnetic memory cells). The fuse circuitry 132 may store various operational information of the microelectronic device 100 by programming one or more fuses therein, such as trim settings including particular timing and/or voltage parameters, read/write clock conditions based on read/write timing results, control bits to enable or disable customer-specific features or functionality, redundant implementation information for repairing a portion of the memory array 102. In some embodiments, fuses in the fuse circuitry 132 may exhibit a high resistance state (e.g., logic 0) when the microelectronic device 100 is fabricated (e.g., through an oxide layer disposed between two conductive layers). One or more fuses in fuse circuitry 132 may be programmed to exhibit a low resistance state (e.g., a logic 1) when a fuse programming voltage or current is applied across the one or more fuses (e.g., by physically changing the oxide layer by electrical stress such that the two conductive layers are connected via a conductive path). Thus, once fuses are programmed (e.g., oxide layers are ruptured to exhibit a low resistance state (logic 1)), the programmed fuses may not be unprogrammed (e.g., to recover their original high resistance state (logic 0)). Such fuses may be referred to as antifuses.

As depicted in fig. 1, control register circuitry 122 may generate column address signals 154 and row address signals 156 that are supplied to column address decoder 104 and row address decoder 106, respectively. As previously discussed herein, the row address decoder 106 may be coupled to a WL driver 114, the driver 114 activating a respective row of memory cells in the memory array 102 corresponding to the received row address. In addition, the selected digit line(s) corresponding to the received column address may be coupled to read/write circuitry to provide read data to the data output buffer of the I/O logic circuitry 112 through the I/O data bus 170. Write data may be applied to the memory array 102 through data input buffers and read/write circuitry of the I/O logic circuitry 112.

The control register circuitry 122 may also be in electrical communication with the alarm terminal 153, and if certain errors are detected, the alarm signal 172 may be supplied to external circuitry (e.g., system processor, controller) in electrical communication with the alarm terminal 153. As a non-limiting example, if a Cyclic Redundancy Check (CRC) error is detected, an alarm signal 172 may be transmitted from the microelectronic device 100.

The voltage generator circuitry 134 may be coupled to a power supply terminal 152. The power supply terminal 152 may receive various potentials 174 from external circuitry, such as, but not limited to, a drain power supply voltage (V _DD) potential, a power supply voltage (V _CC) potential, and a ground (V _SS) potential. The voltage generator circuitry 134 generates various internal potentials 176 such as, but not limited to, a pump precharge (V _PP) potential (or a read/write bias potential), a V _OD potential, an array voltage (V _ARY) potential, a peripheral voltage (V _PERI) potential, and a V _POP potential. As non-limiting examples, the V _PP potential may be used for the row address decoder 106, the V _OD and V _ARY potentials may be used for the sense amplifier 108, the V _PERI potential may be used for other circuitry blocks, and the V _POP potential may be used for the fuse circuitry 132. The power supply terminal 152 and voltage generator circuitry 134 may also be supplied with an output driver power supply (V _DDQ) potential and a V _SSQ potential. The V _DDQ potential and the V _SSQ potential may be supplied to the data I/O and control circuitry 138. The V _DDQ and V _SSQ potentials may be the same as the V _DD and V _SS potentials, respectively, but the V _DDQ and V _SSQ potentials may be used for the data I/O and control circuitry 138 such that power supply noise generated by the data I/O and control circuitry 138 does not propagate to other circuitry. The voltage generator circuitry 134 may be positioned within the vertical boundaries of the control circuitry structure of the microelectronic device 100.

The internal clock and timing generator circuitry 136 may be configured to receive a clock signal (e.g., an internal clock signal, an external clock signal) and generate a phase-controlled internal clock signal 178 in response thereto. Although not limited in this regard, one or more of Delay Locked Loop (DLL) circuitry and Phase Locked Loop (PLL) circuitry may be used for the internal clock and timing generator circuitry 136.DLL circuitry and PLL circuitry may be used for similar purposes and may be used to maintain a fixed timing relationship between signals in environments where process, voltage and temperature variations change these relationships over time, respectively. During operation, the DLL circuitry and PLL circuitry may continuously compare the relationship between two signals and provide feedback to adjust and maintain a fixed relationship between them. DLL circuitry and PLL circuitry may be used to maintain a timing relationship between the clock signal and the output data signal. Maintaining the timing relationship between the clock and the output data with the DLL circuitry and PLL circuitry results in improved timing margins and facilitates faster signaling speeds. In some embodiments, the internal clock and timing generator circuitry 136 includes at least DLL circuitry. The DLL circuitry may include, but is not limited to, one or more (e.g., each) of a DLL differential delay line and delay selection logic circuit, a DLL clock phase interpolator circuit, a DLL output clock comparator circuit, a DLL output circuit, a DLL phase detector circuit, a DLL clock inversion control circuit, a DLL control (coarse and fine control) logic circuit, a DLL bias generator control circuit, a DLL auto-reset block circuit, a DLL enable logic circuit, a bit line dithering circuit, and a Ltree stage circuit. The phase-controlled internal clock signal 178 generated by the internal clock and timing generator circuitry 136 may be supplied to the data I/O and control circuitry 138, for example, and may be used as a timing signal for determining the output timing of the read data. The internal clock and timing generator circuitry 136 may be positioned within the vertical boundaries of the control circuitry structure of the microelectronic device 100.

Data I/O and control circuitry 138, which may also be referred to herein as Data Queue (DQ) circuitry, may be coupled to data terminals 148, such as DQ terminals, read data strobe (RDQS) terminals, data Bus Inversion (DBI) terminals, DMI terminals, and calibration terminals 150, such as ZQ terminals. In addition, data I/O and control circuitry 138 may also be in electrical communication with control register circuitry 122, voltage generator circuitry 134, internal clock and timing generator circuitry 136, and data path circuitry 140. The data I/O and control circuitry 138 may receive data signals 180 (e.g., DQ signals, such as read DQ signals and write DQ signals; DBI signals, DMI signals) and supply the data signals 180 to the data terminals 148 in response to different commands (e.g., read commands, write commands). In addition, the data I/O and control circuitry 138 may communicate with ECC circuitry 141 of the data path circuitry 140 through a global I/O data bus 186. In addition, the data I/O and control circuitry 138 may also, but is not limited to, receive and act on the phase controlled internal clock signal 178 from the internal clock and timing generator circuitry 136, the calibration signal 182 from the calibration terminal 150, and the I/O control signal 184 from the control register circuitry 122. The data I/O and control circuitry 138 may include, but is not limited to, read circuitry, write parallelization, read training control, input buffer circuitry, input buffer latch circuitry, decision Feedback Equalizer (DFE) circuitry, device Interface Board (DIB) circuitry, DQ shift (data queue pin connect/shifter) circuitry, data Queue Strobe (DQs) circuitry, DQs receiver path circuitry, phase generator circuitry, DCC circuitry, DCRC circuitry, clock and power control circuitry, read control circuitry, data serializer circuitry, and data output buffer circuitry. The data I/O and control circuitry 138 may be positioned within the vertical boundaries of the control circuitry structure of the microelectronic device 100.

Still referring to fig. 1, at least some (e.g., substantially all) of the data path circuitry 140 may be positioned within the vertical boundaries of the control circuitry structure of the microelectronic device 100. For example, the I/O logic circuitry 112 and ECC circuitry 141 of the data path circuitry 140 may be positioned within the vertical boundaries of the control circuitry structure of the microelectronic device 100.

The I/O logic circuitry 112 may be configured and operated to receive data from the digit lines selected by the column address decoder 104 during a read operation and to output data to the digit lines selected by the column address decoder 104 during a write operation. During a read operation, digital data values generated by the sense amplifier 108 may be supplied to the data output buffer of the I/O logic circuitry 112 through the I/O data bus 170. In addition, during write operations, write data from the data input buffers of the I/O logic circuitry 112 may be supplied to the memory array 102 through the I/O data bus 170.

The ECC circuitry 141 may be configured and operated to generate an ECC code (also referred to as "check bits"). The ECC code may correspond to a particular data value, and may be stored in a memory cell of the memory array 102 along with the data value. When the data value is read back from the memory cell, another ECC code is generated and compared to the previously generated ECC code to access the memory cell. If not zero, the difference between the previously generated ECC code and the newly generated ECC code indicates that an error has occurred. If an error condition is detected, then ECC circuitry 141 can be utilized to correct the error data. ECC circuitry 141 may be in electrical communication with I/O logic circuitry 112 via an intermediate I/O data bus 188 and may be in electrical communication with data I/O and control circuitry 138 via a global I/O data bus 186.

During use and operation of the microelectronic device 100, when a read command is issued and row and column addresses are timely supplied with the read command, read data can be read from memory cells in the memory array 102 specified by the row and column addresses. The read command may be received by the CA decoder circuitry 124, which may provide an internal command to the data I/O and control circuitry 138 such that read data may be output from the data terminals 148 (e.g., data Queue (DQ) terminals, read data strobe (RDQS) terminals, data Bus Inversion (DBI) terminals, DMI terminals) through the read/write amplifier and the data I/O and control circuitry 138 according to a clock signal (e.g., internal CK signal, internal/CK signal). The read data may be provided at a time defined by read latency information that may be programmed in a mode register 126 in the microelectronic device 100. The read latency information may be defined in terms of clock cycles of the clock signal. For example, the read latency information may be the number of clock cycles of the signal when the associated read data is provided after a read command is received by the microelectronic device 100.

In addition, during use and operation of the microelectronic device 100, when a write command is issued and row and column addresses are timely supplied with the write command, write data may be supplied to the data terminals 148 (e.g., data Queue (DQ) terminals, read data strobe (RDQS) terminals, data Bus Inversion (DBI) terminals, DMI terminals) according to other clock signals (e.g., internal WCK signals, internal/WCK signals). The write command may be received by the CA decoder circuitry 124, the CA decoder circuitry 124 may provide internal commands to the data I/O and control circuitry 138 such that the write data may be received by a data receiver in the data I/O and control circuitry 138 and supplied to the memory array 102 through the data I/O and control circuitry 138 and read/write amplifiers. Write data may be written into memory cells specified by row and column addresses. Write data may be provided to the data terminals 148 at times defined by the write latency information. The write latency information may be programmed in a mode register 126 in the microelectronic device 100. The write latency information may be defined in terms of clock cycles of the clock signal. For example, the write latency information may be the number of clock cycles of a signal when associated write data is received after a write command is received by the microelectronic device 100.

Fig. 2A-2E are simplified schematic views of different portions of the microelectronic device 100 shown in fig. 1, according to some embodiments of the disclosure. Fig. 2A is a simplified schematic view of a microelectronic device 100 illustrating a general layout (e.g., a floor plan) of different regions of the microelectronic device 100, according to some embodiments of the disclosure. Fig. 2B is a simplified schematic view of a control circuitry structure 200 of the microelectronic device 100 showing an arrangement of various circuitry of the control circuitry structure 200 within different regions of the microelectronic device 100, according to some embodiments of the disclosure. Fig. 2C is a simplified schematic diagram of portion a of the control circuitry structure 200 shown in fig. 2B (illustrated with a dashed box in fig. 2B) illustrating the arrangement of some circuitry of the control circuitry structure 200 within portion a, according to some embodiments of the present disclosure. Fig. 2D is a simplified schematic view of a memory array structure 300 of a microelectronic device 100 showing an arrangement of various circuitry of the memory array structure 300 within different regions of the microelectronic device 100, according to some embodiments of the disclosure. Fig. 2E is a simplified schematic view of portion B (illustrated with a dashed box in fig. 2B) of the memory array structure 300 shown in fig. 2D, illustrating the arrangement of some circuitry of the memory array structure 300 within portion B, according to some embodiments of the present disclosure.

Referring to fig. 2A, the microelectronic device 100 may include a peripheral circuitry region 202 and a memory bank region 204. As described in further detail below, within the control circuitry structure 200 (fig. 2B), relatively more speed critical circuitry and devices may be located within the horizontal area of the peripheral circuitry region 202, and relatively less speed critical circuitry and devices may be located within the horizontal area of the memory bank region 204. The relatively more speed critical circuitry and devices of control circuitry structure 200 (FIG. 2B) include, for example, data Bus (DB) circuitry, data bus strobe (DQS) circuitry, delay Locked Loop (DLL) circuitry, phase Locked Loop (PLL) circuitry, and Command Address (CA) circuitry. Relatively less speed critical circuitry and devices of control circuitry structure 200 (fig. 2B) include, for example, antifuse circuitry, repair circuitry, voltage generator circuitry, analog temperature distribution circuitry, and data junction multiplexer circuitry. The memory bank regions 204 may include a first memory bank region 204A (e.g., an upper memory bank region) and a second memory bank region 204B (e.g., a lower memory bank region). The peripheral circuitry area 202 may be interposed horizontally (e.g., along the Y-direction) between the first bank area 204A and the second bank area 204B.

The peripheral circuitry area 202 of the microelectronic device 100 may include a center sub-area 202A, a first arm sub-area 202B, and a second arm sub-area 202C. As shown in fig. 2A, the center sub-region 202A may be integral and continuous with the first and second arm sub-regions 202B, 202C, and may be horizontally interposed between the first and second arm sub-regions 202B, 202C along the X-direction (e.g., the first horizontal direction). The first arm subregion 202B and the second arm subregion 202C may be positioned at or near corners (e.g., diagonal corners) of the center subregion 202A that are opposite each other. For example, the first arm subregion 202B may be positioned at or near a first corner of the center subregion 202A, and the second arm subregion 202C may be positioned at or near a second corner of the center subregion 202A that is diagonally opposite (e.g., a small corner) the first corner. Thus, the peripheral circuitry area 202 may extend in a non-linear path across the microelectronic device 100 in the X-direction.

As shown in fig. 2A, the center sub-region 202A, the first arm sub-region 202B, and the second arm sub-region 202C may exhibit rectangular horizontal cross-sectional shapes that, in combination, provide the peripheral circuitry area 202 with irregular horizontal cross-sectional shapes. The rectangular horizontal cross-sectional shape of the center sub-region 202A may be different from the rectangular horizontal cross-sectional shapes of the first arm sub-region 202B and the second arm sub-region 202C. The rectangular horizontal cross-sectional shapes of the first arm segment 202B and the second arm segment 202C may be substantially the same as each other, or may be different from each other. In some embodiments, the rectangular horizontal cross-sectional shapes of the first arm subregion 202B and the second arm subregion 202C are substantially identical to each other.

In some embodiments, the horizontal center of the center sub-region 202A of the peripheral circuitry area 202 is substantially aligned with the horizontal center of the microelectronic device 100. For example, a horizontal centerline of the center sub-region 202A in the Y-direction may be substantially aligned with a horizontal centerline 210 of the microelectronic device 100 in the Y-direction, and an additional horizontal centerline of the center sub-region 202A in the X-direction may be substantially aligned with an additional horizontal centerline 212 of the microelectronic device 100 in the X-direction. The horizontal centerline 210 of the microelectronic device 100 in the Y-direction may extend substantially linearly in the X-direction, and the additional horizontal centerline 212 of the microelectronic device 100 in the X-direction may extend substantially linearly in the Y-direction. In additional embodiments, the horizontal center of the center sub-region 202A of the peripheral circuitry area 202 is offset from the horizontal center of the microelectronic device 100. For example, the horizontal centerline of the center sub-region 202A in the Y-direction may be offset from the horizontal centerline 210 of the microelectronic device 100 in the Y-direction, and/or the horizontal centerline of the center sub-region 202A in the X-direction may be offset from the additional horizontal centerline 212 of the microelectronic device 100 in the X-direction.

The horizontal centers of the first arm segment 202B and the second arm segment 202C of the peripheral circuitry region 202 are offset from the horizontal center of the microelectronic device 100. The horizontal centerline of the first arm subregion 202B in the Y-direction may be offset from the horizontal centerline 210 of the microelectronic device 100 in the Y-direction and the horizontal centerline of each of the center subregion 202A and the second arm subregion 202C in the Y-direction. The additional horizontal centerline of the first arm subregion 202B in the X-direction may be offset from the additional horizontal centerline 212 of the microelectronic device 100 in the X-direction and the additional horizontal centerlines of each of the center subregion 202A and the second arm subregion 202C in the X-direction. In addition, the horizontal centerline of the second arm subregion 202C in the Y direction may be offset from the horizontal centerline 210 of the microelectronic device 100 in the Y direction and the horizontal centerline of each of the center subregion 202A and the first arm subregion 202B in the Y direction. The additional horizontal centerline of the second arm subregion 202C in the X-direction may be offset from the additional horizontal centerline 212 of the microelectronic device 100 in the X-direction and the additional horizontal centerline of each of the center subregion 202A and the first arm subregion 202B in the X-direction. In some embodiments, the horizontal centerlines of the first and second arm subregions 202B, 202C in the Y-direction are offset from the horizontal centerlines of the central subregion 202A in the Y-direction by substantially the same horizontal distance from each other (e.g., in the positive Y-direction for the first arm subregion 202B and in the negative Y-direction for the second arm subregion 202C). In additional embodiments, the horizontal centerlines of the first and second arm subregions 202B, 202C in the Y-direction are offset from the horizontal centerlines of the central subregion 202A in the Y-direction by different horizontal distances from each other.

As shown in fig. 2A, the center subregion 202A of the peripheral circuitry region 202 may have a first length L ₁ in the Y-direction and a first width W ₁ in the X-direction, the first arm subregion 202B of the peripheral circuitry region 202 may have a second length L ₂ in the Y-direction and a second width W ₂ in the X-direction, and the second arm subregion 202C of the peripheral circuitry region 202 may have a third length L ₃ in the Y-direction and a third width W ₃ in the X-direction. The first length L ₁ of the center sub-region 202A may be greater than each of the second length L ₂ of the first arm sub-region 202B and the third length L ₃ of the second arm sub-region 202C. In some embodiments, the first length L ₁ of the center sub-region 202A is greater than the combined length of the second length L ₂ of the first arm sub-region 202B and the third length L ₃ of the second arm sub-region 202C. The second length L ₂ of the first arm subregion 202B may be substantially equal to the third length L ₃ of the second arm subregion 202C, or the second length L ₂ of the first arm subregion 202B may be different than the third length L ₃ of the second arm subregion 202C. In addition, the first width W ₁ of the center sub-region 202A, the second width W ₂ of the first arm sub-region 202B, and the third width W ₃ of the second arm sub-region 202C may be substantially equal to one another, or the first length W ₁ of the center sub-region 202A, At least one of the second width W ₂ of the first arm subregion 202B and the third width W ₃ of the second arm subregion 202C may be different (e.g., greater than, less than) than at least one other of the first length W ₁ of the center subregion 202A, the second width W ₂ of the first arm subregion 202B, and the third width W ₃ of the second arm subregion 202C (e.g., one other, two others). In some embodiments, the first length W ₁ of the center sub-region 202A, the second width W ₂ of the first arm sub-region 202B, and the third width W ₃ of the second arm sub-region 202C are substantially equal to one another. In some embodiments, the second width W ₂ of the first arm subregion 202B and the third width W ₃ of the second arm subregion 202C are substantially equal to each other and are different (e.g., greater than, less than) the first length W ₁ of the center subregion 202A.

Still referring to fig. 2A, the memory bank region 204 (e.g., first memory bank region 204A, second memory bank region 204B) may individually include a combination of a first memory bank sub-region 206 and a second memory bank sub-region 208. As described in further detail below, within the memory array structure 300 (fig. 2D) of the microelectronic device 100, the memory banks of memory cells may be positioned within the horizontal regions of the first 206 and second 208 memory bank sub-regions of the memory bank region 204. The first bank sub-region 206 may have a different horizontal geometric configuration (e.g., different horizontal size, different horizontal shape) than the second bank sub-region 208. For example, the individual first bank sub-regions 206 are relatively longer in the Y-direction and relatively narrower in the X-direction than the individual second bank sub-regions 208. However, as described in further detail below, the number of memory cells within the banks of memory cells within the horizontal area of the individual first bank sub-area 206 may be substantially equal to the number of memory cells within the additional banks of memory cells within the horizontal area of the individual second bank sub-area 208.

The memory bank regions 204 (e.g., first memory bank region 204A, second memory bank region 204B) of the microelectronic device 100 individually include a group of first memory bank sub-regions 206 and a group of second memory bank sub-regions 208. For example, the first bank region 204A may include a group of first bank sub-regions 206 and a group of second bank sub-regions 208 horizontally adjacent to the group of first bank sub-regions 206 in the X-direction (e.g., positive X-direction), and the second bank region 204B may include an additional group of first bank sub-regions 206 and an additional group of second bank sub-regions 208 horizontally adjacent to the additional group of first bank sub-regions 206 in the X-direction (e.g., negative X-direction). For an individual bank region 204, the combination of the group of first bank sub-regions 206 with the group of second bank sub-regions 208 may provide an irregular horizontal cross-sectional shape, such as an "L-shaped" horizontal cross-sectional shape, to the bank region 204. The horizontal cross-sectional shape (e.g., L-shaped horizontal cross-sectional shape) of the first memory bank region 204A may be inverted (e.g., flipped) in the X-direction relative to the horizontal cross-sectional shape (e.g., L-shaped horizontal cross-sectional shape) of the second memory bank region 204B.

As shown in fig. 2A, the group of first memory bank sub-regions 206 of the first memory bank region 204A may be completely horizontally offset from the additional group of first memory bank sub-regions 206 of the second memory bank region 204B in the X-direction, and the group of first memory bank sub-regions 206 of the first memory bank region 204A may partially (e.g., incompletely) horizontally overlap with the additional group of first memory bank sub-regions 206 of the second memory bank region 204B in the Y-direction. Furthermore, as shown in FIG. 2A, the group of second bank sub-regions 208 of the first bank region 204A may be completely horizontally offset from the additional group of second bank sub-regions 208 of the second bank region 204B in the Y-direction, and the group of second bank sub-regions 208 of the first bank region 204A may partially (e.g., incompletely) horizontally overlap with the additional group of second bank sub-regions 208 of the second bank region 204B in the X-direction.

The central sub-region 202A of the peripheral circuitry region 202 may be interposed horizontally in the X-direction between the group of first memory sub-regions 206 of the first memory region 204A and the additional group of first memory sub-regions 206 of the second memory region 204B, and may partially (e.g., incompletely) horizontally overlap each of the group of first memory sub-regions 206 of the first memory region 204A and the additional group of first memory sub-regions 206 of the second memory region 204B in the Y-direction. In addition, the center sub-region 202A of the peripheral circuitry region 202 may be horizontally interposed between the group of second memory sub-regions 208 of the first memory region 204A and the additional group of second memory sub-regions 208 of the second memory region 204B in the Y-direction, and may partially (e.g., incompletely) horizontally overlap each of the group of second memory sub-regions 208 of the first memory region 204A and the additional group of second memory sub-regions 208 of the second memory region 204B in the X-direction.

The second arm region 202C of the peripheral circuitry region 202 may be interposed horizontally in the Y-direction between the group of first bank regions 206 of the first bank region 204A and the additional group of second bank regions 208 of the second bank region 204B, and may overlap in the X-direction with the group of first bank regions 206 of the first bank region 204A and the additional group of second bank regions 208 of the second bank region 204B. In addition, the first arm region 202B of the peripheral circuitry region 202 may be interposed horizontally in the Y-direction between the additional group of first memory regions 206 of the second memory region 204B and the group of second memory regions 208 of the first memory region 204A, and may overlap the additional group of first memory regions 206 of the second memory region 204B and the group of second memory regions 208 of the first memory region 204A in the X-direction.

The first and second memory bank sub-regions 206, 208 of the memory bank region 204 (e.g., the first and second memory bank regions 204A, 204B) of the microelectronic device 100 may exhibit rectangular horizontal cross-sectional shapes. Each of the first bank sub-regions 206 may exhibit rectangular horizontal cross-sectional shapes that are substantially identical to each other, and each of the second bank sub-regions 208 may exhibit rectangular horizontal cross-sectional shapes that are substantially identical to each other. The rectangular horizontal cross-sectional shape of each of the first memory bank sub-regions 206 may be different from the rectangular horizontal cross-sectional shape of each of the second memory bank sub-regions 208.

As shown in fig. 2A, each of the first bank sub-regions 206 may have a fourth length L ₄ in the Y-direction and a fourth width W ₄ in the X-direction, and each of the second bank sub-regions 208 may have a fifth length L ₅ in the Y-direction and a fifth width W ₅ in the X-direction. The fourth length L ₄ of each of the first bank sub-regions 206 may be greater than the fifth length L ₅ of each of the second bank sub-regions 208. In some embodiments, the fourth length L ₄ of each of the first bank sub-regions 206 is about twice (2X) the fifth length L ₅ of each of the second bank sub-regions 208. In addition, the fourth width W ₄ of each of the first bank sub-regions 206 may be less than the fifth width W ₅ of each of the second bank sub-regions 208. In some embodiments, the fifth width W ₅ of each of the second bank sub-regions 208 is about twice (2X) the fourth width W ₄ of each of the first bank sub-regions 206.

The bank region 204 (e.g., first bank region 204A, second bank region 204B) may individually include a desired number of first bank sub-regions 206 and a desired number of second bank sub-regions 208. As shown in fig. 2A, in some embodiments, the first bank region 204A includes one (1) group of four (4) first bank subregions 206 and one (1) group of four (4) second bank subregions 208, and the second bank region 204B includes one (1) additional group of four (4) first bank subregions 206 and one (1) additional group of four (4) second bank subregions 208. In additional embodiments, one or more (e.g., each) of the first and second memory regions 204A, 204B includes a different number of first memory sub-regions 206 (e.g., greater than four (4) first memory sub-regions 206, less than four (4) first memory sub-regions 206) and/or a different number of second memory sub-regions 208 (e.g., greater than four (4) second memory sub-regions 208, less than four (4) second memory sub-regions 208). For an individual memory bank region 204, the number of its first memory bank sub-regions 206 may be substantially equal to the number of its second memory bank sub-regions 208, or the number of its first memory bank sub-regions 206 may be different (e.g., less than, greater than) the number of its second memory bank sub-regions 208. In addition, the first and second bank regions 204A, 204B may have substantially the same number of first and second bank sub-regions 206, 208 as each other, or the first and second bank regions 204A, 204B may have different numbers of first and/or second bank sub-regions 206, 208 as each other.

Referring next to fig. 2B, an example arrangement of various circuitry of the control circuitry structure 200 within the horizontal regions of the peripheral circuitry region 202 and the memory bank region 204 of the microelectronic device 100 is depicted. To facilitate an understanding of the drawings and the associated description, not all features of the microelectronic device 100 previously described with reference to fig. 2A are depicted in fig. 2B. However, it will be understood that any features of the microelectronic device 100 described with reference to one or more of fig. 2A-2E are applicable to one or more (e.g., all) of the other of fig. 2A-2E.

As previously described herein, the control circuitry structure 200 may contain relatively more speed critical circuitry and devices within the horizontal area of the peripheral circuitry area 202 of the microelectronic device 100. For example, within the horizontal region of the peripheral circuitry area 202 of the microelectronic device 100, the control circuitry structure 200 may include, but is not limited to, a data I/O and control section 214, an internal clock and timing generator section 216, a Command and Address (CA) section(s) 218, a fuse section(s) 220, a capacitor section 222, a voltage generator section 224, an analog section 226, a data junction section 228, and a package interface section 230. The foregoing sections and their arrangement within the horizontal region of the peripheral circuitry area 202 of the microelectronic device 100 are described in further detail below.

The data I/O and control section 214 of the control circuitry structure 200 may include the data I/O and control circuitry 138 previously described with reference to FIG. 1. As non-limiting examples, the data I/O and control section 214 may include one or more (e.g., each) of a read circuit, a write parallelization, a read training control, an input buffer circuit, an input buffer latch circuit, a DFE circuit, a DIB circuit, a DQ shift circuit, a DQS receiver path circuit, a phase generator circuit, a DCC circuit, a DCRC circuit, a clock and power control circuit, a read control circuit, a data serializer circuit, and a data output buffer circuit. As shown in fig. 2B, the data I/O and control section 214 may be positioned within a horizontal region of the central sub-region 202A of the peripheral circuitry region 202 of the microelectronic device 100. The data I/O and control section 214 may be positioned near the horizontal center of the center sub-zone 202A. In some embodiments, the data I/O and control section 214 is positioned near a horizontal center of the microelectronic device 100 defined by the intersection of a horizontal centerline 210 of the microelectronic device 100 in the Y-direction and an additional horizontal centerline 212 of the microelectronic device 100 in the X-direction. The data I/O and control circuitry 138 (FIG. 1) within a first half of the data I/O and control section 214 (e.g., the half above the horizontal centerline 210) of the control circuitry structure 200 may be used for locating the banks of memory cells of the memory array structure 300 (FIG. 2D) within the horizontal area of the first bank region 204A of the microelectronic device 100, and the data I/O and control circuitry 138 (FIG. 1) and a second half of the data I/O and control section 214 (e.g., the half below the horizontal centerline 210) of the control circuitry structure 200 may be used for locating additional banks of memory cells of the memory array structure 300 (FIG. 2D) within the horizontal area of the second bank region 204B of the microelectronic device 100.

The internal clock and clock generator section 216 of the control circuitry structure 200 may include the internal clock and clock generator circuitry 136 previously described with reference to fig. 1. As non-limiting examples, the internal clock and timing generator section 216 may include one or more (e.g., each) of a DLL differential delay line and delay selection logic circuit, a DLL clock phase interpolator circuit, a DLL output clock comparator circuit, a DLL output circuit, a DLL phase detector circuit, a DLL clock inversion control circuit, a DLL control (coarse and fine control) logic circuit, a DLL bias generator control circuit, a DLL auto-reset block circuit, a DLL enable logic circuit, a bit line dithering circuit, and a Ltree stage circuit. As shown in fig. 2B, the internal clock and timing generator section 216 may also be positioned within a horizontal region of the central sub-region 202A of the peripheral circuitry region 202 of the microelectronic device 100. The internal clock and timing generator section 216 may be positioned near the horizontal center of the center sub-section 202A. In some embodiments, the internal clock and timing generator section 216 is positioned near a horizontal center of the microelectronic device 100 defined by the intersection of the horizontal centerline 210 of the microelectronic device 100 in the Y-direction and the additional horizontal centerline 212 of the microelectronic device 100 in the X-direction. The internal clock and timing generator section 216 may be offset from the data I/O and control section 214 in the X direction. For example, the internal clock and timing generator section 216 may be horizontally positioned to one side of the additional horizontal centerline 212 of the microelectronic device 100 in the X-direction, and the data I/O and control section 214 may be the other side of the additional horizontal centerline 212 of the microelectronic device 100 in the X-direction.

The CA section(s) 218 of the control circuitry structure 200 may include the CA input circuitry 115 and CA decoder circuitry 124 previously described with reference to fig. 1. As non-limiting examples, CA section(s) 218 may include one or more (e.g., each) of a column address buffer circuit, a center driver circuit, epprMode register circuit, pcc control Wck circuit, ecs control circuit, QED shifter circuit, clkgen refresh circuit, column controller circuit, command expander circuit, act pre cntl circuit, and BARArray timer circuit. As shown in fig. 2B, CA section(s) 218 may also be positioned within the horizontal region of the central sub-region 202A of the peripheral circuitry area 202. As a non-limiting example, two (2) CA sections 218 may be positioned within the center sub-region 202A of the peripheral circuitry region 202 at opposite horizontal boundaries of the internal clock and timing generator section 216 in the X-direction. One (1) of the CA sections 218 may be interposed horizontally in the X direction between the data I/O and control section 214 and the internal clock and timing generator section 216, and the other (1) of the CA sections 218 may be interposed horizontally in the X direction between the internal clock and timing generator section 216 and the fuse section 220. As another non-limiting example, the control circuitry structure 200 may include a single (e.g., only one) CA section 218 within a horizontal region of the central sub-region 202A of the peripheral circuitry region 202 of the microelectronic device 100. A single CA section 218 may be positioned horizontally in the X-direction between the data I/O and control section 214 and the internal clock and timing generator section 216, or may be positioned horizontally in the X-direction between the internal clock and timing generator section 216 and the fuse section 220.

Still referring to fig. 2B, the fuse section(s) 220 of the control circuitry structure 200 may include the fuse circuitry 132 (e.g., anti-fuse circuitry) previously described with reference to fig. 1. The fuse section(s) 220 may also be positioned within a horizontal region of the center sub-region 202A of the peripheral circuitry region 202 of the microelectronic device 100. As a non-limiting example, two (2) fuse sections 220 may be positioned within the center sub-region 202A of the peripheral circuitry region 202. One (1) of the fuse sections 220 may be positioned at or near the horizontal boundary of the data I/O and control section 214 and may be interposed horizontally in the X-direction between the data I/O and control section 214 and the first bank sub-region 206 of the first bank region 204A. The other (1) of the fuse sections 220 may be positioned at or near the horizontal boundary of the one (1) of the CA sections 218 adjacent to the internal clock and timing generator section 216, and may be interposed horizontally in the X-direction between the CA section 218 and the first bank sub-region 206 of the second bank region 204B. As another non-limiting example, the control circuitry structure 200 may include a single (e.g., only one) fuse section 220 within a horizontal region of the central sub-region 202A of the peripheral circuitry region 202 of the microelectronic device 100. The single fuse section 220 may be positioned horizontally in the X-direction between the data I/O and control section 214 and the first memory bank sub-region 206 of the first memory bank region 204A, or may be positioned horizontally in the X-direction between one (1) of the CA sections 218 and the first memory bank sub-region 206 of the second memory bank region 204B.

The capacitor section 222 of the control circuitry structure 200 may include circuitry (e.g., capacitors) configured and positioned to assist in powering various devices (e.g., control logic devices, access devices) of the microelectronic device 100. For example, the capacitor section 222 may include capacitors for charge pumps, RC filters, peaking amplifiers, capacitors for AC coupling (e.g., RF amplifier capacitors), capacitors for DC blocking (e.g., DC blocking capacitors), and decoupling capacitors, as well as capacitors for powering one or more control logic devices, such as one or more Digital Signal Acquisition (DSA) devices, one or more ECC devices, one or more voltage generators (e.g., one or more low voltage generators, one or more high voltage generators), one or more command address devices, one or more capacitor structures (e.g., one or more decoupling capacitors), one or more data outputs (e.g., DQL), one or more command address devices, one or more antifuse devices, one or more DLL systems, one or more delay enabling devices (e.g., one or more DQ enabling delay devices), one or more temperature sensors, one or more additional data junctions for importing and exporting data to and from a memory bank, and one or more control logic devices. The capacitors within the capacitor section 222 of the control circuitry structure 200 may be coupled to back-end-of-line (BEOL) structures of the microelectronic device 100.

The capacitor section 222 of the control circuitry structure 200 may also be positioned within the horizontal region of the center sub-region 202A of the peripheral circuitry region 202 of the microelectronic device 100. As a non-limiting example, two (2) capacitor segments 222 may be positioned within the center sub-region 202A of the peripheral circuitry region 202. One (1) of the capacitor sections 222 may be positioned at or near a first horizontal boundary in the Y-direction of the data I/O and control section 214, the internal clock and timing generator section 216, the CA section(s) 218, and the fuse section(s) 220. Another one (1) of the capacitor sections 222 may be positioned at or near the second horizontal boundary of the data I/O and control section 214, the internal clock and timing generator section 216, the CA section(s) 218, and the fuse section(s) 220 in the Y-direction. Two (2) capacitor sections 222 may flank the data I/O and control section 214, the internal clock and timing generator section 216, the CA section(s) 218, and the fuse section(s) 220 in the Y-direction. The capacitor section 222 may overlap horizontally with each of the data I/O and control section 214, the internal clock and timing generator section 216, the CA section(s) 218, and the fuse section(s) 220, respectively, in the X-direction. The capacitor segments 222 may individually extend horizontally in the X-direction across at least a majority (e.g., greater than 50%, greater than or equal to 75%, greater than or equal to 90%, greater than or equal to 95%) of the central sub-region 202A of the peripheral circuitry region 202.

Still referring to fig. 2B, the voltage generator section 224 of the control circuitry structure 200 may include the voltage generator circuitry 134 previously described with reference to fig. 1. The voltage generator section 224 may also be positioned within the horizontal region of the center sub-region 202A of the peripheral circuitry region 202 of the microelectronic device 100. As a non-limiting example, two (2) voltage generator sections 224 may be positioned within the center sub-region 202A of the peripheral circuitry region 202. One (1) of the voltage generator sections 224 may be positioned at or near a horizontal boundary of one (1) of the capacitor sections 222 in the Y-direction, and another (1) of the voltage generator sections 224 may be positioned at or near a horizontal boundary of another (1) of the capacitor sections 222 in the Y-direction. Two (2) voltage generator sections 224 may flank two (2) capacitor sections 222 in the Y-direction. The voltage generator section 224 may horizontally overlap with the capacitor section 222 and each of the data I/O and control section 214, the internal clock and timing generator section 216, the CA section(s) 218, and the fuse section(s) 220, respectively, in the X-direction. The voltage generator sections 224 may individually extend horizontally in the X-direction across at least a majority (e.g., greater than 50%, greater than or equal to 75%, greater than or equal to 90%, greater than or equal to 95%) of the central sub-region 202A of the peripheral circuitry region 202.

The analog section 226 of the control circuitry structure 200 may include one or more of analog temperature distribution circuitry and circuitry configured to act on and/or generate analog voltage signals during use and operation of the microelectronic device 100. As a non-limiting example, the analog section 226 may include one or more circuits (analog temperature distribution circuits) that employ analog components to control one or more temperatures of the microelectronic device 100. Such circuitry may include, for example, a temperature sensor (e.g., thermistor, thermocouple), and an amplifier configured and positioned to amplify the output of the temperature sensor. The amplified signal may be used to control one or more of the heating element and the cooling element to maintain a desired temperature of the microelectronic device 100. As another example, the analog section 226 may include an analog-to-digital conversion (ADC) device and/or a digital-to-analog conversion (DAC) device in operable communication with the data I/O and control circuitry 138 and memory cells of the microelectronic device 100 previously described with reference to fig. 1.

The analog section 226 of the control circuitry structure 200 may be positioned within the horizontal regions of the first and second arm sub-regions 202B, 202C of the peripheral circuitry region 202 of the microelectronic device 100. For example, the peripheral circuitry area 202 may include two (2) analog sections 226 within its horizontal region, with one (1) of the analog sections 226 positioned within the first arm sub-area 202B and another (1) of the analog sections 226 positioned within the second arm sub-area 202C. The analog section 226 within the first arm region 202B may overlap horizontally with the first memory bank region 206 of the second memory bank region 204B in the X-direction, and the analog section 226 within the second arm region 202C may overlap horizontally with the first memory bank region 206 of the first memory bank region 204A in the X-direction. The simulated section 226 within the first arm subregion 202B may extend in the X-direction across at least a majority (e.g., greater than 50%, greater than or equal to 75%, greater than or equal to 90%, greater than or equal to 95%) of the first arm subregion 202B, and the simulated section 226 within the second arm subregion 202C may extend in the X-direction across at least a majority (e.g., greater than 50%, greater than or equal to 75%, greater than or equal to 90%, greater than or equal to 95%) of the second arm subregion 202C. In some embodiments, the analog section 226 at least partially horizontally overlaps the capacitor section 222 of the control circuitry structure 200 in the Y-direction within the horizontal region of the central sub-region 202A of the peripheral circuitry region 202 of the microelectronic device 100.

The data junction section 228 of the control circuitry structure 200 may include Multiplexer (MUX) circuitry configured and operative to select one of a number of input signals and then forward the selected input into a single line. For example, the encapsulation interface section 230 may include row MUX circuitry configured and operative to selectively forward at least one row address signal from an external device to the row address decoder 106 (fig. 1). As another example, the data junction section 228 may include column MUX circuitry configured and operative to selectively forward at least one column address signal from an external device to the column address decoder 104 (fig. 1). As another example, the data junction section 228 may include other MUX circuitry configured and operative to receive the digital data values generated by the I/O logic circuitry 112 (fig. 1) and to generate global data signals from the digital data values.

The data junction section 228 of the control circuitry structure 200 may be positioned within the horizontal regions of the first and second arm regions 202B, 202C of the peripheral circuitry region 202 of the microelectronic device 100. For example, the peripheral circuitry area 202 may include two (2) data junction sections 228 in its horizontal region, with one (1) of the data junction sections 228 positioned within the first arm sub-area 202B and the other (1) of the data junction sections 228 positioned within the second arm sub-area 202C. The data junction sections 228 may be interposed horizontally in the Y-direction between one of the analog sections 226 of the control circuitry structure 200 and one of the memory bank regions 204 of the microelectronic device 100, respectively. For example, the data junction section 228 within the first arm subregion 202B may be interposed horizontally in the Y-direction between the analog section 226 within the first arm subregion 202B and the second bank subregion 208 of the first bank region 204A, and the data junction section 228 within the second arm subregion 202C may be interposed horizontally in the Y-direction between the analog section 226 within the second arm subregion 202C and the second bank subregion 208 of the second bank region 204B. The data junction section 228 within the first arm region 202B may overlap the first memory bank region 206 of the second memory bank region 204B horizontally in the X-direction, and the data junction section 228 within the second arm region 202C may overlap the first memory bank region 206 of the first memory bank region 204A horizontally in the X-direction. The data junction section 228 within the first arm subregion 202B may extend in the X-direction across at least a majority (e.g., greater than 50%, greater than or equal to 75%, greater than or equal to 90%, greater than or equal to 95%) of the first arm subregion 202B, and the data junction section 228 within the second arm subregion 202C may extend in the X-direction across at least a majority (e.g., greater than 50%, greater than or equal to 75%, greater than or equal to 90%, greater than or equal to 95%) of the second arm subregion 202C. In some embodiments, the data junction section 228 at least partially horizontally overlaps the voltage generator section 224 of the control circuitry structure 200 in the Y-direction within the horizontal region of the central sub-region 202A of the peripheral circuitry region 202 of the microelectronic device 100.

The package interface section 230 of the control circuitry structure 200 includes structure and circuitry configured to facilitate electrical communication between the microelectronic device 100 and a relatively large device package including the microelectronic device 100. For example, the package interface section 230 may include BEOL structures (e.g., pad structures such as bond pads; conductive wiring) that are in electrical communication with circuitry of the microelectronic device 100 and are configured to interface with additional structures (e.g., wiring) that are in electrical communication with circuitry external to the microelectronic device 100.

The package interface section 230 of the control circuitry structure 200 may be positioned within the horizontal regions of the first and second arm regions 202B, 202C of the peripheral circuitry region 202 of the microelectronic device 100. For example, the peripheral circuitry area 202 may include two (2) package interface sections 230 in its horizontal region, with one (1) of the package interface sections 230 positioned within the first arm section 202B and the other (1) of the package interface sections 230 positioned within the second arm section 202C. The package interface section 230 may be interposed horizontally between one of the analog sections 226 and one of the memory bank regions 204, respectively, along the Y-direction. For example, the package interface section 230 within the first arm sub-region 202B may be interposed horizontally in the Y-direction between the analog section 226 within the first arm sub-region 202B and the first bank sub-region 206 of the second bank region 204B, and the package interface section 230 within the second arm sub-region 202C may be interposed horizontally in the Y-direction between the analog section 226 within the second arm sub-region 202C and the first bank sub-region 206 of the first bank region 204A. The package interface section 230 within the first arm region 202B may overlap the first memory bank region 206 of the second memory bank region 204B horizontally in the X-direction, and the package interface section 230 within the second arm region 202C may overlap the first memory bank region 206 of the first memory bank region 204A horizontally in the X-direction. The encapsulation interface section 230 within the first arm sub-region 202B may extend in the X-direction across at least a majority (e.g., greater than 50%, greater than or equal to 75%, greater than or equal to 90%, greater than or equal to 95%) of the first arm sub-region 202B, and the encapsulation interface section 230 within the second arm sub-region 202C may extend in the X-direction across at least a majority (e.g., greater than 50%, greater than or equal to 75%, greater than or equal to 90%, greater than or equal to 95%) of the second arm sub-region 202C.

Within the horizontal region of the respective first bank sub-region 206 of the microelectronic device 100, the control circuitry structure 200 may include a transistor array section 232, a column decoder section 234, a column decoder section 236, a control logic device section 238, and a bank logic section 240. Within the individual first bank sub-regions 206, the row decoder section 234 may be horizontally adjacent to the transistor array section 232 in the X-direction. The row decoder sections 234 within some groups of two (2) of the first bank sub-regions 206 that are horizontally adjacent to each other in the X-direction may be positioned proximate to each other (e.g., substantially "back-to-back") in the X-direction such that the transistor array sections 232 of some groups of two (2) of the first bank sub-regions 206 are not interposed horizontally in the X-direction between the row decoder sections 234. The row decoder sections 234 within some other groups of two (2) of the first bank sub-regions 206 that are horizontally adjacent to each other in the X-direction may be positioned farther away from each other in the X-direction such that the transistor array sections 232 of some other groups of two (2) of the first bank sub-regions 206 are horizontally interposed between the row decoder sections 234 in the X-direction. Additionally, within the respective first bank sub-regions 206, transistor array sections 232 and row decoder sections 234 may be interposed horizontally in the Y-direction between a first one of the column decoder sections 236 and a second one of the column decoder sections 236. A first one of the column decoder sections 236 may be positioned at or near a first end of the transistor array section 232 in the Y-direction, and a second one of the column decoder sections 236 may be positioned at or near a second end of the transistor array section 232 in the Y-direction. A second one of the column decoder sections 236 may be interposed horizontally in the Y-direction between the control logic device section 238 and each of the transistor array section 232 and the row decoder section 234. Further, the control logic device section 238 may be interposed horizontally in the Y-direction between the column decoder section 236 and the bank logic section 240, and the bank logic section 240 may be interposed horizontally in the Y-direction between the control logic device section 238 and one (1) of the first and second arm regions 202B, 202C of the peripheral circuitry region 202 of the microelectronic device 100.

The transistor array section 232 of the control circuitry structure 200 within the horizontal region of the respective first memory bank sub-region 206 of the microelectronic device 100 may include a plurality of patch sub-sections of the microelectronic device 100 within its horizontal region. Within the horizontal region of the individual patch sub-regions, the control circuitry structure 200 may include various control logic circuitry (e.g., sense Amplifier (SA) circuitry, decoder circuitry, such as column decoder circuitry, word line driver circuitry, such as main word line driver (MWD) circuitry and sub-word line driver (SWD) circuitry). A non-limiting example of the configuration of the control circuitry structure 200 within the horizontal region of an individual patch sub-section of the microelectronic device 100 is described in further detail below with reference to fig. 2C.

The row decoder section 234 of the control circuitry structure 200 within the horizontal region of the respective first bank sub-region 206 of the microelectronic device 100 may include row decoder circuitry configured for implementing at least some row operations on banks of memory cells underlying the memory array structure 300 (fig. 2D) of the control circuitry structure 200. The memory banks of memory cells may be located within a horizontal region of the first bank sub-region 206 of the microelectronic device 100, as described in further detail below with reference to fig. 2D. As shown in fig. 2B, the row decoder section 234 within the first bank sub-region 206 may extend horizontally in the Y-direction across at least a majority (e.g., greater than 50%, greater than or equal to 75%, greater than or equal to 90%, greater than or equal to 95%) of each of the transistor array sections 232 of the first bank sub-region 206. The horizontal position of the row decoder section 234 within each first bank sub-region 206 in the X-direction may facilitate a Main Word Line (MWL) length in the X-direction within each first bank sub-region 206 that is substantially equal to the MWL length in the X-direction within each second bank sub-region 208 (described in further detail below). The consistent MWL length within the first and second bank sub-regions 206, 208 may facilitate, but is not limited to, driver size consistency, RC consistency, and timing consistency for the first and second bank sub-regions 206, 208 even though the first bank sub-region 206 has a different horizontal geometric configuration (e.g., different horizontal dimensions in the X-direction and Y-direction) than the second bank sub-region 208.

The column decoder sections 236 of the control circuitry structure 200 within the horizontal region of the respective first bank sub-regions 206 of the microelectronic device 100 may individually include column decoder circuitry configured for implementing at least some column operations on banks of memory cells within the memory array structure 300 (fig. 2D) underlying the control circuitry structure 200. As shown in fig. 2B, the column decoder section 236 within the first bank sub-region 206 may be horizontally positioned at or near opposite horizontal ends of the transistor array section 232 and the row decoder section 234 along the Y-direction. Each first bank sub-region 206 may include two (2) column decoder sections 236. One (1) of the two (2) column decoder sections 236 may be positioned at or near a first horizontal end of the transistor array section 232 and the row decoder section 234 in the Y-direction, and one (1) other of the two (2) column decoder sections 236 may be positioned at or near a second horizontal end of the transistor array section 232 and the row decoder section 234 in the Y-direction. The column decoder segment 236 may individually extend horizontally in the X-direction across at least a majority (e.g., greater than 50%, greater than or equal to 75%, greater than or equal to 90%, greater than or equal to 95%) of the total horizontal dimension (e.g., the total width in the X-direction) of the combination of the transistor array segment 232 and the row decoder segment 234 within the first bank sub-region 206. The number and horizontal position of column decoder segments 236 within each first bank sub-region 206 in the Y-direction may facilitate Column Select (CS) line lengths and main input/output (MIO) line lengths in the Y-direction within each first bank sub-region 206 that are substantially equal to CS line lengths and MIO line lengths in the Y-direction within each second bank sub-region 208. The uniform CS line length and the uniform MIO line length within the first and second memory bank sub-regions 206, 208 may facilitate, but are not limited to, driver size uniformity, RC uniformity, and timing uniformity within the first and second memory bank sub-regions 206, 208 even though the first memory bank sub-region 206 has a different horizontal geometric configuration (e.g., different horizontal dimensions in the X and Y directions) than the second memory bank sub-region 208.

The control logic device section 238 of the control circuitry structure 200 within the horizontal region of the respective first memory bank sub-region 206 of the microelectronic device 100 may include various control logic circuitry for the microelectronic device 100, including, but not limited to, DSA circuitry and ECC circuitry. In some embodiments, the control logic device section 238 within the respective first bank sub-region 206 includes both ECC circuitry and DSA circuitry for performing associated operations on banks of memory cells within the memory array structure 300 (FIG. 2D) underlying the control circuitry structure 200. The banks of memory cells may be located within a horizontal region of the first bank sub-region 206 of the microelectronic device 100. In additional embodiments, the control logic device section 238 includes additional control logic circuitry, such as one or more of repair circuitry (e.g., column repair circuitry, row repair circuitry), I/O devices (e.g., local I/O devices), test devices, MUX devices, self-refresh/wear-leveling devices, redundant fuse and logic (DFM) devices, and DFT devices. As shown in fig. 2B, control logic device sections 238 within the horizontal region of the individual first bank sub-sections 206 may be positioned horizontally in the Y-direction at or near the horizontal end of one of the column decoder sections 236. The control logic device section 238 may extend horizontally in the X-direction across at least a majority (e.g., greater than 50%, greater than or equal to 75%, greater than or equal to 90%, greater than or equal to 95%) of the column decoder section 236.

The bank logic section 240 of the control circuitry structure 200 within the horizontal region of the respective first bank sub-section 206 of the microelectronic device 100 may include additional control logic circuitry for implementing the operation of the control logic circuitry of the transistor array section 232, the row decoder section 234, and the column decoder section 236 within the first bank sub-section 206. As shown in fig. 2B, the bank logic section 240 within the first bank sub-region 206 may be horizontally positioned at or near the horizontal end of the control logic device section 238 in the Y-direction. The bank logic section 240 may extend horizontally in the X-direction across at least a majority (e.g., greater than 50%, greater than or equal to 75%, greater than or equal to 90%, greater than or equal to 95%) of the control logic device section 238 (and thus the column decoder section 236).

Still referring to fig. 2B, within the horizontal region of the respective second bank sub-region 208 of the microelectronic device 100, the control circuitry structure 200 may include an additional transistor array section 242, an additional column decoder section 244, an additional row decoder section 246, an additional control logic device section 248, and an additional bank logic section 250. Within the respective second bank sub-regions 208, additional row decoder sections 244 may be interposed horizontally in the X-direction between two (2) additional transistor array sections 242. In addition, within the respective second bank sub-regions 208, additional row decoder segments 246 may be interposed horizontally in the Y-direction between additional control logic device segments 248 and each of the additional transistor array segments 242 and the additional column decoder segments 244, additional control logic device segments 248 may be interposed horizontally in the Y-direction between additional row decoder segments 246 and additional bank logic segments 250, and additional bank logic segments 250 may be interposed horizontally in the Y-direction between additional control logic device segments 248 and one of the first and second arm sub-regions 202B, 202C of the peripheral circuitry region 202 of the microelectronic device 100.

The additional transistor array segments 242 of the control circuitry structure 200 within the horizontal region of the respective second memory bank sub-regions 208 of the microelectronic device 100 may include a first additional transistor array segment 242A and a second additional transistor array segment 242B horizontally offset from the first additional transistor array segment 242A in the X-direction. The first and second additional transistor array segments 242A, 242B may exhibit substantially the same horizontal dimensions (e.g., length in the Y direction, width in the X direction) as each other, and substantially the same horizontal cross-sectional shape as each other. The length (e.g., first horizontal dimension) of each of the additional transistor array sections 242 of the respective second bank sub-regions 208 in the Y-direction may be relatively smaller than the length (e.g., first horizontal dimension) of the transistor array section 232 within the horizontal region of the respective first bank sub-region 206 in the Y-direction. In some embodiments, each of the additional transistor array segments 242 has a length in the Y-direction that is less than or equal to about half (1/2) of the length of the transistor array segment 232 in the Y-direction. In addition, the width (e.g., second horizontal dimension) in the X-direction of each of the additional transistor array sections 242 of the respective second memory bank sub-regions 208 may be substantially equal to the width (e.g., second horizontal dimension) in the X-direction of the transistor array sections 232 within the horizontal region of the respective first memory bank sub-regions 206. The additional transistor array section 242 may individually include a plurality of patch subsections of the microelectronic device 100 within its horizontal region. As previously mentioned, within the horizontal region of the individual patch subsections, the control circuitry structure 200 may include various control logic circuitry (e.g., SA circuitry, decoder circuitry, such as column decoder circuitry, word line driver circuitry, such as MWD circuitry and SWD circuitry). A non-limiting example of the configuration of the control circuitry structure 200 within the horizontal region of an individual patch sub-section of the microelectronic device 100 is described in further detail below with reference to fig. 2C. In some embodiments, the respective additional transistor array section 242 within the respective second memory bank sub-region 208 has about half (1/2) as many patch sub-regions in the Y-direction as the transistor array section 232 within the respective first memory bank sub-region 206, and about the same number of patch sub-regions in the X-direction as the transistor array section 232 within the first memory bank sub-region 206.

The additional row decoder section 244 within the horizontal region of the respective second bank sub-region 208 of the microelectronic device 100 can include additional row decoder circuitry configured for implementing at least some row operations on additional banks of memory cells within the memory array structure 300 (fig. 2D) underlying the control circuitry structure 200. Additional banks of memory cells may be located within the horizontal region of the second bank sub-region 208 of the microelectronic device 100, as described in further detail below with reference to fig. 2D. In some embodiments, the additional row decoder sections 244 within the respective second bank sub-regions 208 have a length (e.g., a first horizontal dimension) in the Y-direction that is less than or equal to about half (1/2) of the length (e.g., the first horizontal dimension) of the row decoder sections 234 within one (1) of the first bank sub-regions 206 in the Y-direction. As shown in fig. 2B, additional row decoder sections 244 within individual second bank sub-regions 208 may extend horizontally in the Y-direction across at least a majority (e.g., greater than 50%, greater than or equal to 75%, greater than or equal to 90%, greater than or equal to 95%) of each of the additional transistor array sections 242 of the second bank sub-regions 208.

The additional column decoder section 246 within the horizontal region of the respective second bank sub-region 208 of the microelectronic device 100 can include additional column decoder circuitry configured for implementing at least some column operations on additional banks of memory cells within the memory array structure 300 (fig. 2D) underlying the control circuitry structure 200. In some embodiments, the additional column decoder sections 246 within the respective second bank sub-regions 208 have a width (e.g., a second horizontal dimension) in the X-direction that is greater than or equal to about twice (2) the width (e.g., a second horizontal dimension) of one (1) of the column decoder sections 236 within one (1) of the first bank sub-regions 206 in the X-direction. As shown in fig. 2B, additional column decoder sections 246 within individual bank sub-regions 208 may be positioned horizontally in the Y-direction at or near the horizontal ends of additional transistor array sections 242 and additional row decoder sections 244. The additional column decoder segment 246 may extend horizontally in the X-direction across at least a majority (e.g., greater than 50%, greater than or equal to 75%, greater than or equal to 90%, greater than or equal to 95%) of the total horizontal dimension (e.g., the total width in the X-direction) of the combination of the additional transistor array segment 242 and the additional row decoder segment 244 within the second bank sub-region 208.

The additional control logic device section 248 within the horizontal region of the respective second memory subregion 208 of the microelectronic device 100 can include various control logic circuitry for the microelectronic device 100 including, but not limited to, the control logic circuitry previously described herein in relation to the control logic device section 238 within the respective first memory subregion 206. In some embodiments, the additional control logic device section 248 within the respective second bank sub-section 208 includes at least one ECC device and at least one DSA device for correlating additional banks of memory cells within the memory array structure 300 (FIG. 2D) underlying the control circuitry structure 200. Additional banks of memory cells may be located within the horizontal region of the second bank sub-region 208. The additional control logic device segments 248 within the respective second bank sub-regions 208 may have a width (e.g., a second horizontal dimension) in the X-direction that is greater than or equal to about twice (2) the width (e.g., a second horizontal dimension) of the control logic device segments 238 of one (1) of the first bank sub-regions 206 in the X-direction. As shown in fig. 2B, additional control logic device sections 248 within individual second bank sub-sections 208 may be positioned horizontally in the Y-direction at or near the horizontal ends of additional column decoder sections 246. The additional control logic device section 248 may extend horizontally in the X-direction across at least a majority (e.g., greater than 50%, greater than or equal to 75%, greater than or equal to 90%, greater than or equal to 95%) of the additional column decoder section 246.

The additional bank logic section 250 within the horizontal region of the respective second bank sub-section 208 of the microelectronic device 100 may include additional control logic circuitry for implementing the operation of the control logic circuitry of the additional transistor array section 242, the additional column decoder section 244, and the additional row decoder section 246 of the first bank sub-section 206. The additional bank logic sections 250 within the respective second bank sub-regions 208 may have a width (e.g., a second horizontal dimension) in the X-direction that is greater than or equal to about twice (2) the width (e.g., a second horizontal dimension) of the bank logic sections 240 of one (1) of the first bank sub-regions 206 in the X-direction. As shown in fig. 2B, additional bank logic sections 250 within individual second bank sub-regions 208 may be positioned horizontally in the Y-direction at or near the horizontal ends of additional control logic device sections 248. The additional bank logic section 250 may extend horizontally in the X-direction across at least a majority (e.g., greater than 50%, greater than or equal to 75%, greater than or equal to 90%, greater than or equal to 95%) of the additional control logic device section 248 (and thus the additional column decoder section 246).

As previously mentioned, fig. 2C is a simplified schematic view of portion a (illustrated with a dashed box in fig. 2B) of the control circuitry structure 200 of the microelectronic device 100, in accordance with an embodiment of the disclosure. Section a illustrates the configuration of the control circuitry structure 200 within the horizontal region of the patch subsection 252 of the microelectronic device 100. The patch subsections 252 may be positioned within a horizontal region of one (1) of the second bank subsections 208 of one of the bank regions 204 of the control circuitry structure 200 (e.g., the first bank region 204A). Each of the second bank sub-regions 208 of the control circuitry structure 200 (fig. 2B) may include multiple (e.g., a group, multiple (a) of patch sub-sections 252) within its horizontal region, and the control circuitry structure 200 may exhibit a configuration similar to that shown in fig. 2C within the horizontal region of each patch sub-section 252. In addition, within the horizontal region of the individual first memory bank sub-regions 206 (fig. 2B) of the microelectronic device 100, the control circuitry structure 200 may include multiple (e.g., a group, multiple (a-multiple)) patch sub-sections 252, and the control circuitry structure 200 may exhibit a configuration similar to that shown in fig. 2C within the horizontal region of each patch sub-section 252.

Within the horizontal area of each patch subsection 252 of the microelectronic device 100, the control circuitry structure 200 is substantially free of memory cells. Instead, the memory cells of the microelectronic device 100 are contained (e.g., defined) within a memory array structure 300 (fig. 2D) of the microelectronic device 100, the memory array structure 300 being vertically offset from (e.g., vertically underlying) the control circuitry structure 200.

Each patch subsection 252 of the microelectronic device 100 may include an array region 254, a digit line outlet region 256 (also referred to as a "digit line contact receptacle region") interposed between pairs of array regions 254 horizontally adjacent to each other along a Y-direction, and a word line outlet region 258 (also referred to as a "word line contact receptacle region") interposed between pairs of array regions 254 horizontally adjacent to each other along an X-direction orthogonal to the Y-direction. The array region 254, the digit line outlet region 256, and the word line outlet region 258 within the individual patch subsections 252 of the microelectronic device 100 are described in further detail below.

The array region 254 of the microelectronic device 100 may include a horizontal region of the microelectronic device 100 having an array of memory cells (e.g., an array of DRAM cells) within its horizontal boundaries. The memory cell array may be vertically positioned within the memory array structure 300 (fig. 2D) of the microelectronic device 100. In addition, the array region 254 may also have a desired arrangement of control logic devices within its horizontal boundaries. The control logic device may be vertically positioned to be formed within the horizontal boundaries of the array region 254 within the control circuitry structure 200 (fig. 2B) of the microelectronic device 100.

Individual patch subsections 252 of the microelectronic device 100 may be formed to include a desired number of array regions 254. For clarity and ease of understanding of the drawings and related description, fig. 2C depicts individual patch subsections 252 as including four (4) array regions 254, a first array region 254A, a second array region 254B, a third array region 254C, and a fourth array region 254D. As shown in fig. 2C, the second array region 254B may be horizontally adjacent to the first array region 254A in the Y-direction and may be horizontally adjacent to the fourth array region 254D in the X-direction, the third array region 254C may be horizontally adjacent to the first array region 254A in the X-direction and may be horizontally adjacent to the fourth array region 254D in the Y-direction, and the fourth array region 254D may be horizontally adjacent to the third array region 254C in the Y-direction and may be horizontally adjacent to the second array region 254B in the Y-direction. In additional embodiments, individual patch subsections 252 include different numbers of array regions 254. For example, patch subsections 252 may include more than four (4) array regions 254 or less than four (4) array regions 254.

In addition, individual patch subsections 252 of the microelectronic device 100 may include a desired distribution of array regions 254. As shown in fig. 2C, in some embodiments, the microelectronic device 100 is formed to include rows of array regions 254 extending in the X-direction and columns of array regions 254 extending in the Y-direction. The rows of array regions 254 may, for example, include a first row including a first array region 254A and a third array region 254C, and a second row including a second array region 254B and a fourth array region 254D. The columns of the array region 254 may, for example, include a first column including a first array region 254A and a second array region 254B, and a second column including a third array region 254C and a fourth array region 254D.

With continued reference to fig. 2C, the digit line exit region 256 of the microelectronic device 100 can include a horizontal region of the microelectronic device 100 configured and positioned to have at least some digit lines (e.g., bit lines, data lines) horizontally terminating therein. For individual digit line exit regions 256, at least some of the formed digit lines that are located laterally (e.g., at opposite boundaries in the Y-direction) of digit line exit region 256 that are operatively associated with array region 254 may have ends within the horizontal boundaries of digit line exit region 256. In addition, digit line exit region 256 may also be configured and positioned to include contact structures and routing structures whose horizontal boundaries are operatively associated with at least some of the digit lines. Some of the contact structures within the digit line exit region 256 may couple the digit lines to control logic circuitry of control logic devices (e.g., SA devices) within the horizontal region of the array region 254. As shown in fig. 2C, in some embodiments, the digit line exit regions 256 extend horizontally in the X-direction and are interposed horizontally in the Y-direction between horizontally adjacent rows of the array region 254. The digit line exit regions 256 may alternate horizontally with rows of the array region 254, for example, in the Y-direction.

Individual digit line exit regions 256 may be divided into a plurality of sub-regions. For example, as shown in fig. 1, the individual digit line outlet regions 256 may include a first digit line outlet sub-region 256A and a second digit line outlet sub-region 256B. In some embodiments, the first digit line outlet sub-section 256A horizontally alternates with the second digit line outlet sub-section 256B in the X-direction. A pair (e.g., two (2)) of horizontally adjacent array regions 254 within a respective column of array regions 254 may include one (1) of first digit line outlet sub-regions 256A and one (1) of second digit line outlet sub-regions 256B positioned horizontally therebetween along the Y-direction. As a non-limiting example, the first array region 254A and the second array region 254B of the first column of array regions 254 may include one (1) of the first digit line outlet subregion 256A and one (1) of the second digit line outlet subregion 256B positioned horizontally therebetween along the Y-direction. The one (1) of the first digit line outlet sub-region 256A and the one (1) of the second digit line outlet sub-region 256B may be at least partially (e.g., substantially) defined by horizontal boundaries of the first array region 254A and the second array region 254B in the X-direction.

The individual first digit line outlet sub-regions 256A may be configured and positioned to facilitate electrical connection between groups of digit lines (e.g., odd digit lines or even digit lines) within the memory array structure 300 (fig. 2D) and groups of control logic devices (e.g., odd or even SA devices) within the control circuitry structure 200 (fig. 2B), operatively associated with a portion (e.g., half in the X-direction) of one (1) of the pair of horizontally adjacent array regions 254 (e.g., the first array region 254A). The first digit line outlet sub-region 256A may also be configured and positioned to facilitate electrical connection between a group of additional digit lines (e.g., additional odd digit lines or additional even digit lines) within the memory array structure 300 (fig. 2D) and a group of additional control logic devices (e.g., additional odd SA devices or additional even SA devices) within the control circuitry structure 200 (fig. 2B), operatively associated with corresponding portions (corresponding halves in the X-direction) of additional array regions 254 (e.g., second array region 254B) in the pair of horizontally adjacent arrays 254. In addition, the individual second digit line outlet sub-regions 256B may be configured and positioned to facilitate electrical connection between groups of further digit lines within the memory array structure 300 (fig. 2D) and groups of further control logic devices within the control circuitry structure 200 (fig. 2B) operably associated with another portion (e.g., another half portion in the X-direction) of the one (1) array regions 254 (e.g., the first array region 254A). The second digit line outlet sub-region 256B may also be configured and positioned and also facilitate electrical connection between a group of yet further digit lines within the memory array structure 300 (fig. 2D) and a group of yet further control logic devices within the control circuitry structure 200 (fig. 2B), operatively associated with a corresponding other portion (e.g., a corresponding other half portion in the X-direction) of the additional array region 254 (e.g., the second array region 254B).

Still referring to fig. 2C, the wordline outlet region 258 of the microelectronic device 100 may include a horizontal region of the microelectronic device 100 configured and positioned to have at least some wordlines (e.g., access lines) horizontally terminating therein. For individual word line outlet regions 258, at least some of the word lines located laterally (e.g., at opposite boundaries in the X-direction) of the word line outlet regions 258 that are operatively associated with the array region 254 may have ends within the horizontal boundaries of the word line outlet regions 258. In addition, the word line outlet region 258 may also be configured and positioned to include contact structures and routing structures within its horizontal boundaries that are operatively associated with the word lines. Some of the contact structures within the word line exit region 258 may couple the word lines to control logic circuitry of additional control logic devices (e.g., SWD devices) within the horizontal region of the array region 254. As shown in fig. 2C, in some embodiments, the word line outlet regions 258 extend horizontally in the Y-direction and are interposed horizontally in the X-direction between horizontally adjacent columns of the array region 254. The word line outlet regions 258 may alternate horizontally with columns of the array region 254, for example, in the X-direction.

Individual word line outlet regions 258 may be divided into a plurality of sub-regions. For example, as shown in fig. 1, the individual word line outlet regions 258 may include a first word line outlet sub-region 258A and a second word line outlet sub-region 258B. In some embodiments, the first word line outlet sub-region 258A horizontally alternates with the second word line outlet sub-region 258B in the Y-direction. A pair (e.g., two (2)) of horizontally adjacent array regions 254 within a respective row of array regions 254 may include one (1) of the first wordline outlet subregion 258A and one (1) of the second wordline outlet subregion 258B positioned horizontally therebetween along the X-direction. As a non-limiting example, the first array region 254A and the third array region 254C of the first row of array regions 254 may include one (1) of the first wordline outlet sub-region 258A and one (1) of the second wordline outlet sub-region 258B positioned therebetween along the X-direction. The one (1) of the first wordline outlet subregion 258A and the one (1) of the second wordline outlet subregion 258B may be at least partially (e.g., substantially) defined by horizontal boundaries of the first array region 254A and the third array region 254C in the Y-direction.

The individual first word line outlet sub-regions 258A may be configured and positioned to facilitate electrical connection between groups of word lines (e.g., odd word lines or even word lines) within the memory array structure 300 (fig. 2D) and groups of control logic devices (e.g., odd SWD devices or even SWD devices) within the control circuitry structure 200 (fig. 2B), operatively associated with a portion (e.g., half in the Y-direction) of one (1) array region 254 (e.g., first array region 254A) of a pair of horizontally adjacent array regions 254. The first word line outlet sub-region 258A may also facilitate electrical connection between a group of additional word lines (e.g., additional odd word lines or additional even word lines) within the memory array structure 300 (fig. 2D) and a group of additional control logic devices (e.g., additional odd SWD devices or additional even SWD devices) within the control circuitry structure 200 (fig. 2B), operatively associated with corresponding portions (e.g., corresponding half portions in the Y-direction) of further array regions 254 (e.g., third array region 254C) of the pair of horizontally adjacent array regions 254. In addition, the individual second word line outlet sub-regions 258B may be configured and positioned to facilitate electrical connection between groups of further word lines within the memory array structure 300 (fig. 2D) and groups of further control logic devices within the control circuitry structure 200 (fig. 2B), operatively associated with another portion (e.g., another half portion in the Y-direction) of the one (1) array regions 254 (e.g., the first array region 254A). The second word line outlet sub-region 258B may also facilitate electrical connection between a group of yet further word lines within the memory array structure 300 (fig. 2D) and a group of yet further control logic devices within the control circuitry structure 200 (fig. 2B), operatively associated with a corresponding other portion (e.g., a corresponding other half portion in the Y-direction) of the further array region 254 (e.g., the third array region 254C).

Still referring to fig. 2C, the control circuitry structure 200 of the microelectronic device 100 may include a desired arrangement of SA sections 260 and SWD sections 262 within the horizontal area of each array region 254 of the individual patch subsections 252 of the microelectronic device 100. The SA section 260 of the control circuitry structure 200 may individually include SA devices coupled to digit lines positioned within the memory array structure 300 (FIG. 2D) of the microelectronic device 100. The digit lines may be vertically underlying (e.g., in the Z-direction) the SA devices of the SA section 260 of the control circuitry structure 200. SWD section 262 may include SWD devices coupled to word lines positioned within memory array structure 300 (fig. 2D) of microelectronic device 100. The word lines may be vertically underlying (e.g., in the Z-direction) SWD devices that control SWD sections 262 of circuitry structure 200.

The SA sections 260 within the horizontal area of the individual array regions 254 (e.g., the first array region 254A, the second array region 254B, the third array region 254C, or the fourth array region 254D) of the microelectronic device 100 may include a first SA section 260A and a second SA section 260B. The respective first SA sections 260A and the respective second SA sections 260B of the control circuitry structure 200 within the horizontal region of the respective array region 254 of the microelectronic device 100 may be positioned at or near corners (e.g., diagonal corners) of the array region 254 opposite each other. For example, as shown in fig. 2C, for an individual array region 254, a first SA section 260A may be positioned at or near a first corner 264A of the array region 254, and a second SA section 260B may be positioned at or near a second corner 264B of the array region 254, the second corner 264B being positioned diagonally opposite (e.g., a small corner) from the first corner 264A.

For each SA section 260 (e.g., first SA section 260A, second SA section 260B) of the control circuitry structure 200 within the horizontal region of the individual array region 254 of the microelectronic device 100, the SA devices of the SA section 260 may be coupled to a group of digit lines extending horizontally (e.g., in the Y-direction) through the array region 254 within the memory array structure 300 (FIG. 2D) by a digit line routing and contact structure 266.

For individual patch subsections 252 of the microelectronic device 100, SA devices of the SA sections 260 within array regions 254 (e.g., first and second array regions 254A, 254B; third and fourth array regions 254C, 254D) of the control circuitry structure 200 that are horizontally adjacent to each other in the Y-direction may be coupled to different digit line groups from each other. For example, each of the SA sections 260 (e.g., each of the first SA section 260A and the second SA section 260B) of the control circuitry structure 200 within the first array region 254A may include a so-called "even" SA device coupled to an even digit line within the memory array structure 300 (FIG. 2D) by a digit line routing and contact structure 266 associated with the SA section 260, and each of the SA sections 260 (e.g., each of the first SA section 260A and the second SA section 260B) of the control circuitry structure 200 within the second array region 254B may include a so-called "odd" SA device coupled to an odd digit line within the memory array structure 300 (FIG. 2D) by a digit line routing and contact structure 266 associated with the SA section 260, or vice versa. The even numbered digit lines of the memory array structure 300 (fig. 2D) may alternate horizontally in the X-direction with the odd numbered digit lines of the memory array structure 300 (fig. 2D). The SA devices of each of the SA sections 260 of the control circuitry structure 200 within the horizontal region of the first array region 254A may not be coupled to any odd digit lines of the memory array structure 300 (FIG. 2D), and the SA devices of each of the SA sections 260 of the control circuitry structure 200 within the horizontal region of the second array region 254B may not be coupled to any even digit lines of the memory array structure 300 (FIG. 2D), or vice versa. Similarly, each of the SA sections 260 within the third array region 254C horizontally adjacent to the first array region 254A in the X direction (e.g., each of the first SA section 260A and the second SA section 260B) may include additional even SA devices coupled to additional even digit lines within the memory array structure 300 (FIG. 2D) by digit line routing and contact structures 266 associated with the SA sections 260, and each of the SA sections 260 within the horizontal region of the fourth array region 254D horizontally adjacent to the second array region 254B in the X direction (e.g., each of the first SA section 260A and the second SA section 260B) may include additional odd number devices coupled to additional odd digit lines within the memory array structure 300 (FIG. 2D) by digit line routing and contact structures 266 associated with the SA sections 260, or vice versa.

As shown in fig. 2C, SA devices (e.g., odd or even SA devices) within individual SA sections 260 of individual array regions 254 may be coupled to digit lines (e.g., odd or even digit lines) extending horizontally through an array region 254, and may also be coupled to additional digit lines (e.g., additional odd or additional even digit lines) extending horizontally through another array region 254 horizontally adjacent to the array region 254 in the Y-direction. For example, some odd SA devices within the first SA section 260A of the second array region 254B may be coupled to odd digit lines extending horizontally through the second array region 254B by some digit line routing and contact structures 266 extending to and through the first digit line outlet sub-region 256A horizontally adjacent to the second array region 254B in the Y direction, and some additional odd SA devices within the first SA section 260A of the second array region 254B may be coupled to additional odd digit lines extending horizontally through the first array region 254A by some additional digit line routing and contact structures 266 extending to and through the first digit line outlet sub-region 256A. As another example, some even SA devices within the second SA section 260B of the first array region 254A may be coupled to even digit lines extending horizontally through the first array region 254A by some digit line routing and contact structures 266 extending to and through the second digit line outlet sub-region 256B horizontally adjacent to the first array region 254A in the Y-direction, and some additional even SA devices within the second SA section 260B of the first array region 254A may be coupled to additional even digit lines extending horizontally through the second array region 254B by some additional digit line routing and contact structures 266 extending to and through the second digit line outlet sub-region 256B.

With continued reference to fig. 2C, SWD sections 262 within the horizontal area of the individual array regions 254 (e.g., first array region 254A, second array region 254B, third array region 254C, or fourth array region 254D) of the microelectronic device 100 may include a first SWD section 262A and a second SWD section 262B. The respective first SWD sections 262A and the respective second SWD sections 262B of the control circuitry structure 200 within the horizontal region of the respective array region 254 of the microelectronic device 100 may be positioned at or near different corners of the array region 254 than the first and second SA sections 260A and 260B. In addition, the corners of the array region 254 associated with the first SWD section 262A may be opposite (e.g., diagonally opposite) the corners of the array region 254 associated with the second SWD section 262B. For example, as shown in fig. 2C, for an individual array region 254, a first SWD section 262A may be positioned at or near a third corner 264C of the array region 254, and a second SWD section 262B may be positioned at or near a fourth corner 264D of the array region 254, the fourth corner 264D being positioned diagonally opposite (e.g., at a small angle) from the third corner 264C.

For each SWD segment 262 (e.g., first SWD segment 262A, second SWD segment 262B) of the control circuitry structure 200 within the horizontal region of the individual array region 254 of the microelectronic device 100, the SWD devices of the SWD segments 262 may be coupled to a group of word lines extending horizontally (e.g., in the X-direction) through the array region 254 by word line routing and contact structures 268.

For individual patch subsections 252 of the microelectronic device 100, SWD devices of the SWD sections 262 within array regions 254 (e.g., first and third array regions 254A and 254C; second and fourth array regions 254B and 254D) horizontally adjacent to each other in the X-direction of the control circuitry structure 200 may be coupled to different word line groups from each other. For example, each of the SWD sections 262 (e.g., each of the first and second SWD sections 262A, 262B) of the control circuitry structure 200 within the first array region 254A may include so-called "even" SWD devices coupled to even word lines within the memory array structure 300 (fig. 2D) by word line routing and contact structures 268 associated with the SWD sections 262, and each of the SWD sections 262 (e.g., each of the first and second SWD sections 262A, 262B) of the control circuitry structure 200 within the third array region 254C may include so-called "odd" SWD devices coupled to odd word lines within the memory array structure 300 (fig. 2D) by word line routing and contact structures 268 associated with the SWD sections 262, or vice versa. The even word lines of the memory array structure 300 (fig. 2D) may alternate horizontally in the Y-direction with the odd word lines of the memory array structure 300 (fig. 2D). The SWD devices of each of the SWD sections 262 of the control circuitry structure 200 within the horizontal region of the first array region 254A may not be coupled to any odd digit lines, and the SWD devices of each of the SWD sections 262 of the control circuitry structure 200 within the horizontal region of the third array region 254C may not be coupled to any He Ou digit lines, or vice versa. Similarly, each of the SWD sections 262 within the second array region 254B horizontally adjacent to the first array region 254A in the Y-direction (e.g., each of the first and second SWD sections 262A, 262B) may include additional even SWD devices coupled to additional even word lines within the memory array structure 300 (fig. 2D) by word line routing and contact structures 268 associated with the SWD sections 262, and each of the SWD sections 262 within the fourth array region 254D horizontally adjacent to the third array region 254C in the Y-direction (e.g., each of the first and second SWD sections 262A, 262B) may include additional odd SWD devices coupled to additional odd word lines within the memory array structure 300 (fig. 2D) by word line routing and contact structures 268 associated with the SWD sections 262, or vice versa.

As shown in fig. 2C, SWD devices (e.g., odd SWD devices or even SWD devices) within individual SWD sections 262 of individual array region 254 may be coupled to word lines (e.g., odd word lines or even word lines) that extend horizontally through array region 254, and may also be coupled to additional word lines (e.g., additional odd word lines or additional even word lines) that extend horizontally through another array region 254 that is horizontally adjacent to the array region 254 in the X-direction. For example, some odd SWD devices within the first SWD section 262A of the third array region 254C may be coupled to odd word lines extending horizontally through the third array region 254C by some word line routing and contact structures 268 extending to and through the second word line outlet sub-region 258B horizontally adjacent to the third array region 254C in the X-direction, and some additional odd SWD devices within the first SWD section 262A of the third array region 254C may be coupled to additional odd word lines 120A extending horizontally through the first array region 254A by some additional word line routing and contact structures 268 extending to and through the second word line outlet sub-region 258B. As another example, some even SWD devices within the second SWD section 262B of the first array region 254A may be coupled to even word lines extending horizontally through the first array region 254A by some word line routing and contact structures 268 extending to and through a first word line outlet sub-region 258A horizontally adjacent to the first array region 254A in the X-direction, and some additional even SWD devices within the second SWD section 262B of the first array region 254A may be coupled to additional even word lines 120B extending horizontally through the third array region 254C by some additional word line routing and contact structures 268 extending to and through the first word line outlet sub-region 258A.

With continued reference to fig. 2C, within the horizontal region of the individual patch subsections 252 of the microelectronic device 100, the control circuitry structure 200 may include additional control logic sections that individually include additional control logic devices (e.g., control logic devices other than SA devices and SWD devices). For example, for each array region 254 within the horizontal area of an individual patch sub-section 252 of the microelectronic device 100, the control circuitry structure 200 may include additional control logic sections positioned horizontally between the SA section 260 and the SWD section 262 (e.g., at relatively horizontally centered positions within the array region 254). Additional control logic sections may include, but are not limited to, a column decoder device section including a column decoder device, and a MWD section including a MWD device. In some embodiments, the additional control logic sections of the control circuitry structure 200 within the horizontal area of the individual patch subsections 252 of the microelectronic device 100 include a column decoder device section horizontally adjacent (e.g., directly horizontally adjacent) inward in the Y-direction to the SA section 260, and a MWD section horizontally adjacent (e.g., directly horizontally adjacent) inward in the X-direction to the SWD section 262.

Referring next to fig. 2D, an example arrangement of various circuitry of the memory array structure 300 within the horizontal regions of the peripheral circuitry region 202 and the memory bank region 204 of the microelectronic device 100 is depicted. To facilitate an understanding of the drawings and the associated description, not all features of the microelectronic device 100 previously described with reference to fig. 2A are depicted in fig. 2D. However, as previously mentioned herein, it will be understood that any features of the microelectronic device 100 described with reference to one or more of fig. 2A-2E are applicable to one or more (e.g., all) of the other of fig. 2A-2E.

Within the horizontal region of the peripheral circuitry area 202 of the microelectronic device 100, the memory array structure 300 can include at least one additional capacitor section 302 including circuitry (e.g., capacitors) configured and positioned to assist in powering various devices (e.g., control logic devices, access devices) of the microelectronic device 100. For example, the additional capacitor section 302 may include capacitors for charge pumps, RC filters, peaking amplifiers, capacitors for AC coupling (e.g., RF amplifier capacitors), capacitors for DC blocking (e.g., DC blocking capacitors), and decoupling capacitors, as well as capacitors for powering one or more control logic devices, such as one or more DSA devices, one or more ECC devices, one or more voltage generators (e.g., one or more low voltage generators, one or more high voltage generators), one or more command address devices, one or more capacitor structures (e.g., one or more decoupling capacitors), one or more data outputs (e.g., DQ, DQL), one or more command address devices, one or more antifuse devices, one or more DLL systems, one or more delay enabling devices (e.g., one or more dQ enabling delay devices), one or more temperature sensors, one or more data junctions for importing and exporting data to and from memory banks, and one or more additional logic devices. The capacitors within the additional capacitor section 302 of the memory array structure 300 may be coupled to the BEOL structure of the microelectronic device 100.

The additional capacitor section 302 of the memory array structure 300 may extend horizontally across one or more (e.g., each) of the center sub-region 202A, the first arm sub-region 202B, and the second arm sub-region 202C of the peripheral circuitry region 202 of the microelectronic device 100. In some embodiments, portions of the additional capacitor section 302 of the memory array structure 300 are positioned within the horizontal region of each of the center sub-region 202A, the first arm sub-region 202B, and the second arm sub-region 202C of the peripheral circuitry region 202 of the microelectronic device 100.

Within the horizontal region of the first memory bank sub-region 206 of the microelectronic device 100, the memory array structure 300 may include a memory array memory bank 304. Each first bank sub-region 206 of the microelectronic device 100 may include an individual memory array bank 304 of the memory array structure 300 within its horizontal region. As described in further detail below, each of the memory array banks 304 may include one or more memory array regions that individually include an array of memory cells (e.g., an array of DRAM cells).

Within the horizontal region of the second memory bank sub-region 208 of the microelectronic device 100, the memory array structure 300 can include additional memory array memory banks 306. Each second bank sub-region 208 of the microelectronic device 100 may include within its horizontal region an individual additional memory array memory bank 306 of the memory array structure 300. As described in further detail below, each of the additional memory array banks 306 may include one or more memory array regions that individually include an array of memory cells (e.g., an array of DRAM cells). The additional memory array banks 306 within the respective second bank sub-regions 208 may be relatively smaller (e.g., shorter) than the memory array banks 304 within the horizontal area of the respective first bank sub-regions 206 in the Y-direction and may be relatively larger (e.g., wider) than the memory array banks 304 within the horizontal area of the first bank sub-regions 206 in the X-direction. In some embodiments, the additional memory array banks 306 within the individual second bank sub-regions 208 have a length (e.g., a first horizontal dimension) in the Y-direction that is less than or equal to about half (1/2) of the length (e.g., the first horizontal dimension) of the memory array banks 304 within the horizontal region of the individual first bank sub-regions 206 in the Y-direction. Additionally, in some embodiments, the additional memory array banks 306 within the individual second bank sub-regions 208 have a width (e.g., a second horizontal dimension) in the X-direction that is greater than or equal to about twice (2X) the width (e.g., a second horizontal dimension) of the memory array banks 304 within the horizontal region of the individual first bank sub-regions 206 in the X-direction.

As previously mentioned, fig. 2E is a simplified schematic view of a portion B (illustrated with a dashed box in fig. 2D) of a memory array structure 300 of a microelectronic device 100, according to an embodiment of the disclosure. Part B illustrates the configuration of the memory array structure 300 within the horizontal region of the patch subsection 252 of the microelectronic device 100. The patch subsections 252 may be positioned within a horizontal region of one (1) of the second bank subsections 208 of one of the bank regions 204 of the control circuitry structure 200 (e.g., the first bank region 204A). Each of the second bank sub-regions 208 (fig. 2D) of the memory array structure 300 may include multiple (e.g., a group, multiple (a-multiple)) patch sub-sections 252 within its horizontal region, and the memory array structure 300 may exhibit a configuration similar to that shown in fig. 2E within the horizontal region of each patch sub-section 252. In addition, within the horizontal region of the individual first memory bank sub-regions 206 (fig. 2B) of the microelectronic device 100, the memory array structure 300 may include a plurality (multiple) (e.g., a group, a plurality (a-multiple)) of patch sub-sections 252, and the memory array structure 300 may exhibit a configuration similar to that shown in fig. 2E within the horizontal region of each patch sub-section 252.

As shown in fig. 2E, the memory array structure 300 of the microelectronic device 100 may include a memory cell array 308, digit lines 310, and word lines 312 within the horizontal area of each array region 254 of the individual patch subsections 252 of the microelectronic device 100. The memory cell array 308 may be coupled to a digit line 310 and a word line 312. The digit line 310 may extend in the Y-direction and may be coupled to an SA device of the SA section 260 (fig. 2C) of the control circuitry structure 200 (fig. 2C). Word line 312 may extend in the X-direction and may be coupled to SWD devices of SWD section 262 (fig. 2C) of control circuitry structure 200 (fig. 2C).

For the individual patch subsections 252 of the microelectronic device 100, the digit lines 310 within the memory array structure 300 may include odd digit lines 310A and even digit lines 310B. As previously discussed herein with reference to fig. 2C, the odd numbered lines 310A may be coupled to odd SA devices of the SA section 260 of the control circuitry structure 200, and the even numbered lines 310B may be coupled to even SA devices of the SA section 260 of the control circuitry structure 200.

For the individual patch subsections 252 of the microelectronic device 100, the word lines 312 within the memory array structure 300 may include odd word lines 312A and even word lines 312B. As previously discussed herein with reference to fig. 2C, the odd word lines 312A may be coupled to odd SWD devices of the SWD section 262 (fig. 2C) of the control circuitry structure 200 (fig. 2C), and the even word lines 312B may be coupled to even SWD devices of the SWD section 262 (fig. 2C) of the control circuitry structure 200 (fig. 2C).

Thus, in accordance with an embodiment of the present disclosure, a microelectronic device includes a peripheral circuitry region, a memory bank region, a control circuitry structure, and a memory array structure. The peripheral circuitry area includes a center sub-area and two arm sub-areas extending from the center sub-area in a first horizontal direction from the center sub-area. Each of the two arm subregions has a different length than the center subregion in a second horizontal direction orthogonal to the first horizontal direction. The memory bank region is horizontally outside the peripheral circuitry region. The control circuitry structure includes relatively more speed critical circuitry within a horizontal region of the peripheral circuitry region and relatively less speed critical circuitry within a horizontal region of the memory bank region. The memory array structure is vertically underlying the control circuitry structure and includes an array of memory cells within the horizontal region of the memory bank region.

In additional embodiments, the microelectronic device 100 is configured to have a different configuration than that previously described herein with reference to fig. 2A-2E. For example, the microelectronic device 100 may have a different general layout of different regions thereof, and may also have a different arrangement of various circuitry within its control circuitry structure 200 (fig. 2B) and memory array structure 300 (fig. 2D), as compared to that previously described herein with reference to fig. 2A. As a non-limiting example, fig. 3A-3C are simplified schematic views of different portions of a microelectronic device 400 (e.g., a memory device, such as a DRAM device) according to additional embodiments of the present disclosure. The microelectronic device 400 may have a general configuration substantially similar to that of the microelectronic device 100 previously described with reference to fig. 1, but may have an arrangement of various features thereof that is different from the arrangement of various features (e.g., regions, circuitry, devices, structures) of the microelectronic device 100 previously described with reference to fig. 2A-2E. Fig. 3A is a simplified schematic view of a microelectronic device 400 illustrating a general layout (e.g., a floor plan) of different regions of the microelectronic device 400, according to some embodiments of the disclosure. Fig. 3B is a simplified schematic view of a control circuitry structure 500 of a microelectronic device 400 showing an arrangement of various circuitry of the control circuitry structure 500 within different regions of the microelectronic device 400, according to some embodiments of the disclosure. Fig. 3C is a simplified schematic view of a memory array structure 600 of a microelectronic device 400 showing an arrangement of various circuitry of the memory array structure 600 within different regions of the microelectronic device 400, according to some embodiments of the disclosure.

Referring to fig. 3A, a microelectronic device 400 may include a peripheral circuitry region 402 and a memory bank region 408. As described in further detail below, within the control circuitry structure 500 (fig. 3B), relatively more speed critical circuitry and devices may be located within the horizontal area of the peripheral circuitry area 402, and relatively less speed critical circuitry and devices may be located within the horizontal area of the memory bank area 408.

The peripheral circuitry area 402 of the microelectronic device 400 may include a scribe line sub-area 404 and an additional scribe line sub-area 406 integral and continuous with the scribe line sub-area 404. Additional scribe line sub-region 406 may intersect the scribe line sub-region 404 horizontally. The location where the scribe line region 404 intersects with the extra scribe line region 406 and horizontally overlaps may be considered as a center region of the peripheral circuitry region 402. The scribe line sub-region 404 may extend in a substantially linear path in the X-direction and may be further divided into a first scribe line sub-region portion 404A and a second scribe line sub-region portion 404B in the X-direction. The extra dicing street sub-area 406 may extend in a substantially linear path in the Y-direction and may be further divided into a first extra dicing street sub-area portion 406A and a second extra dicing street sub-area portion 406B in the Y-direction.

As shown in fig. 3A, the scribe line subregion 404 and the additional scribe line subregion 406 of the peripheral circuitry region 402 may exhibit rectangular horizontal cross-sectional shapes. The combination of the scribe line sub-region 404 and the extra scribe line sub-region 406 may provide the peripheral circuitry region 402 with an irregular horizontal cross-sectional shape, such as a shape similar to the shape of a plus sign (+).

In some embodiments, the horizontal centerline of the scribe line region 404 in the Y direction is substantially aligned with the horizontal centerline 412 of the microelectronic device 400 in the Y direction, and the additional horizontal centerline of the additional scribe line region 406 in the X direction is substantially aligned with the additional horizontal centerline 414 of the microelectronic device 400 in the X direction. The horizontal centerline 412 of the microelectronic device 400 in the Y-direction may extend substantially linearly in the X-direction, and the additional horizontal centerline 414 of the microelectronic device 400 in the X-direction may extend substantially linearly in the Y-direction. An additional horizontal centerline 414 of the microelectronic device 400 in the X-direction may divide the dicing street sub-region 404 into a first dicing street sub-region portion 404A and a second dicing street sub-region portion 404B. The horizontal centerline 412 of the microelectronic device 400 in the Y-direction may divide the extra dicing street sub-area 406 into a first extra dicing street sub-area portion 406A and a second extra dicing street sub-area portion 406B. In additional embodiments, the horizontal centerline of the scribe line region 404 in the Y direction is offset from the horizontal centerline 412 of the microelectronic device 400 in the Y direction, and/or the additional horizontal centerline of the additional scribe line region 406 in the X direction is offset from the additional horizontal centerline 414 of the microelectronic device 400 in the X direction.

As shown in fig. 3A, the scribe line region 404 of the peripheral circuitry region 402 may extend continuously in the X-direction across at least a majority (e.g., greater than 50%, greater than or equal to 75%, greater than or equal to 90%, greater than or equal to 95%) of the microelectronic device 400, and may have a first length L ₁₀ in the Y-direction. In addition, the additional scribe line region 406 of the peripheral circuitry region 402 may extend continuously in the Y-direction across at least a majority (e.g., greater than 50%, greater than or equal to 75%, greater than or equal to 90%, greater than or equal to 95%) of the microelectronic device 400, and may have a first width W ₁₀ in the X-direction. In some embodiments, the first width W ₁₀ of the additional scribe line region 406 in the X-direction is substantially equal to the first length L ₁₀ of the scribe line region 404 in the Y-direction. In additional embodiments, the first width W ₁₀ of the additional scribe line region 406 in the X-direction is different (e.g., less than, greater than) the first length L ₁₀ of the scribe line region 404 in the Y-direction.

Still referring to fig. 2A, the memory bank regions 408 of the microelectronic device 400 may be horizontally separated from one another by the peripheral circuitry region 402 of the microelectronic device 400. The microelectronic device 400 may include, for example, four (4) memory bank regions 408, a first memory bank region 408A, a second memory bank region 408B, a third memory bank region 408C, and a fourth memory bank region 408D. The second bank region 408B may be horizontally adjacent to the first bank region 408A in the Y direction and may be horizontally adjacent to the fourth bank region 408D in the X direction. The third bank region 408C may be horizontally adjacent to the first bank region 408A in the X direction and may be horizontally adjacent to the fourth bank region 408D in the Y direction. The fourth bank region 408D may be horizontally adjacent to the third bank region 408C in the Y direction and may be horizontally adjacent to the second bank region 408B in the Y direction. In additional embodiments, the microelectronic device 400 includes a different number of memory bank regions 408. For example, the microelectronic device 400 may include more than four (4) memory bank regions 408 or less than four (4) memory bank regions 408.

Each of the memory bank regions 408 (e.g., first memory bank region 408A, second memory bank region 408B, third memory bank region 408C, fourth memory bank region 408D) of the microelectronic device 400 can exhibit a rectangular horizontal cross-sectional shape. As shown in fig. 3A, each of the bank regions 408 may have a second length L ₁₁ in the Y-direction and a second width W ₁₁ in the X-direction.

The individual bank regions 408 of the microelectronic device 400 may include a bank sub-region 410 and at least one throat sub-region 413. The throat subregion 413 of the bank region 408 may extend in a substantially linear path in the Y-direction and may be interposed between some (e.g., a group) of the plurality of bank subregions 410 of the bank region 408 and some other (e.g., an additional group) of the plurality of bank subregions 410 of the bank region 408 in the X-direction. As described in further detail below, within the memory array structure 600 (fig. 3C) of the microelectronic device 400, the memory banks of memory cells may be positioned within the horizontal region of the bank sub-region 410 of the bank region 408.

The bank sub-region 410 of the bank region 408 (e.g., first bank region 408A, second bank region 408B, third bank region 408C, fourth bank region 408D) of the microelectronic device 400 may exhibit a rectangular horizontal cross-sectional shape. In some embodiments, the bank sub-regions 410 exhibit rectangular horizontal cross-sectional shapes that are substantially identical to each other. As shown in fig. 3A, each of the bank sub-regions 410 may have a third length L ₁₂ in the Y-direction and a third width W ₁₂ in the X-direction.

The memory bank regions 408 (e.g., first memory bank region 408A, second memory bank region 408B, third memory bank region 408C, fourth memory bank region 408D) of the microelectronic device 400 may individually include a desired number of memory bank sub-regions 410. As shown in fig. 3A, in some embodiments, individual bank regions 408 include eight (8) bank subregions 410 within their horizontal regions. Eight (8) bank sub-regions 410 may include a first group of four (4) bank sub-regions 410 positioned at one side of the throat sub-region 413 of the bank region 408 and a second group of four (4) bank sub-regions 410 positioned at another opposite side of the throat sub-region 413 of the bank region 408. The four (4) bank sub-regions 410 of the first group may be substantially aligned with each other in the X-direction. The four (4) bank sub-regions 410 of the second group may also be substantially aligned with each other in the X-direction. The throat subregion 413 of the bank region 408 horizontally separates a first group of four (4) bank subregions 410 from a second group of four (4) bank subregions 410 in the X-direction. In additional embodiments, one or more (e.g., each) of the bank regions 408 individually includes a different number of bank sub-regions 410 (e.g., greater than eight (8) bank sub-regions 410, less than eight (8) bank sub-regions 410) within their horizontal regions.

Referring next to fig. 3B, an example arrangement of various circuitry of the control circuitry structure 500 within the horizontal regions of the peripheral circuitry region 402 and the memory bank region 408 of the microelectronic device 400 is depicted. To facilitate an understanding of the drawings and the associated description, not all features of the microelectronic device 400 previously described with reference to fig. 3A are depicted in fig. 3B. However, it will be understood that any features of the microelectronic device 400 described with reference to one or more of fig. 3A-3C are applicable to one or more (e.g., all) of the other of fig. 3A-3C.

As previously described herein, the control circuitry structure 500 may contain relatively more speed critical circuitry and devices within the horizontal area of the peripheral circuitry area 402 of the microelectronic device 400. For example, within the horizontal region of the peripheral circuitry area 402 of the microelectronic device 400, the control circuitry structure 500 may include, but is not limited to, an internal clock and timing generator section 502, a data I/O and control section 504, a Command and Address (CA) section 506, a data junction section 508, an analog section 510, a capacitor section 512, a fuse section 514, a voltage generator section 516, and a package interface section 518. The foregoing sections and their arrangement within the horizontal region of the peripheral circuitry area 402 of the microelectronic device 400 are described in further detail below.

The internal clock and timing generator section 502 of the control circuitry structure 500 may include substantially similar devices and circuitry as the internal clock and timing generator section 216 (fig. 2B) of the control circuitry structure 200 (fig. 2B) described previously herein with reference to fig. 2B. As shown in fig. 3B, the internal clock and timing generator section 216 may be positioned at or near the horizontal center of the horizontal region of the peripheral circuitry area 402, such as at or near the intersection of the scribe line sub-area 404 and the additional scribe line sub-area 406 of the peripheral circuitry area 402. In some embodiments, the internal clock and timing generator section 502 is positioned at or near a horizontal center of the microelectronic device 400 defined by the intersection of the horizontal centerline 412 (fig. 3A) of the microelectronic device 400 in the Y-direction and the additional horizontal centerline 414 (fig. 3A) of the microelectronic device 400 in the X-direction.

The data I/O and control section 504 of the control circuitry structure 500 may include substantially similar devices and circuitry as the devices and circuitry of the data I/O and control section 214 (fig. 2B) of the control circuitry structure 200 (fig. 2B) previously described herein with reference to fig. 2B. As shown in fig. 3B, the data I/O and control section 504 may be positioned within a horizontal region of the dicing lane sub-area 404 of the peripheral circuitry area 402 of the microelectronic device 400. The data I/O and control section 504 may, for example, include a first data I/O and control section 504A and a second data I/O and control section 504B. In some embodiments, the first data I/O and control section 504A and the second data I/O and control section 504B are each positioned within a horizontal region of the first dicing lane subsection 404A of the peripheral circuitry area 402 of the microelectronic device 400. The first data I/O and control section 504A may be positioned relatively closer to the internal clock and timing generator section 502 in the X direction, and the second data I/O and control section 504B may be positioned relatively farther from the internal clock and timing generator section 502 in the X direction. The first data I/O and control section 504A and the second data I/O and control section 504B may be horizontally offset from each other in the X-direction by one or more other of the sections of the control circuitry structure 500 (e.g., one of the data junction sections 508), as described in further detail below. The first data I/O of the control circuitry structure 500 and the data I/O and control circuitry 138 (fig. 1) within the control section 504A may be used for banks of memory cells of the memory array structure 600 (fig. 3C) that are positioned within a horizontal region of a first half of the microelectronic device 400 (e.g., the half above the horizontal centerline 412 (fig. 3A)). The second data I/O of the control circuitry structure 500 and the data I/O and control circuitry 138 (fig. 1) within the control section 504B may be used for banks of memory cells of the memory array structure 600 (fig. 3C) that are positioned within a horizontal region of a second, different half of the microelectronic device 400, e.g., the half below the horizontal centerline 412 (fig. 3A).

The CA section 506 of the control circuitry structure 500 may include the CA input circuitry 115 and CA decoder circuitry 124 previously described with reference to FIG. 1. As non-limiting examples, CA section 506 may include one or more (e.g., each) of a column address buffer circuit, a center driver circuit, epprMode register circuits, pcc control Wck circuits, ecs control circuits, QED shifter circuits, clkgen refresh circuits, column controller circuits, command extender circuits, act_pre_cntl circuits, and BARArray timer circuits. As shown in fig. 3B, the CA section 506 may also be positioned within a horizontal region of the dicing lane sub-area 404 of the peripheral circuitry area 402 of the microelectronic device 400. In some embodiments, the CA section 506 is positioned within a horizontal region of the second dicing lane sub-section 404B of the peripheral circuitry area 402 of the microelectronic device 400. The CA section 506 may be positioned proximate to the internal clock and timing generator section 502 in the X-direction, such as directly horizontally adjacent to the internal clock and timing generator section 502 in the X-direction.

The data junction section 508 of the control circuitry structure 500 may include substantially similar devices and circuitry as the devices and circuitry of the data junction section 228 (fig. 2B) of the control circuitry structure 200 (fig. 2B) previously described herein with reference to fig. 2B. The data junction section 508 may also be positioned within the horizontal region of the dicing street sub-region 404 of the peripheral circuitry area 402 of the microelectronic device 400. The data junction sections 508 may, for example, include a first data junction section 508A and a second data junction section 508B. In some embodiments, the first data junction section 508A is positioned within a horizontal region of the first scribe line sub-section 404A of the peripheral circuitry area 402 and the second data junction section 508B is positioned within a horizontal region of the second scribe line sub-section 404B of the peripheral circuitry area 402. The first data junction section 508A may be interposed between the first data I/O and control section 504A and the second data I/O and control section 504B along the X direction. The second data junction section 508B may be interposed between the CA section 506 and the second data I/O and analog section 510 in the X direction. As shown in fig. 3B, the first data junction section 508A may overlap horizontally in the X-direction with the throat subregions 413 of the first and second memory bank regions 408A, 408B of the microelectronic device 400, and the second data junction section 508B may overlap horizontally in the X-direction with the throat subregions 413 of the third and fourth memory bank regions 408C, 408D of the microelectronic device 400.

The analog section 510 of the control circuitry structure 500 may include substantially similar devices and circuitry as the devices and circuitry of the analog section 226 (fig. 2B) of the control circuitry structure 200 (fig. 2B) previously described herein with reference to fig. 2B. The analog section 510 may also be positioned within the horizontal area of the dicing lane sub-area 404 of the peripheral circuitry area 402 of the microelectronic device 400. In some embodiments, the analog section 510 is positioned within a horizontal region of the second dicing lane sub-section 404B of the peripheral circuitry area 402 of the microelectronic device 400. The analog section 510 may be positioned proximate to the second data junction section 508B in the X-direction, e.g., directly horizontally adjacent to the second data junction section 508B in the X-direction.

The capacitor section 512 of the control circuitry structure 500 may include substantially similar devices and circuitry as the devices and circuitry of the capacitor section 222 (fig. 2B) of the control circuitry structure 200 (fig. 2B) previously described herein with reference to fig. 2B. The capacitor section 512 may also be positioned within the horizontal area of the dicing street section 404 of the peripheral circuitry area 402 of the microelectronic device 400. In some embodiments, the capacitor section 512 is positioned within a horizontal region of the second dicing lane sub-section 404B of the peripheral circuitry area 402 of the microelectronic device 400. The capacitor section 512 may be positioned proximate to the analog section 510 in the X-direction, such as directly horizontally adjacent to the analog section 510 in the X-direction.

The fuse section 514 of the control circuitry structure 500 may include devices and circuitry substantially similar to the devices and circuitry of the fuse section 220 (fig. 2B) of the control circuitry structure 200 (fig. 2B) previously described herein with reference to fig. 2B. The fuse section 514 may also be positioned within the horizontal region of the scribe line region 404 of the peripheral circuitry region 402 of the microelectronic device 400. In some embodiments, the fuse section 514 is positioned within a horizontal region of the second dicing lane sub-section 404B of the peripheral circuitry area 402 of the microelectronic device 400. The fuse section 514 may be positioned proximate to the capacitor section 512 in the X-direction, such as directly horizontally adjacent to the capacitor section 512 in the X-direction.

The voltage generator section 516 of the control circuitry structure 500 may include substantially similar devices and circuitry as the devices and circuitry of the voltage generator section 224 (fig. 2B) of the control circuitry structure 200 (fig. 2B) previously described herein with reference to fig. 2B. The voltage generator section 516 may also be positioned within the horizontal region of the dicing lane sub-area 404 of the peripheral circuitry area 402 of the microelectronic device 400. The voltage generator section 516 may include, for example, a first voltage generator section 516A and a second voltage generator section 516B. In some embodiments, a first voltage generator section 516A is positioned within a horizontal region of the first scribe line sub-section 404A of the peripheral circuitry area 402 and a second voltage generator section 516B is positioned within a horizontal region of the second scribe line sub-section 404B of the peripheral circuitry area 402. The first voltage generator section 516A may be positioned proximate to the first data I/O and control section 504A in the X-direction, e.g., directly horizontally adjacent to the first data I/O and control section 504A in the X-direction. The second voltage generator section 516B may be positioned proximate to the fuse section 514 in the X-direction, such as directly horizontally adjacent to the fuse section 514 in the X-direction.

The package interface section 518 of the control circuitry structure 500 may include substantially similar devices and circuitry as the devices and circuitry of the package interface section 230 (fig. 2B) of the control circuitry structure 200 (fig. 2B) previously described herein with reference to fig. 2B. The package interface section 518 may be positioned within a horizontal region of the additional dicing lane sub-area 406 of the peripheral circuitry area 402 of the microelectronic device 400. The encapsulation interface section 518 may, for example, include a first encapsulation interface section 518A and a second encapsulation interface section 518B. In some embodiments, a first package interface section 518A is positioned within a horizontal region of a first extra dicing street subsection 406A of the peripheral circuitry area 402 and a second package interface section 518B is positioned within a horizontal region of a second extra dicing street subsection 406B of the peripheral circuitry area 402. The first and second package interface sections 518A and 518B may be individually positioned proximate to the internal clock and timing generator section 502 in the Y-direction, such as directly horizontally adjacent to the internal clock and timing generator section 502 in the Y-direction. The internal clock and timing generator section 502 may be interposed between the first package interface section 518A and the second package interface section 518B along the Y-direction. The internal clock and timing generator section 502 may overlap horizontally with the first and second package interface sections 518A and 518B in the X-direction.

Within the horizontal region of the individual memory bank sub-regions 410 of the individual memory bank regions 408 of the microelectronic device 400, the control circuitry structure 500 may include a transistor array section 520, a row decoder section 522, a column decoder section 524, and a memory bank logic section 526. Within the individual memory bank sub-regions 410, a row decoder section 522 may be positioned horizontally adjacent to the transistor array section 520 in the Y-direction, and a column decoder section 524 may be interposed horizontally in the X-direction between the memory bank logic section 240 and each of the transistor array section 520 and the row decoder section 522.

The transistor array section 520 of the control circuitry structure 500 within the horizontal region of the individual memory bank sub-regions 410 of the microelectronic device 400 may include a plurality of patch sub-sections of the microelectronic device 400 within its horizontal region. The patch subsections of the microelectronic device 400 may be substantially similar to the patch subsections 252 (fig. 2C) of the microelectronic device 100 (fig. 2C) previously described herein with reference to fig. 2C. Within the horizontal region of the individual patch subsections of the microelectronic device 400, the control circuitry structure 500 may include various control logic circuitry (e.g., SA circuitry, decoder circuitry, such as column decoder circuitry, word line driver circuitry, such as MWD circuitry and SWD circuitry). As a non-limiting example, within the horizontal area of an individual patch sub-section of the microelectronic device 400, the control circuitry structure 500 may exhibit the configuration previously described herein with reference to fig. 2C.

The row decoder section 522 of the control circuitry structure 500 within the horizontal region of the individual memory bank sub-regions 410 of the microelectronic device 400 may include row decoder circuitry configured for implementing at least some row operations on banks of memory cells within the memory array structure 600 (fig. 3C) underlying the control circuitry structure 500. The memory banks of memory cells may be positioned within a horizontal region of the memory bank sub-region 410 of the microelectronic device 400, as described in further detail below with reference to fig. 3C. As shown in fig. 3C, the row decoder section 522 within the bank sub-region 410 may extend horizontally in the X-direction across at least a majority (e.g., greater than 50%, greater than or equal to 75%, greater than or equal to 90%, greater than or equal to 95%) of the transistor array section 520 within the bank sub-region 410. In addition, as shown in fig. 3B, row decoder sections 522 within horizontal regions of some pairs of bank sub-regions 410 that are adjacent to each other in the Y-direction and aligned with each other in the X-direction may be positioned proximate (e.g., directly adjacent) to each other in the Y-direction. The row decoder circuitry of row decoder sections 522 positioned proximate to each other in the Y-direction may be shared by other circuitry of the microelectronic device 400 within the horizontal regions of some pairs of the memory bank sub-regions 410 of the microelectronic device 400.

The column decoder section 524 of the control circuitry structure 500 within the horizontal region of the individual memory bank sub-regions 410 of the microelectronic device 400 may include column decoder circuitry configured for implementing at least some column operations on the banks of memory cells within the memory array structure 600 (fig. 3C) underlying the control circuitry structure 500. As shown in fig. 3B, the column decoder section 524 within the bank sub-region 410 may be positioned horizontally in the X-direction at or near the horizontal ends of the transistor array section 520 and the row decoder section 522. The column decoder section 524 may extend horizontally in the Y-direction across at least a majority (e.g., greater than 50%, greater than or equal to 75%, greater than or equal to 90%, greater than or equal to 95%) of the total horizontal dimension (e.g., the total width in the Y-direction) of the combination of the transistor array section 520 and the row decoder section 522 within the memory bank sub-section 410.

The bank logic section 526 of the control circuitry structure 500 within the horizontal region of the individual bank sub-section 410 of the microelectronic device 400 may include additional control logic circuitry for implementing the operation of the control logic circuitry of the transistor array section 520, the row decoder section 522, and the column decoder section 524 within the bank sub-section 410. As shown in fig. 3B, the bank logic section 526 within the bank sub-region 410 may be positioned horizontally in the X-direction at or near the horizontal end of the column decoder section 524. The bank logic section 526 may extend horizontally in the Y-direction across at least a majority (e.g., greater than 50%, greater than or equal to 75%, greater than or equal to 90%, greater than or equal to 95%) of the column decoder section 524.

Still referring to fig. 3B, the control circuitry structure 500 may include a control logic device section 528 within the horizontal region of the respective throat subregion 413 of the respective memory bank region 408 of the microelectronic device 400. The individual control logic device sections 528 may include various control logic circuitry for the microelectronic device 400, including but not limited to DSA circuitry and ECC circuitry. In some embodiments, the individual control logic device sections 528 have both DSA circuitry and ECC circuitry within their horizontal regions. As shown in fig. 3B, the individual throat subregion 413 may include a plurality of control logic device segments 528 that are substantially aligned with each other in the X-direction. As a non-limiting example, within the horizontal region of the individual throat subregion 413 of the individual bank region 408, the control circuitry structure 500 may include a column of four (4) control logic device segments 528. The individual control logic device sections 528 may overlap two (2) memory bank sub-regions 410 of the memory bank region 408 in the Y-direction and may be interposed between two (2) memory bank sub-regions 410 of the memory bank region 408 in the X-direction. The control logic circuitry (e.g., DSA circuitry, ECC circuitry) of the individual control logic device sections 528 may be shared by other circuitry of the microelectronic device 400 within the horizontal area of the two (2) memory bank sub-sections 410 horizontally adjacent to the control logic device sections 528. The individual control logic device sections 528 may extend horizontally in the Y-direction across at least a majority (e.g., greater than 50%, greater than or equal to 75%, greater than or equal to 90%, greater than or equal to 95%) of each of the two (2) memory bank sub-sections 410 horizontally adjacent to the control logic device sections 528.

Referring next to fig. 3C, an example arrangement of various circuitry of the memory array structure 600 within the horizontal regions of the peripheral circuitry region 402 and the memory bank region 408 of the microelectronic device 400 is depicted. To facilitate an understanding of the drawings and the associated description, all features of the microelectronic device 400 previously described with reference to fig. 3A are shown and described in fig. 3C. However, as previously mentioned herein, it will be understood that any features of the microelectronic device 400 described with reference to one or more of fig. 3A-3C are applicable to one or more (e.g., all) of the other of fig. 3A-3C.

Within the horizontal region of the peripheral circuitry area 402 of the microelectronic device 400, the memory array structure 600 can include at least one additional capacitor section 602 including circuitry (e.g., capacitors) configured and positioned to assist in powering various devices (e.g., control logic devices, access devices) of the microelectronic device 400. For example, the additional capacitor section 602 may include capacitors for charge pumps, RC filters, peaking amplifiers, capacitors for AC coupling (e.g., RF amplifier capacitors), capacitors for DC blocking (e.g., DC blocking capacitors), and decoupling capacitors, as well as capacitors for powering one or more control logic devices, such as one or more DSA devices, one or more ECC devices, one or more voltage generators (e.g., one or more low voltage generators, one or more high voltage generators), one or more command address devices, one or more capacitor structures (e.g., one or more decoupling capacitors), one or more data outputs (e.g., DQ, DQL), one or more command address devices, one or more antifuse devices, one or more DLL systems, one or more delay enabling devices (e.g., one or more dQ enabling delay devices), one or more temperature sensors, one or more data junctions for importing and exporting data to and from memory banks, and one or more additional logic devices. The capacitors within the additional capacitor section 602 of the memory array structure 600 may be coupled to the BEOL structure of the microelectronic device 400.

The additional capacitor section 602 of the memory array structure 600 may extend horizontally across one or more (e.g., each) of the scribe line sub-region 404 and the additional scribe line sub-region 406 of the peripheral circuitry region 402 of the microelectronic device 100. In some embodiments, portions of the additional capacitor section 602 of the memory array structure 600 are positioned within the horizontal region of each of the first scribe line sub-region 404A, the second scribe line sub-region 404B, the first additional scribe line sub-region 406A, and the second additional scribe line sub-region 406B of the peripheral circuitry region 402 of the microelectronic device 400.

Within the horizontal region of the memory bank sub-region 410 of the microelectronic device 400, the memory array structure 600 may include a memory array memory bank 604. Each bank sub-region 410 of the microelectronic device 400 may include within its horizontal region an individual memory array bank 604 of the memory array structure 600. Memory array structure 600 memory array bank 604 within the horizontal region of individual bank sub-regions 410 of a microelectronic device 400 the memory array bank 604 may include a plurality of patch sub-segments of the microelectronic device 400 within its horizontal region. The patch subsections of the microelectronic device 400 may be substantially similar to the patch subsections 252 (fig. 2C) of the microelectronic device 100 (fig. 2C) previously described with reference to fig. 2C. Within the horizontal area of the individual patch subsections of the microelectronic device 400, the memory array structure 600 may include various circuitry (e.g., memory cell arrays, digit lines, word lines). As a non-limiting example, within the horizontal area of an individual patch sub-section of the microelectronic device 400, the memory array structure 600 can exhibit the configuration previously described with reference to fig. 2E.

Thus, in accordance with an embodiment of the present disclosure, a microelectronic device includes a peripheral circuitry region, a memory bank region, a control circuitry structure, and a memory array structure. The peripheral circuitry area includes a substantially linearly extending scribe line sub-area in a first horizontal direction and an additional scribe line sub-area that extends substantially linearly in a second horizontal direction orthogonal to the first horizontal direction. The additional scribe line subregion horizontally intersects the scribe line subregion. The memory bank regions are horizontally separated from each other by the peripheral circuitry region. The control circuitry structure includes relatively more speed critical circuitry within a horizontal region of the peripheral circuitry region and relatively less speed critical circuitry within a horizontal region of the memory bank region. The memory array structure is located vertically below the control circuitry structure and includes an array of memory cells within the horizontal region of the memory bank region.

Further, according to an embodiment of the present disclosure, a memory device includes a peripheral circuitry area, a memory bank area, a control circuitry structure, and a memory array structure. The peripheral circuitry area includes a center sub-area and at least two additional sub-areas extending horizontally from the center sub-area. The memory bank region is horizontally adjacent to the peripheral circuitry region. The control circuitry structure includes relatively more speed critical circuitry within a horizontal region of the peripheral circuitry region and relatively less speed critical circuitry within a horizontal region of the memory bank region. The memory array structure is attached to and vertically offset from the control circuitry structure. The memory array structure includes an array of memory cells within the horizontal region of the bank region.

Microelectronic devices (e.g., microelectronic device 100, microelectronic device 400) according to embodiments of the present disclosure may be used in embodiments of the electronic systems of the present disclosure. For example, fig. 4 is a simplified schematic block diagram illustrating an electronic system 700 according to an embodiment of the present disclosure. For example, electronic system 700 may include a computer or computer hardware component, a server or other networking hardware component, a cellular telephone, a digital camera, a Personal Digital Assistant (PDA), a portable media (e.g., music) player, wi-Fi, or a cellular-enabled tablet computer (such as, for exampleOr (b)Tablet computer), electronic book, navigation device, etc. The electronic system 700 includes at least one memory device 702. The memory device 702 may include, for example, a microelectronic device (e.g., microelectronic device 100, microelectronic device 400) as previously described herein. The electronic system 700 may further include at least one electronic signal processor device 704 (commonly referred to as a "microprocessor"). The electronic signal processor device 704 may optionally include the microelectronic devices previously described herein (e.g., microelectronic device 100, microelectronic device 400). Although the memory device 702 and the electronic signal processor device 704 are depicted in fig. 1 as two (2) separate devices, in additional embodiments a single (e.g., only one) memory/processor device with the functionality of the memory device 702 and the electronic signal processor device 704 is included in the electronic system 700. In such embodiments, the memory/processor device may include the microelectronic devices previously described herein (e.g., microelectronic device 100, microelectronic device 400). The electronic system 700 may further include one or more input devices 706, such as, for example, a mouse or other pointing device, keyboard, touchpad, buttons, or control panel, for inputting information into the electronic system 700 by a user. The electronic system 700 may further include one or more output devices 708 for outputting information (e.g., visual or audio output) to a user, such as, for example, a monitor, display, printer, audio output jack, speakers, etc. In some embodiments, input device 706 and output device 708 comprise a single touch screen device that can be used to both input information to electronic system 700 and output visual information to a user. The input device 706 and the output device 708 may be in electrical communication with one or more of the memory device 702 and the electronic signal processor device 704.

The structures, devices, and methods of the present disclosure advantageously facilitate one or more of improved microelectronic device performance, reduced cost (e.g., manufacturing cost, material cost), improved component miniaturization, and greater packing density as compared to conventional structures, conventional devices, and conventional methods. The structures, devices, and methods of the present disclosure may also improve scalability, efficiency, and simplicity as compared to conventional structures, conventional devices, and conventional methods.

Additional non-limiting example embodiments of the present disclosure are set forth below.

Embodiment 1a microelectronic device comprising a peripheral circuitry region comprising a central subregion, and two arm subregions extending from the central subregion in a first horizontal direction from the central subregion, each of the two arm subregions having a different length than the central subregion in a second horizontal direction orthogonal to the first horizontal direction, a memory bank region horizontally outboard of the peripheral circuitry region, a control circuitry structure comprising relatively more speed critical circuitry within a horizontal region of the peripheral circuitry region, and relatively less speed critical circuitry within a horizontal region of the memory bank region, and a memory array structure vertically underlying the control circuitry structure and comprising an array of memory cells within the horizontal region of the memory bank region.

Embodiment 2 the microelectronic device of embodiment 1 wherein the two arm subregions of the peripheral circuitry region comprise a first arm subregion extending substantially linearly in the first horizontal direction from a first side of the center subregion, a centerline of the first arm subregion in the second horizontal direction being offset from a centerline of the center subregion in the second horizontal direction, and a second arm subregion extending substantially linearly in the first horizontal direction from a second side of the center subregion, a centerline of the second arm subregion in the second horizontal direction being offset from each of the centerline of the first arm subregion and the centerline of the center subregion.

Embodiment 3 the microelectronic device of embodiment 2 wherein the center subregion of the peripheral circuitry region has a first length in the second horizontal direction and each of the first and second arm subregions of the peripheral circuitry region has a second length in the second horizontal direction that is less than the first length.

Embodiment 4 the microelectronic device of any of embodiments 2 and 3, wherein within a horizontal region of the center subregion of the peripheral circuitry region, the control circuitry structure comprises a data I/O and control circuitry comprising a data I/O and control circuitry, an internal clock and timing generator section adjacent to the data I/O and control section in the first horizontal direction and comprising an internal clock and timing generator circuitry, a Command and Address (CA) section adjacent to the internal clock and timing generator section in the first horizontal direction and comprising a CA circuitry, and a voltage generator section adjacent to each of the data I/O and control section, the internal clock and timing generator section, and the CA section in the second horizontal direction, the voltage generator sections each comprising a voltage generator circuitry.

Embodiment 5 the microelectronic device of embodiment 4 wherein within the central subregion of the peripheral circuitry region, the control circuitry structure further comprises a fuse section adjacent to the CA section in the first horizontal direction and comprising antifuse circuitry, and a capacitor section comprising a plurality of capacitors interposed between the voltage generator section and each of the data I/O and control section, the internal clock and timing generator section, the CA section, and the fuse section in the second horizontal direction.

Embodiment 6 the microelectronic device of any of embodiments 4 and 5, wherein within a horizontal region of each of the first and second arm regions of the peripheral circuitry region, the control circuitry structure comprises a data junction section comprising Multiplexer (MUX) circuitry, a package interface section comprising package interface circuitry, and an analog section interposed between the data junction section and the package interface section along the second horizontal direction and comprising one or more of analog temperature distribution circuitry, analog-to-digital conversion (ADC) devices, and digital-to-analog conversion (DAC) devices.

Embodiment 7 the microelectronic device of any of embodiments 2-6, wherein each of the memory regions includes a first memory region each including a first width in the first horizontal direction and a first length in the second horizontal direction orthogonal to the first horizontal direction, and a second memory region each including a second width in the first horizontal direction greater than the first width and a second length in the second horizontal direction less than the first length.

Embodiment 8 the microelectronic device of embodiment 7 wherein within the horizontal region of each of the first memory bank sub-regions, the control circuitry structure comprises a transistor array section, a row decoder section comprising row decoder circuitry adjacent to the transistor array section in the first horizontal direction, and a column decoder section individually comprising column decoder circuitry adjacent to the transistor array section and opposite ends of the row decoder section in the second horizontal direction.

Embodiment 9 the microelectronic device of embodiment 8 wherein within the horizontal region of each of the second memory bank sub-regions, the control circuitry structure includes additional transistor array sections, additional row decoder sections including additional row decoder circuitry interposed between the additional transistor array sections along the first horizontal direction, and additional column decoder sections including additional column decoder circuitry adjacent to the additional transistor array sections and the additional row decoder sections in the second horizontal direction.

Embodiment 10 the microelectronic device of any of embodiments 1-9, wherein within a horizontal region of the peripheral circuitry area, the memory array structure includes capacitors configured and positioned to assist in powering some devices within the control circuitry structure.

Embodiment 11 is a microelectronic device comprising a peripheral circuitry region including a scribe line region extending substantially linearly in a first horizontal direction and an additional scribe line region extending substantially linearly in a second horizontal direction orthogonal to the first horizontal direction, the additional scribe line region intersecting the scribe line region horizontally, a bank region horizontally separated from each other by the peripheral circuitry region, a control circuitry structure comprising relatively more speed critical circuitry within a horizontal region of the peripheral circuitry region and relatively less speed critical circuitry within a horizontal region of the bank region, and a memory array structure vertically below the control circuitry structure and comprising an array of memory cells within the horizontal region of the bank region.

Embodiment 12 the microelectronic device of embodiment 11 wherein the centerline of the street subregion in the first horizontal direction is substantially aligned within the centerline of the additional street subregion in the first horizontal direction and the additional centerline of the street subregion in the second horizontal direction is substantially aligned within the additional centerline of the additional street subregion in the second horizontal direction.

Embodiment 13 the microelectronic device of any of embodiments 11 and 12, wherein within the horizontal region of the lane sub-regions of the peripheral circuitry area, the control circuitry structure includes an internal clock and timing generator section including internal clock and timing generator circuitry, the internal clock and timing generator section at least partially horizontally overlapping additional lane sub-regions of the peripheral circuitry area in the first horizontal direction, a data I/O and control section including data I/O and control circuitry, the data I/O and control section adjacent a first side of the internal clock and timing generator section in the first horizontal direction, and a Command and Address (CA) section adjacent including CA circuitry, the Command and Address (CA) section adjacent a second side of the internal clock and timing generator section in the first horizontal direction.

Embodiment 14 the microelectronic device of embodiment 13 wherein within the horizontal region of the dicing street segment of the peripheral circuitry region, the control circuitry structure further comprises a first data junction section comprising Multiplexer (MUX) circuitry interposed horizontally in the first horizontal direction between two of the data I/O and control sections, a second data junction section comprising additional MUX circuitry horizontally adjacent to the CA section in the first horizontal direction, a first voltage generator section comprising voltage generator circuitry adjacent to one of the data I/O and control sections in the first horizontal direction, and a second voltage generator section comprising additional voltage generator circuitry adjacent to the second data junction section in the first horizontal direction.

Embodiment 15 the microelectronic device of embodiment 14, wherein within the horizontal region of the dicing street region of the peripheral circuitry region, the control circuitry structure further comprises an analog section interposed between the second data junction section and the second voltage generator section along the first horizontal direction and comprising one or more of analog temperature distribution circuitry, analog-to-digital conversion (ADC) devices, and digital-to-analog conversion (DAC) devices, a capacitor section interposed between the analog section and the second voltage generator section along the first horizontal direction and comprising a plurality of capacitors, and a fuse section interposed between the capacitor section and the second voltage generator section along the first horizontal direction, adjacent to and comprising the antifuse circuitry.

Embodiment 16 the microelectronic device of any of embodiments 11-15, wherein within the horizontal region of the additional dicing street sub-region of the peripheral circuitry area, the control circuitry structure comprises package interface sections each comprising package interface circuitry.

Embodiment 17 the microelectronic device of any of embodiments 11-16, wherein each of the bank regions includes a bank sub-region and a throat region interposed between a first group of the bank sub-regions and a second group of the bank sub-regions along the first horizontal direction.

Embodiment 18 the microelectronic device of embodiment 17 wherein within a horizontal region of each of the memory bank sub-regions of each of the memory bank regions, the control circuitry structure comprises a transistor array section, a row decoder section comprising row decoder circuitry adjacent to the transistor array section in the second horizontal direction, a column decoder section comprising column decoder circuitry adjacent to the transistor array section and the row decoder section in the first horizontal direction, and a bank logic section comprising bank logic adjacent to the column decoder section in the first horizontal direction, and within a horizontal region of the throat region of each of the memory bank regions, the control circuitry structure comprises control logic sections each comprising Digital Signal Acquisition (DSA) circuitry and Error Correction Code (ECC) circuitry.

Embodiment 19 is a memory device comprising a peripheral circuitry area comprising a center sub-area and at least two additional sub-areas extending horizontally from the center sub-area, a memory bank area horizontally adjacent to the peripheral circuitry area, a control circuitry structure comprising relatively speed critical circuitry within a horizontal area of the peripheral circuitry area and relatively less speed critical circuitry within a horizontal area of the memory bank area, and a memory array structure attached to and located vertically below the control circuitry structure, the memory array structure comprising an array of memory cells within the horizontal area of the memory bank area.

Embodiment 20 the memory device of embodiment 19 wherein the array of memory cells comprises an array of Dynamic Random Access Memory (DRAM) cells.

While the disclosure is susceptible to various modifications and alternative forms, specific embodiments have been shown by way of example in the drawings and have been described in detail herein. However, the present disclosure is not intended to be limited to the particular forms disclosed. On the contrary, the present disclosure is to cover all modifications, equivalents, and alternatives falling within the scope of the appended claims and their legal equivalents. For example, elements and features disclosed with respect to one embodiment may be combined with elements and features disclosed with respect to other embodiments of the present disclosure.

Claims

1. A microelectronic device, comprising:

a peripheral circuitry area comprising:

Center subregion

Two arm subregions extending from the center subregion in a first horizontal direction from the center subregion, each of the two arm subregions having a different length than the center subregion in a second horizontal direction orthogonal to the first horizontal direction;

A memory bank region horizontally outside the peripheral circuitry region;

A control circuitry architecture, comprising:

Relatively speed critical circuitry within the horizontal region of the peripheral circuitry area, and

Relatively less speed critical circuitry within the horizontal region of the memory bank region, and

A memory array structure vertically underlying the control circuitry structure and comprising an array of memory cells within the horizontal region of the memory bank region.

2. The microelectronic device of claim 1, wherein the two arm regions of the peripheral circuitry region comprise:

A first arm subregion extending substantially linearly in the first horizontal direction from a first side of the center subregion, a centerline of the first arm subregion in the second horizontal direction being offset from a centerline of the center subregion in the second horizontal direction, and

A second arm subregion extending substantially linearly in the first horizontal direction from a second side of the center subregion, a centerline of the second arm subregion in the second horizontal direction being offset from each of the centerline of the first arm subregion and the centerline of the center subregion.

3. The microelectronic device of claim 2, wherein:

The center subregion of the peripheral circuitry region has a first length in the second horizontal direction, and

Each of the first and second arm subregions of the peripheral circuitry region has a second length in the second horizontal direction that is less than the first length.

4. The microelectronic device of claim 2, wherein within a horizontal region of the central subregion of the peripheral circuitry region, the control circuitry structure comprises:

A data I/O and control section including data I/O and control circuitry;

An internal clock and timing generator section adjacent to the data I/O and control section in the first horizontal direction and including internal clock and timing generator circuitry;

A Command and Address (CA) section adjacent to the internal clock and timing generator section in the first horizontal direction and including CA circuitry, and

A voltage generator section adjacent to each of the data I/O and control section, the internal clock and timing generator section, and the CA section in the second horizontal direction, the voltage generator sections each including voltage generator circuitry.

5. The microelectronic device of claim 4, wherein within the center subregion of the peripheral circuitry region, the control circuitry structure further comprises:

a fuse section adjacent to the CA section in the first horizontal direction and including antifuse circuitry, and

A capacitor section including a plurality of capacitors interposed in the second horizontal direction between the voltage generator section and each of the data I/O and control section, the internal clock and timing generator section, the CA section, and the fuse section.

6. The microelectronic device of claim 4, wherein within a horizontal region of each of the first and second arm subregions of the peripheral circuitry region, the control circuitry structure comprises:

A data junction section including Multiplexer (MUX) circuitry;

A package interface section including package interface circuitry, and

An analog section interposed between the data junction section and the package interface section along the second horizontal direction and including one or more of analog temperature distribution circuitry, an analog-to-digital conversion (ADC) device, and a digital-to-analog conversion (DAC) device.

7. The microelectronic device of claim 2, wherein each of the memory bank regions comprises:

A first bank sub-region, each comprising:

A first width in the first horizontal direction, and

A first length in the second horizontal direction orthogonal to the first horizontal direction, and

A second bank sub-region, each comprising:

a second width greater than the first width in the first horizontal direction, and

A second length, in the second horizontal direction, that is less than the first length.

8. The microelectronic device of claim 7, wherein within a horizontal region of each of the first memory subregions, the control circuitry structure comprises:

A transistor array section;

a row decoder section including row decoder circuitry adjacent to the transistor array section in the first horizontal direction, and

A column decoder section individually including column decoder circuitry adjacent opposite ends of the transistor array section and the row decoder section in the second horizontal direction.

9. The microelectronic device of claim 8, wherein within a horizontal region of each of the second memory subregions, the control circuitry structure comprises:

an additional transistor array section;

An additional row decoder section including additional row decoder circuitry interposed between the additional transistor array sections along the first horizontal direction, and

An additional column decoder section including additional column decoder circuitry adjacent to the additional transistor array section and the additional row decoder section in the second horizontal direction.

10. The microelectronic device of any of claims 1-9, wherein within a horizontal region of the peripheral circuitry region, the memory array structure comprises capacitors configured and positioned to assist in powering some devices within the control circuitry structure.

11. A microelectronic device, comprising:

a peripheral circuitry area comprising:

A cutting lane sub-zone extending substantially linearly in a first horizontal direction, and

An additional scribe line sub-region extending substantially linearly in a second horizontal direction orthogonal to the first horizontal direction, the additional scribe line sub-region intersecting the scribe line sub-region horizontally;

A bank region horizontally separated from each other by the peripheral circuitry region;

A control circuitry architecture, comprising:

A memory array structure vertically below the control circuitry structure and comprising an array of memory cells within the horizontal region of the bank region.

12. The microelectronic device of claim 11, wherein:

The centerlines of the cutting street sub-regions in the first horizontal direction are substantially aligned within the centerlines of the additional cutting street sub-regions in the first horizontal direction, and

An additional centerline of the scribe line subregion in the second horizontal direction is substantially aligned within an additional centerline of the additional scribe line subregion in the second horizontal direction.

13. The microelectronic device of claim 11, wherein within a horizontal region of a dicing street segment of the peripheral circuitry region, the control circuitry structure comprises:

An internal clock and timing generator section comprising internal clock and timing generator circuitry, the internal clock and timing generator section at least partially horizontally overlapping additional dicing lane sub-sections of the peripheral circuitry area in the first horizontal direction;

a data I/O and control section including data I/O and control circuitry, the data I/O and control section being adjacent to a first side of the internal clock and timing generator section in the first horizontal direction, and

A Command and Address (CA) section, adjacent to which CA circuitry is included, the Command and Address (CA) section adjacent to a second side of the internal clock and timing generator section in the first horizontal direction.

14. The microelectronic device of claim 13, wherein within the horizontal region of a dicing street segment of the peripheral circuitry region, the control circuitry structure further comprises:

A first data junction section comprising Multiplexer (MUX) circuitry interposed horizontally in the first horizontal direction between two of the data I/O and control sections;

a second data junction section including additional MUX circuitry horizontally adjacent to the CA section in the first horizontal direction;

A first voltage generator section including voltage generator circuitry adjacent to one of the two of the data I/O and control sections in the first horizontal direction, and

A second voltage generator section including additional voltage generator circuitry adjacent to the second data junction section in the first horizontal direction.

15. The microelectronic device of claim 14, wherein within the horizontal region of a dicing street segment of the peripheral circuitry region, the control circuitry structure further comprises:

An analog section interposed between the second data junction section and the second voltage generator section along the first horizontal direction and including one or more of analog temperature distribution circuitry, an analog-to-digital conversion (ADC) device, and a digital-to-analog conversion (DAC) device;

a capacitor section interposed between the analog section and the second voltage generator section in the first horizontal direction and including a plurality of capacitors, and

A fuse section interposed between the capacitor section and the second voltage generator section along the first horizontal direction, adjacent to and including the antifuse circuitry.

16. The microelectronic device of any of claims 11-15, wherein within the horizontal region of the additional dicing lane sub-area of the peripheral circuitry area, the control circuitry structure comprises package interface sections each comprising package interface circuitry.

17. The microelectronic device of any of claims 11-15, wherein each of the memory regions comprises:

Memory bank subregions

A throat region interposed between the first group of bank subregions and the second group of bank subregions along the first horizontal direction.

18. The microelectronic device of claim 17, wherein:

within a horizontal region of each of the memory bank sub-regions of each of the memory bank regions, the control circuitry structure comprises:

A transistor array section;

A row decoder section including row decoder circuitry adjacent to the transistor array section in the second horizontal direction;

A column decoder section including column decoder circuitry adjacent to the transistor array section and the row decoder section in the first horizontal direction, and

A bank logic section including bank logic circuitry adjacent to the column decoder section in the first horizontal direction, and

Within the horizontal region of the throat region of each of the bank regions, the control circuitry structure includes control logic device sections each including Digital Signal Acquisition (DSA) circuitry and Error Correction Code (ECC) circuitry.

19. A memory device, comprising:

a peripheral circuitry area comprising:

Center subregion

At least two additional subregions extending horizontally from the central subregion;

a memory bank region horizontally adjacent to the peripheral circuitry region;

A control circuitry architecture, comprising:

A memory array structure attached to and vertically below the control circuitry structure, the memory array structure comprising an array of memory cells within the horizontal region of the bank region.

20. The memory device of claim 19, wherein the array of memory cells comprises an array of Dynamic Random Access Memory (DRAM) cells.