CN120567050A

CN120567050A - A highly integrated V-band broadband multi-channel multi-mode detector front-end chip

Info

Publication number: CN120567050A
Application number: CN202511022181.2A
Authority: CN
Inventors: 叶松; 贺永鑫
Original assignee: Chengdu Iridium Communications Co ltd
Current assignee: Chengdu Iridium Communications Co ltd
Priority date: 2025-07-24
Filing date: 2025-07-24
Publication date: 2025-08-29
Anticipated expiration: 2045-07-24

Abstract

This invention discloses a highly integrated V-band broadband multi-channel, multi-mode detector front-end chip, belonging to the field of millimeter-wave integrated circuits. The chip comprises a phase-locked loop (PLL) module, a radio frequency local oscillator (LO) chain module, a dual transmit channel module (TX), a dual receive channel module (RX), a pulse timing control module, and an SPI configuration interface module. This invention addresses the challenges of existing V-band detector chips, such as difficulty in generating broadband signals, severe multi-channel phase mismatches, complex and inefficient multi-mode systems, and the difficulty in balancing transmit link speed and power consumption.

Description

Front-end chip of highly integrated V-band broadband multichannel multimode detector

Technical Field

The invention belongs to the field of millimeter wave integrated circuits, and particularly relates to a front-end chip of a highly integrated V-band broadband multichannel multimode detector.

Background

With the wide application of millimeter wave detection technology in the fields of security inspection perspective, radio astronomy and the like, the performance requirement on the front-end chip of the V-band (60-90 GHz) detector is increasingly improved. In the prior art, probes have typically faced the disadvantage and bottleneck of achieving a direct oscillating VCO with a wide tuning range (e.g., 6 ghz+) in the V-band. Conventional schemes often employ frequency multiplication (sacrificing phase noise and efficiency) or multiple narrowband VCO switching (increasing complexity and area). There is a strong contradiction between wide tuning range and low phase noise and low power consumption. Integrating multiple millimeter wave transceiver channels (e.g., 2T 2R) on a single chip faces the great challenge that insufficient inter-channel isolation results in crosstalk, difficult signal path matching, concentrated power consumption and heat dissipation, and increased chip area. Most importantly, ensuring phase consistency (homography) of all channels is critical for advanced applications such as MIMO, beamforming, etc., but achieving accurate phase synchronization of multiple channels in the millimeter wave band is extremely complex and susceptible to process bias and temperature. Modern radar systems (e.g. automotive, industrial) often need to support both FMCW (continuous wave frequency modulation) and pulsed doppler modes. Conventional schemes typically require complex off-chip waveform generation circuitry (e.g., dac+fpga to generate triangular waves), sophisticated off-chip timing control circuitry to manage the on/off, delay, pulse width of the pulse pattern, which results in complex system board level design, large volume, high cost, and introduces additional delay, jitter, and signal integrity risks, limiting switching speed and timing accuracy. It has been difficult to design a high-efficiency, high-Power Amplifier (PA) itself in the millimeter wave band. Integrating it on-chip with the driver stage (TXDA) and the transmit switch (TXSW) that needs to handle high power, achieve fast turn-on/turn-off (steep rising/falling edges) is more challenging-TXDA needs to provide enough driving capability and is itself efficient, TXSW needs to keep low insertion loss (efficiency), high isolation (off state) and extremely fast switching speed (pulse mode critical) when handling high power of PA output.

Disclosure of Invention

Aiming at the defects in the prior art, the front-end chip of the highly integrated V-band broadband multichannel multimode detector provided by the invention solves the problems of difficult broadband signal generation, serious multichannel phase mismatch, complex and low-efficiency multimode system and difficult compromise of the speed and the power consumption of a transmitting link of the conventional V-band detector chip.

In order to achieve the aim of the invention, the technical scheme adopted by the invention is that the front-end chip of the high-integration V-band broadband multichannel multimode detector comprises:

The phase-locked loop module PLL comprises a phase-locked comparator, a loop filter and a voltage-controlled oscillator VCO;

The radio frequency local oscillator chain module LO comprises a voltage controlled oscillator VCO, a local oscillator buffer LOBUF, a receiving pulse switch RXSW, a transmitting pulse switch TXSW and a transmitting driving amplifier TXDA;

the dual transmit channel module TX comprises a power amplifier PA;

The dual receiving channel module RX comprises a low noise amplifier LNA, a low noise transconductance amplifier LNTA, a mixer MIX, a mixer local oscillation buffer MIXBUF, a transimpedance amplifier TIA, a transimpedance amplifier output buffer TIABUF, a high pass filter HPF, an intermediate frequency variable gain amplifier VGA, a low pass filter LPF and a baseband output buffer BBBUF;

The pulse time sequence control module outputs a transmitting time sequence pulse and a receiving time sequence pulse and is provided with an independent channel selection pin;

and the SPI configuration interface module is respectively connected with the phase-locked loop module, the radio frequency local oscillator chain module, the double-transmitting channel module, the double-receiving channel module and the pulse time sequence control module, and performs unified parameter configuration on the modules.

Further, after the VCO output of the PLL is buffered by the local oscillation buffer LOBUF, one path of the VCO output enters the mixer MIX of the RX and the other path of the VCO output returns to the PFD through the feedback divider inside the chip to lock the frequency in a closed loop.

Further, the local oscillation buffer LOBUF in the radio frequency local oscillation chain module LO is respectively connected to one end of the receive pulse switch RXSW, one end of the transmit pulse switch TXSW, and one end of the voltage-controlled oscillator VCO, the other end of the transmit pulse switch TXSW is connected to the input end of the transmit driving amplifier TXDA, and the other end of the voltage-controlled oscillator VCO is respectively connected to the pins VT33, VCOSEL, BANDSEL, and PREO.

Further, the dual transmit channel module TX is a two-channel transmit channel with the same structure, and includes a power amplifier PA, where an input end of the power amplifier PA is connected to an output end of the transmit driver amplifier TXDA, and an output end of the power amplifier PA is connected to the pin TXOL or TXOU.

Further, the dual receive channel module RX is two receive channels with the same structure, and includes:

The input end of the LNA is connected with a pin RXIL or RXIU, the output end of the LNA is connected with the input end of the LNTA, the output end of the LNTA is connected with the input end of the MIX, the output end of the MIX is respectively connected with the input end of the MIX local oscillation buffer MIXBUF and the input end of the TIA, the output end of the MIX local oscillation buffer MIXBUF is connected with the RXSW, the output end of the TIA is respectively connected with the input end of the HPF and the input end of the TIA output buffer TIABUF, the output end of the high pass filter HPF is connected with the input end of the intermediate frequency variable gain amplifier VGA and one end of the receiving pulse switch RXSW, the output end of the intermediate frequency variable gain amplifier VGA is connected with the input end of the low pass filter LPF, the output end of the low pass filter LPF is connected with the input end of the baseband output buffer BBBUF, the output end of the baseband output buffer BBBUF is connected with pins IFON _bb_rxu, ifop_bb_rxu, ifon_bb_rxl or IFOP _bb_rxl, the other end of the receiving pulse switch RXSW is connected with pins vga_inn_rxu, vga_inp_rxu, vga_inn_rxl or vga_inp_rxl, and the output end of the trans-impedance amplifier output buffer TIABUF is connected with pins rxifo_rxu or ifo_tia_rxl.

Further, the pulse timing control module includes pin TXPULSE, pin RXPULSE33, pin TXPULSEL33, and pin RXPULSEL;

the pin TXPULSE is connected with an external emission driver and is used for generating emission time sequence pulses;

the pin RXPULSE is connected with an external receiving driver and is used for generating a receiving time sequence pulse;

The pin TXPULSEL is coupled with the ground potential through a bypass capacitor, so that independent gating of an upper transmission channel and a lower transmission channel is realized;

the pin RXPULSEL is coupled with the ground potential through a bypass capacitor, so that independent gating of the upper receiving channel and the lower receiving channel is realized.

Further, the SPI configuration interface module comprises a pin SPI_ENB, a pin SPI_CLK, a pin SPI_DI and a pin SPI_DO;

enabling an SPI bus when the pin SPI_ENB is pulled down by the host MCU;

The pin SPI_CLK receives a clock signal provided by the host MCU and is used for synchronizing the shift and sampling of data;

the pin SPI_DI transmits a configuration word, a register address and a control command to an internal register of the chip;

when the pin SPI_DO reads the register, the chip serially returns the state data of the internal register to the host MCU through the pin and outputs the state data along the CLK edge.

Further, the chip further comprises an antenna output matching network, the antenna output matching network comprises a grounding capacitor C1, a capacitor C2, a grounding capacitor C3, a grounding capacitor C4, a grounding resistor R2, a resistor R3, a resistor R4 and a grounding resistor R5, one end of the capacitor C2 is respectively connected with one end of the grounding capacitor C1 and one end of the resistor R3 and a chip pin CP33, the other end of the capacitor C2 is connected with the grounding resistor R2, the other end of the resistor R3 is respectively connected with one ends of the grounding capacitor C3 and the resistor R4, the other end of the resistor R4 is respectively connected with one ends of the grounding capacitor C4, a chip pin VT33 and the resistor R5, and the other end of the resistor R5 is connected with an interface J3.

Further, the chip further comprises an interface J8, an interface J9, an interface J10 and an interface J11;

The port 1, the port 2, the port 3 and the port 4 of the interface J8 are all connected with one end of an inductor L1, the other end of the inductor L1 is respectively connected with a grounding capacitor C6 and a pin VDD12 RXRF RXMIX of the chip, and the port 5, the port 6, the port 7 and the port 8 of the interface J8 are all grounded;

Port 1 of the interface J9 is connected to pin LD33 of the chip, port 2 thereof is connected to one end of an inductor L3, the other end of the inductor L3 is connected to a ground capacitor C12, pins VDD12_xo and VDD12_spi of the chip, port 3 of the interface J9 is connected to one end of the inductor L2, the other end of the inductor L2 is connected to a ground capacitor C10, pins VDD33_ PFDCP and VDD33_pst of the chip, port 4 of the interface J9 is connected to pin spi_do of the chip, port 5 of the interface J9 is connected to pin spi_di of the chip, port 6 of the interface J9 is connected to pin spi_clk of the chip, port 7 of the interface J9 is connected to pin spi_enb of the chip, port 8 of the interface J9 is connected to pin 3836 of the chip, port 9 is connected to pin TXPULSEU of the chip, port 10 of the interface J9 is connected to pin 3233 of the chip, port 5 of the interface J9 is connected to pin spi_dl 33 of the chip, port 10 of the interface J9 is connected to pin 3233 of the chip, port 12 of the interface J9 is connected to pin 33 of the chip, and port 13 of the interface J9 is connected to pin 33 of the chip;

The port 1, the port 2, the port 3 and the port 4 of the interface J10 are all connected with one end of an inductor L4, the other end of the inductor L4 is respectively connected with a grounding capacitor C15 and a pin VDD12_PA of the chip, and the port 5, the port 6, the port 7 and the port 8 of the interface J10 are all grounded;

The port 1 and the port 2 of the interface J11 are connected with one end of an inductor L7, the other end of the inductor L7 is respectively connected with a grounding capacitor C20 and a pin VDD33_VT of the chip, the port 3 and the port 4 of the interface J11 are respectively connected with one end of an inductor L6, the other end of the inductor L6 is respectively connected with a grounding capacitor C18 and a pin VDD12_DIV of the chip, the port 5 of the interface J11 is connected with a pin VCOSEL of the chip, the port 6 of the interface J11 is connected with a pin BANDSEL33 of the chip, the port 7, the port 8 and the port 9 of the interface J11 are respectively grounded, the port 10, the port 11 and the port 12 of the interface J11 are respectively connected with one end of the inductor L5, and the other end of the inductor L5 is respectively connected with a grounding capacitor C16 and a pin VDD12_PA1 of the chip.

The front-end chip of the highly-integrated V-band broadband multichannel multimode detector has the beneficial effects that the problems that broadband signal generation is difficult, multichannel phase mismatch is serious, a multimode system is complex and low-efficiency, and the speed and the power consumption of a transmitting link are difficult to be compatible are solved by dividing four sections into four sections to cover 6GHz+ bandwidth, monolithically integrating 2T2R and guaranteeing phase consistency, integrating a triangular wave generator and programmable pulse time sequence control, and the high-efficiency and high-speed integrated design of TXDA and TXSW.

Drawings

FIG. 1 is a basic block diagram of a highly integrated V-band broadband multi-channel multi-mode detector front-end chip.

Fig. 2 is a schematic diagram of a highly integrated V-band broadband multi-channel multi-mode detector front-end chip.

Fig. 3 is a schematic diagram of the interfacing.

Detailed Description

The invention will be further described with reference to the drawings and specific examples.

As shown in fig. 1 and 2, a highly integrated V-band broadband multi-channel multi-mode detector front-end chip includes:

the dual transmit channel module TX comprises a power amplifier PA;

After the output of the voltage controlled oscillator VCO in the phase locked loop module PLL is buffered by the local oscillation buffer LOBUF, one path of the output enters the mixer MIX in the dual receiving channel module RX, and the other path of the output returns to the phase frequency detector PFD through the feedback frequency divider in the chip to lock the frequency in a closed loop. The pin VDD33_ PFDCP/PST of the chip is the power supply of the PLL sub-module, and TRIG_PULSE33 (which is connected to the E12 pin after R5/C3 filtering) is the lock start trigger signal.

The phase-locked loop module PLL internally integrates a phase-locked comparator, a loop filter and a VCO, wherein the REF_CLK is an external crystal oscillator input port, the VCO ground is tightly coupled with the ground network, and digital control signals related to all the PLLs are set through an SPI configuration interface, so that the programmable radio frequency local oscillation frequency is realized. The module cooperates with the double-transmitting and double-receiving channel and the pulse time sequence controller to form a complete receiving and transmitting management subsystem.

In the phase-locked loop module PLL and the radio frequency local oscillator chain module LO:

Chirp Gen (triangular wave generator) is started by SPI in FMCW mode, generating a linear slope control signal to the PLL. The phase-locked loop module PLL comprises a phase-locked comparator, a loop filter and a programmable frequency division network, and works together with the VCO feedback loop to realize the frequency locking and frequency sweep of the V-band local oscillator. The VCO oscillates directly in the V-band (60-90 GHz) and the output signal first goes into LOBUF and redistributes to the LO inputs of the transmit and receive mixers.

The local oscillation buffer LOBUF in the radio frequency local oscillation chain module LO is respectively connected with one end of the receiving pulse switch RXSW, one end of the transmitting pulse switch TXSW and one end of the voltage-controlled oscillator VCO, the other end of the transmitting pulse switch TXSW is connected with the input end of the transmitting driving amplifier TXDA, and the other end of the voltage-controlled oscillator VCO is respectively connected with pins VT33, VCOSEL33, BANDSEL33 and PREO.

The dual transmit channel module TX is a transmit channel with the same two-channel structure, and includes a power amplifier PA, where an input end of the power amplifier PA is connected to an output end of the transmit driver amplifier TXDA, and an output end of the power amplifier PA is connected to the pin TXOL or TXOU.

As shown in fig. 2, the dual transmit channel module includes two rf output pins TXOU (Q7) and TXOL (Q5) corresponding to transmit channel 1 and transmit channel 2, respectively, from which transmit output signals are ultimately sent to an external antenna interface (NC) via an off-chip impedance matching network. The power supply of the transmitting-stage power amplifier is also supplied by a 1.2V power supply network, all transmitting channels are internally integrated with a front-stage power device, and the VSS_PA pin at the output end is grounded, so that the stability of the output of radio frequency power is ensured.

The dual receiving channel module RX is two receiving channels with the same structure, and includes:

The LNA and the LNTA perform primary amplification and impedance transformation on weak echo signals fed by the antenna. MIXBUF +MIX mixes the LNA/LNTA output with the LO signal to obtain the intermediate frequency IF. HPF+VGA+LPF+BB_BUF (high pass filtering, variable gain amplification, low pass filtering, baseband buffering) is used for filtering out high-frequency spurious and adjustable gain amplification intermediate frequency signals, and then outputting low-frequency baseband signals. The final baseband signal is led out from each pin.

As shown in fig. 2, the chip is of the model yx8922_ wlcsp _v1, wherein the dual-receive channel module further comprises RXIU (B6), RXIL (B4) two rf input pins, and a common low noise front end (tia_if_out_rxu/C1, tia_if_out_rxl/E1). The signals amplified by TIA are output from TIA_IF_OUT_RXU and TIA_IF_OUT_RXL pins to the later stages in the chip, the later stages use VGA_INN_RXU (J1)/VGA_INP_RXU (J2) and VGA_INN_RXL (L2)/VGA_INP_RXL (L1) to carry OUT variable gain amplification on the uplink and downlink channels, and the baseband output is led OUT from IF_OUTP_RXL (N1) and IF_OUTN_RXL (O1) pins. The pins C1, E1, G1, H1, J2, L1, N1 and O1 are respectively connected with decoupling capacitors C21, C22, C23, C24, C25, C26, C27, C28, C29 and C30 in parallel, and the other ends of the capacitors are respectively connected with external interfaces J14, J15, J16, J17, J18, J19, J20, J21, J13 and J12.

Pin ref_clk (E12) connects decoupling capacitor C6 (200 pF) in parallel to ground, PREO (O10) connects decoupling capacitor C5 (50 pF) in parallel to ground for VCO output bypass as PLL reference clock decoupling. All vss_lo pins are grounded.

Pins VSS_ RX, VSSPST, VSS _XO_DIV, VSS33_PFDCP, VSS_PKG, and vss10_SPI are all grounded.

The SPI configuration interface module is communicated with an external main control through four pins and is used for configuring internal registers, including PLL frequency division ratio, transmitting/receiving gate control time sequence, FMCW triangular wave parameters and the like. The module provides programmable control for key parameters such as PLL loop parameters, LO output power, detection channel gain, baseband filter bandwidth and the like, and flexible configuration and real-time monitoring for the V-band detector are realized.

The pulse timing control module comprises a pin TXPULSE, a pin RXPULSE33, a pin TXPULSEL and a pin RXPULSEL;

The PULSE timing control module receives SPI configuration and then generates various timing PULSEs (TXSW, RXSW gating signals), and completes PULSE Doppler or FMCW starting/ending control through the cooperation of pins such as TRIG_PULSE33, RXPULSEL33 and the like at the bottom and an external trigger (such as an FPGA).

The SPI configuration interface module comprises a pin SPI_ENB, a pin SPI_CLK, a pin SPI_DI and a pin SPI_DO;

The SPI bus is enabled when the pin SPI_ENB is pulled down by the host MCU, chip selection is released when the power is high, and all SPI pins enter high resistance to avoid collision with other SPI devices;

The pin SPI_CLK receives a clock signal provided by the host MCU and is used for synchronizing the shift and sampling of data, all DI/DO are positioned on the rising edge or the falling edge of CLK for latching, and the specific time sequence is determined by a time sequence table;

The pin SPI_DI transmits configuration words, register addresses and control commands to the internal registers of the chip;

when the pin SPI_DO reads the register, the chip serially returns the state data of the internal register to the host MCU through the pin and outputs the state data along the edge of the CLK.

The chip further comprises an antenna output matching network, the antenna output matching network comprises a grounding capacitor C1, a capacitor C2, a grounding capacitor C3, a grounding capacitor C4, a grounding resistor R2, a resistor R3, a resistor R4 and a grounding resistor R5, one end of the capacitor C2 is respectively connected with one end of the grounding capacitor C1 and one end of the resistor R3 and a chip pin CP33, the other end of the capacitor C2 is connected with the grounding resistor R2, the other end of the resistor R3 is respectively connected with one end of the grounding capacitor C3 and one end of the resistor R4, the other end of the resistor R4 is respectively connected with one end of the grounding capacitor C4, one end of the chip pin VT33 and one end of the resistor R5, and the other end of the resistor R5 is connected with an interface J3.

As shown in fig. 3, the chip further includes an interface J8, an interface J9, an interface J10, and an interface J11, and is connected with an external device through each interface;

The power supply adopted in the chip comprises:

VDD12 PA 1.2V bias supply, led out to all power amplifier PA bias points.

VDD12 RX 1.2V bias power supply, led to all receive channel low noise amplifier LNA, transconductance amplifier LNTA and detector bias.

VDD12_SPI 1.2V power, SPI configuration logic and PULSE timing control PULSE CTRL.

VDD3V 3:3.3V main power is led out to PLL, VCO, LO buffer and other digital/analog modules.

The signal flow and the working mode of the chip provided by the invention are as follows:

FMCW mode, in which SPI issues triangle wave parameters, chirp Gen generates slope, PLL/VCO continuously sweeps linearly, TXSW is always on, TXDA is changed to PA transmitting frequency continuously, echo signal is mixed to generate difference frequency IF changing with distance, and then amplified, filtered and output to external ADC.

The pulse Doppler mode comprises SPI configuration with fixed LO frequency, external or internal trigger generation pulse time sequence (TXSW is opened, transmitting, closing, RXSW is opened, receiving), and multiple paths of receiving channels can work simultaneously or in a time sharing mode, and an intermediate frequency post-stage is output for processing by a distance measuring and speed measuring algorithm.

All modules are connected with each other through pins to form a complete V-band detection link. The SPI configuration interface module is responsible for carrying out unified parameter configuration on functional units such as a PLL (phase locked loop), an LO (local oscillator), a detection channel and the like, the pulse time sequence controller realizes time-sharing gating of the detection channel, the double detection channel completes frequency mixing and envelope detection of V-band signals, and the LO chain and the PLL module provide high-stability local oscillation signals for the frequency mixer so as to jointly meet the detection requirements of high sensitivity and low noise of the V-band.

Those of ordinary skill in the art will recognize that the embodiments described herein are for the purpose of aiding the reader in understanding the principles of the present invention and should be understood that the scope of the invention is not limited to such specific statements and embodiments. Those of ordinary skill in the art can make various other specific modifications and combinations from the teachings of the present disclosure without departing from the spirit of the invention, and such modifications and combinations are still within the scope of the invention.

Claims

1. A highly integrated V-band broadband multichannel multimode detector front-end chip comprising:

the dual transmit channel module TX comprises a power amplifier PA;

2. The front-end chip of the highly integrated V-band wideband multi-channel multi-mode detector according to claim 1, wherein the VCO output of the PLL is buffered by the local oscillation buffer LOBUF, one path of the VCO output enters the mixer MIX of the RX and the other path of VCO output returns to the PFD via the feedback divider inside the chip to lock the frequency in a closed loop.

3. The front-end chip of the highly integrated V-band wideband multi-channel multi-mode detector according to claim 2, wherein the local oscillation buffer LOBUF in the radio frequency local oscillation chain module LO is respectively connected to one end of the receive pulse switch RXSW, one end of the transmit pulse switch TXSW and one end of the voltage controlled oscillator VCO, the other end of the transmit pulse switch TXSW is connected to the input end of the transmit driving amplifier TXDA, and the other end of the voltage controlled oscillator VCO is respectively connected to pins VT33, VCOSEL, BANDSEL33 and PREO.

4. The front-end chip of claim 3, wherein the dual transmit channel module TX is a two-channel transmit channel with the same structure, and comprises a power amplifier PA, an input terminal of the power amplifier PA is connected to an output terminal of the transmit driver amplifier TXDA, and an output terminal thereof is connected to a pin TXOL or TXOU.

5. The front-end chip of the highly integrated V-band wideband multi-channel multi-mode detector according to claim 4, wherein the dual receive channel module RX is a two-channel receive channel with the same structure, comprising:

6. The highly integrated V-band broadband multi-channel multi-mode detector front-end chip of claim 5, wherein said pulse timing control module comprises pin TXPULSE, pin RXPULSE33, pin TXPULSEL33, and pin RXPULSEL;

7. The highly integrated V-band broadband multi-channel multi-mode detector front-end chip of claim 6, wherein said SPI configuration interface module comprises pin spi_enb, pin spi_clk, pin spi_di, and pin spi_do;

enabling an SPI bus when the pin SPI_ENB is pulled down by the host MCU;

8. The front-end chip of the highly integrated V-band broadband multi-channel multi-mode detector according to claim 7, further comprising an antenna output matching network, wherein the antenna output matching network comprises a grounding capacitor C1, a capacitor C2, a grounding capacitor C3, a grounding capacitor C4, a grounding resistor R2, a resistor R3, a resistor R4 and a grounding resistor R5, one end of the capacitor C2 is connected with one end of the grounding capacitor C1 and the resistor R3 and the chip pin CP33, the other end of the capacitor C2 is connected with the grounding resistor R2, the other end of the resistor R3 is connected with one end of the grounding capacitor C3 and one end of the resistor R4, the other end of the resistor R4 is connected with one end of the grounding capacitor C4, the chip pin VT33 and one end of the resistor R5, and the other end of the resistor R5 is connected with the interface J3.

9. The highly integrated V-band broadband multi-channel multi-mode detector front-end chip of claim 8, further comprising interface J8, interface J9, interface J10, and interface J11;