CN120440831A - MEMS packaging structures and electronic devices - Google Patents

Abstract

The application discloses an MEMS packaging structure and electronic equipment. The MEMS packaging structure comprises a substrate, a cover body, an MEMS chip and an ASIC chip, wherein an open pore structure is arranged on the substrate, the cover body is arranged on the first surface of the substrate, a containing cavity is formed between the cover body and the substrate, the MEMS chip is located in the containing cavity and is arranged on the first surface of the substrate, the ASIC chip is embedded in the substrate, and the ASIC chip is provided with a first bonding pad which is arranged opposite to the open pore structure and is electrically connected to the MEMS chip through wiring of the open pore structure. The MEMS packaging structure provided by the application can improve the performance of devices when being used for microphone products.

Description

MEMS packaging structure and electronic equipment

Technical Field

The application belongs to the technical field of MEMS structures, and particularly relates to a packaging structure and electronic equipment.

Background

In the conventional MEMS (Micro-Electro-MECHANICAL SYSTEMS, micro-Electro-mechanical system) package structure, a MEMS chip and an ASIC (Application-SPECIFIC INTEGRATED Circuit) chip are typically mounted on a PCB in parallel, and then a case is soldered on the PCB. This packaging approach can result in a larger product size, and the two chips are in the same space, which can result in the heat generated by the ASIC chip affecting the performance of the MEMS chip, resulting in reduced product performance.

In order to solve the above problems, in the prior art, an ASIC chip is embedded in a substrate, but the high impedance pin of the ASIC chip may cause problems of parasitic capacitance and leakage, which reduces the performance of the product.

Disclosure of Invention

The application aims to provide a MEMS packaging structure and electronic equipment, which at least solve one of the problems in the background art.

In order to solve the technical problems, the application is realized as follows:

according to a first aspect of the present application, there is provided a MEMS package structure comprising:

a substrate, wherein a first surface of the substrate is provided with an open pore structure;

the cover body is buckled on the first surface and forms a containing cavity with the substrate;

the MEMS chip is positioned in the accommodating cavity and is arranged on the first surface of the substrate;

The ASIC chip is embedded in the substrate and is provided with a first bonding pad, and the first bonding pad is exposed out of the first surface through the open pore structure so as to be electrically connected with the MEMS chip through the open pore structure wire.

Optionally, the first bonding pads are provided in plurality, the open pore structure is provided with one, and the plurality of first bonding pads are electrically connected with the MEMS chip through one open pore structure wire, or

The number of the open pore structures corresponding to the number of the first bonding pads is multiple, and the first bonding pads are respectively and correspondingly electrically connected with the MEMS chip through the open pore structure wires.

Optionally, in the thickness direction of the substrate, the open-pore structure includes a first open pore and a second open pore which are communicated, the number of the first open pores is the same as that of the first bonding pads, and the projection of each first open pore in the thickness direction of the substrate falls into the second open pore;

the first bonding pads are respectively and electrically connected with the MEMS chip through gold wires, and the gold wires penetrate through the first holes in a one-to-one correspondence mode and jointly penetrate through the second holes, so that the first bonding pads are electrically connected with the MEMS chip in a wiring mode.

Optionally, in the thickness direction of the substrate, the projection of the first bonding pad on the substrate falls into the inner side of the open pore structure completely, and the distance between the first bonding pad and the edge of the open pore structure is 30-100 μm.

Optionally, in a thickness direction of the substrate, a projection of the ASIC chip on the substrate at least partially overlaps a projection of the MEMS chip on the substrate.

Optionally, the substrate includes a conductive structure, a first end of the conductive structure being located inside the substrate, a second end extending from the inside of the substrate to a second surface of the substrate and forming an exposed outer pad region, the second surface being located on an opposite side of the first surface;

the ASIC chip also has a second bonding pad electrically connected with the first end of the conductive structure, and the outer bonding pad region is used for electrically connecting with an external circuit.

Optionally, the substrate further includes an insulating region and a metal region surrounding the insulating region, the conductive structure and the ASIC chip are both located in the insulating region, and the metal region is grounded.

Optionally, the second pad is located at a side of the ASIC chip facing the first surface, and the conductive structure bypasses the ASIC chip from a side of the ASIC chip close to the first surface to a side far from the first surface.

Optionally, the number of the second bonding pads is the same as that of the second bonding pads, and each second bonding pad is electrically connected to the second surface through each conductive structure in a one-to-one correspondence mode.

According to a second aspect of the present application, there is provided an electronic device comprising the MEMS package structure of the first aspect.

In the embodiment of the application, the first pad of the ASIC chip can be exposed out of the first surface of the substrate by arranging the open pore structure on the first surface of the substrate and embedding the ASIC chip in the substrate, so that the first pad and the MEMS chip are electrically connected by directly penetrating the open pore structure through the wiring, and the electrical connection of the ASIC chip and the MEMS chip is realized.

The ASIC chip is embedded in the substrate, so that the performance of the MEMS chip is prevented from being influenced by heat generated by the ASIC chip, the occupation of the space of the accommodating cavity is saved, the performance of the MEMS chip is improved, and the volume of the packaging structure is reduced. Meanwhile, the first bonding pad can be directly connected with the MEMS chip through the open pore structure, so that parasitic capacitance and leakage caused by high-impedance pins of the ASIC chip are avoided, and SNR and acoustic performance of the product are improved.

Additional aspects and advantages of the application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the application.

Drawings

The foregoing and/or additional aspects and advantages of the application will become apparent and may be better understood from the following description of embodiments taken in conjunction with the accompanying drawings in which:

fig. 1 is a top view of a MEMS package structure (without a cover) provided by the present application.

FIG. 2 is a cross-sectional view of the MEMS package structure provided by the present application at G-G in FIG. 1;

FIG. 3 is an enlarged view of a portion of FIG. 2 at A;

FIG. 4 is a cross-sectional view of the MEMS package structure provided by the present application taken at B-B in FIG. 3;

FIG. 5 is a cross-sectional view of the MEMS package structure provided by the present application taken at C-C in FIG. 3;

FIG. 6 is a cross-sectional view of the MEMS package structure provided by the present application taken at D-D in FIG. 3;

FIG. 7 is a schematic diagram of the connection of the ASIC chip of FIG. 6 to a conductive structure;

FIG. 8 is a cross-sectional view of the MEMS package structure provided by the present application taken at E-E in FIG. 3;

FIG. 9 is a cross-sectional view of the MEMS package structure provided by the present application taken at F-F in FIG. 3;

fig. 10 is a schematic structural diagram of a second surface of the substrate provided by the present application.

Reference numerals:

1. Substrate, 11, open pore structure, 111, first open pore, 112, second open pore, 12, conductive structure, 13, metal area, 14, outer bonding pad area, 15, insulating area, 16, first surface, 17, second surface, 18, grounding pad, 2, cover, 21, accommodating cavity, 3, MEMS chip, 4, ASIC chip, 41, first pad, 42, second pad, 421, VDD wire, 422, DATA wire, 423, CLK wire, 424, L/R wire, 5, gold wire.

Detailed Description

Reference will now be made in detail to embodiments of the present application, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to like or similar elements throughout or elements having like or similar functionality. The embodiments described below by referring to the drawings are illustrative only and are not to be construed as limiting the application. All other embodiments, which are obtained by a person skilled in the art based on the embodiments of the present application, fall within the scope of protection of the present application.

The features of the application "first", "second" and the like in the description and in the claims may be used for the explicit or implicit inclusion of one or more such features. In the description of the present application, unless otherwise indicated, the meaning of "a plurality" is two or more. Furthermore, in the description and claims, "and/or" means at least one of the connected objects, and the character "/", generally means that the associated object is an "or" relationship.

In the description of the present application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings are merely for convenience in describing the present application and simplifying the description, and do not indicate or imply that the device or element being referred to must have a specific orientation, be configured and operated in a specific orientation, and therefore should not be construed as limiting the present application.

In the description of the present application, unless explicitly stated or limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected, mechanically connected, electrically connected, directly connected, indirectly connected via an intervening medium, or in communication between two elements. The specific meaning of the above terms in the present application will be understood in specific cases by those of ordinary skill in the art.

A MEMS package structure and an electronic device according to an embodiment of the present application are described below with reference to fig. 1 to 10.

As shown in fig. 1 to 10, according to a first aspect of the present application, there is provided a MEMS package structure, including a substrate 1, a cover 2, a MEMS chip 3 and an ASIC chip 4, wherein a first surface 16 of the substrate 1 is provided with an open hole structure 11, the cover 2 is fastened to the first surface 16 and forms a receiving cavity 21 with the substrate 1, the MEMS chip 3 is located in the receiving cavity 21 and is disposed on the first surface 16 of the substrate 1, the ASIC chip 4 is embedded in the substrate 1 and has a first bonding pad 41, and the first bonding pad 41 is exposed to the first surface 16 through the open hole structure 11 so as to be electrically connected with the MEMS chip 3 through routing of the open hole structure 11.

Specifically, in the present embodiment, by embedding the ASIC chip 4 inside the substrate 1, compared to directly disposing it on the first surface 16 of the substrate 1, on one hand, the occupied space in the accommodating cavity 21 is saved, so that when the MEMS package structure is applied to a microphone product, the accommodating cavity 21 serves as a back cavity of the product, the back cavity can be increased, the SNR (Signal-to-Noise Ratio) of the product can be improved, and on the other hand, the heat generated by the ASIC chip 4 is avoided from interfering with the MEMS chip 3, and the SNR of the product is further improved. The higher the SNR of the microphone product is, the clearer and purer the sound is, the stronger the anti-interference capability is, and the recording effect is more excellent especially in a noisy environment.

It can be appreciated that when the ASIC chip 4 is embedded inside the substrate 1, referring to fig. 2, it can be disposed overlapping or overlapping the MEMS chip 3 in the thickness direction (X direction in fig. 2) of the substrate 1, compared to directly disposing the ASIC chip 4 on the first surface 16 of the substrate 1 without being disposed side by side with the MEMS, facilitating miniaturization of the MEMS package structure. And when the MEMS package structure is used for a microphone product, the ASIC chip 4 is embedded inside the substrate 1, so that the Anti-RF (radio frequency interference resistance) capability of the product can be enhanced.

Further, in the present embodiment, the substrate 1 is provided with the open-pore structure 11 connected to the first surface 16, and when the ASIC chip 4 is embedded in the substrate 1, the first pad 41 may be exposed to the first surface 16 of the substrate 1 through the open-pore structure 11, referring to fig. 1 to 3, that is, the first pad 41 is opposite to the open-pore structure 11 and may be directly contacted with the outside, so that the MEMS chip 3 may be directly electrically connected to the first pad 41 through a trace, for example, connecting the first pad 41 and the MEMS chip 3 through the gold wire 5, so as to achieve an electrical connection with the ASIC chip 4.

In the form of directly connecting the ASIC chip 4 and the MEMS chip 3 through the wiring of the open-pore structure 11, compared with the form of arranging the ASIC chip 4 inside the substrate 1, the MEMS chip 3 and the ASIC chip 4 are connected by arranging the bonding pad on the substrate 1, so that parasitic capacitance is avoided under the condition of high impedance, leakage is avoided, safety and reliability of the MEMS packaging structure are improved, and acoustic performance of the product is ensured. In addition, the process and the material cost for manufacturing the bonding pad on the substrate 1 can be saved, and the production cost of the MEMS packaging structure is reduced.

For example, as shown in fig. 1, in one embodiment, the ASIC chip 4 has three pads (first pads 41) for Vmic, vin and Vsub connected to the MEMS chip 3, where both pads are high impedance pins, when the ASIC chip 4 is embedded in the substrate 1, if connected to the MEMS chip 3 through the pads of the first surface 16 of the substrate 1, parasitic capacitance is generated, so that the SNR when the MEMS package structure is used for a microphone is correspondingly reduced.

In the application, the open pore structure 11 is arranged on the first surface 16 of the substrate 1, so that three bonding pads of Vmic, vin and Vsub of the ASIC chip 4 can be directly electrically connected with the MEMS chip 3 through the gold wire 5, thereby avoiding parasitic capacitance, avoiding leakage and improving the acoustic performance and safety of the product. In addition, the cost of RDL (Re-distribution Layer) for arranging the bonding pads on the substrate 1 is saved, and the production cost is reduced.

It will be appreciated that in the above embodiments, the first pads 41 are exposed on the first surface 16 of the substrate 1, which means that the connection to the outside can be made directly, and does not represent a requirement that the first pads 41 protrude from the first surface 16 of the substrate 1 or are flush with the first surface 16, but alternatively the surface of the first pads 41 is generally lower than the first surface 16 of the substrate 1, so that the open-cell structure 11 can protect the first pads 41.

Alternatively, as shown in fig. 1 to 2, the first bonding pads 41 are provided in plurality, the open-pore structure 11 is provided with one, the plurality of first bonding pads 41 are electrically connected with the MEMS chip 3 through one open-pore structure 11 wiring, or the open-pore structure 11 is provided in plurality corresponding to the number of the first bonding pads 41, and the plurality of first bonding pads 41 are respectively electrically connected with the MEMS chip 3 through the plurality of open-pore structure 11 wiring in a one-to-one correspondence.

Specifically, in the present embodiment, three first pads 41, that is, three pins of Vmic, vin, and Vsub, are typically provided when the ASIC chip 4 is connected to the MEMS chip 3. In practical application, only one open pore structure 11 may be provided, and gold wires 5 electrically connected to the MEMS chip 3 by the plurality of first bonding pads 41 all pass through the same open pore structure 11, so that the process of the substrate 1 in the processing procedure is simpler, and the process requirement and the production cost are reduced.

In another embodiment, a plurality of open structures 11 may be provided corresponding to the number of the first pads 41, for example, three open structures 11 are provided corresponding to three pins of Vmic, vin and Vsub, and the three pins are electrically connected with the connection gold wires 5 of the MEMS chip 3 respectively through one of the open structures 11. This way of opening can further reduce the heat generated by the ASIC from being transferred into the receiving cavity 21, avoiding too much affecting the performance of the MEMS chip 3, and in addition, further enhancing the Anti-RF capability of the product due to the increased coverage of the ASIC chip 4.

In the above embodiments, the number or form of the open cell structures 11 may be selected to be adaptively designed according to the specific requirements of the product, cost control, etc., and is not limited thereto. In addition, the shape of the open structure 11 may be a circle, a square, or other shape, and may be sized to completely cover the first pad 41, which is not limited in this regard.

Alternatively, as shown in fig. 2 to 3, in the thickness direction of the substrate 1, the open-pore structure 11 includes a first opening 111 and a second opening 112 that are connected, the number of the first bonding pads 41 is the same as the number of the first bonding pads 41, and projections of the first openings 111 in the thickness direction of the substrate 1 fall into the second opening 112, wherein the plurality of first bonding pads 41 are electrically connected with the MEMS chip 3 through gold wires 5, and the gold wires 5 pass through the first openings 111 one by one and pass through the second openings 112 in a common way, so that the first bonding pads 41 are electrically connected with the MEMS chip 3.

Specifically, in the present embodiment, the open-pore structure 11 is configured as a first open pore 111 and a second open pore 112 that are in communication, the first open pore 111 is located inside the substrate 1, and the second open pore 112 communicates the first open pore 111 to the first surface 16 of the substrate 1, so that the gold wires 5 connected to each first bonding pad 41 can respectively pass through one of the first open pores 111 first, then jointly pass out of the first surface 16 of the substrate 1 from the second open pore 112 and are connected to the MEMS chip 3. The first openings 111 are configured to avoid the mutual interference between the wires 5 and other wires or conductive structures 12 inside the substrate 1, and the second openings 112 are configured to facilitate the wires 5 to be led out to the substrate 1 and connected to the MEMS chip 3.

In some embodiments, the substrate 1 and the ASIC chip 4 are manufactured integrally, that is, the ASIC chip 4 is embedded in the substrate 1 during the production process of the substrate 1, and the substrate 1 is manufactured layer by layer, so that the first opening 111 is more convenient to be disposed, and after the substrate 1 is manufactured, only the second opening 112 needs to be disposed at the position of the first surface 16 of the substrate 1 corresponding to the first opening 111. Wherein, each first opening 111 needs to fall in the second opening 112, and a certain distance is left between the edge of the second opening 112, so as to facilitate the connection between the subsequent gold wire 5 and the first bonding pad 41 and the MEMS chip 3.

Alternatively, as shown in fig. 1, 3 and 4, in the thickness direction of the substrate 1, the projection of the first pad 41 on the substrate 1 falls entirely inside the open structure 11 and is spaced from the edge of the open structure 11 by 30 μm to 100 μm.

Specifically, in the present embodiment, the first bonding pad 41 falls entirely inside the open-cell structure 11, that is, means that the first bonding pad 41 is entirely exposed inside the open-cell structure 11, so that the operation is facilitated when the gold wire 5 is connected to the first bonding pad 41 and the MEMS chip 3. Meanwhile, a certain gap is reserved between the first bonding pad 41 and the edge of the open pore structure 11, interference or abrasion between the gold wire 5 and the open pore structure 11 can be avoided, and connection reliability is improved.

The distance between the edge of the first pad 41 and the edge of the open hole structure 11 may be generally set to 30 μm to 100 μm, for example, 40 μm, 50 μm, 80 μm, etc., and an excessive distance may cause the open hole structure 11 to be too large, so that the heat generated by the ASIC still may affect the performance of the MEMS chip 3, and affect the effect of embedding the ASIC chip 4 into the substrate 1. The too small distance can cause inconvenient connection of the gold wires 5, and the distance is set within 30-100 μm, so that the embedding effect can be ensured, and the convenience of assembly can be considered.

Alternatively, as shown in fig. 2, in the thickness direction of the substrate 1, the projection of the ASIC chip 4 onto the substrate 1 at least partially overlaps with the projection of the MEMS chip 3 onto the substrate 1.

Specifically, in the present embodiment, the ASIC chip 4 is embedded inside the substrate 1 so that it can be overlapped or overlapped with the MEMS chip 3 in the thickness direction of the substrate 1, reducing the size of the entire package structure, facilitating miniaturization of the product. In practical applications, the first pads 41 of the ASIC chip 4 may be reserved at positions outside the MEMS chip 3, so that the first pads 41 leak out of the first surface 16 from the open-pore structure 11 to be electrically connected to the MEMS chip 3 by routing.

Alternatively, as shown in fig. 2 to 10, the substrate 1 comprises a conductive structure 12, a first end of the conductive structure 12 is located inside the substrate 1, a second end extends from the inside of the substrate 1 to a second surface 17 of the substrate 1 and forms an exposed outer pad area 14, the second surface 17 is located on the opposite side of the first surface 16, the ASIC chip 4 further has a second pad 42, the second pad 42 is electrically connected to the first end of the conductive structure 12, and the outer pad area 14 is used for electrical connection with an external circuit.

Specifically, in the present embodiment, the electrical connection between the ASIC chip 4 and the substrate 1 is achieved through the conductive structure 12 inside the substrate 1, so that the ASIC chip 4 does not need to draw the second pad 42 out to the first surface 16 of the substrate 1, and the first surface 16 of the substrate 1 does not need to reserve a connection position or a setting position of the second pad 42, thereby further reducing the size of the substrate 1.

Further, the first end of the conductive structure 12 is located inside the substrate 1, and the second end extends from the inside of the substrate 1 to the second surface 17 of the substrate 1 to form the outer pad region 14, so that the ASIC chip 4 is electrically connected with the first end of the conductive structure 12, i.e. the electrical connection between the ASIC chip 4 and the substrate 1 is simplified by the outer pad. The conductive structure 12 may be a conductive member such as gold wire, and may be manufactured and laid together during the manufacturing process of the substrate 1.

Optionally, as shown in fig. 5 to 6, the substrate 1 further includes an insulating region 15 and a metal region 13 surrounding the insulating region 15, where the conductive structure 12 and the ASIC chip 4 are both located in the insulating region 15, and the metal region 13 is grounded.

Specifically, in this embodiment, the substrate 1 has the insulating region 15 and the metal region 13 outside the insulating region 15, and the metal region 13 is grounded through the grounding pad 18 on the second surface 17 of the substrate 1, so that the metal region 13 can form a metal shield for the ASIC chip 4 located in the insulating region 15, interference of signals such as various antennas outside the substrate 1 is avoided, anti-RF capability of the MEMS package structure when the MEMS package structure is used for a microphone is further improved, and acoustic performance of the product is improved. In addition, the conductive structure 12 is also located in the insulating region 15, which facilitates the arrangement of the conductive structure 12.

Alternatively, as shown in fig. 2 to 3, the second pad 42 is located on a side of the ASIC chip 4 facing the first surface 16, and the conductive structure 12 bypasses the ASIC chip 4 from a side of the ASIC chip 4 close to the first surface 16 to a side remote from the first surface 16.

Specifically, in the present embodiment, the first pad 41 and the second pad 42 on the ASIC chip 4 are both located on the side close to the first surface 16 of the substrate 1, the first pad 41 is located on the side close to the first surface 16 of the substrate 1 so as to expose the first surface 16 through the open structure 11 and connect with the MEMS chip 3, and the second pad 42 needs to be connected to the first end of the conductive structure 12 and then connected to the outer pad area 14 through the conductive structure 12.

In an actual connection, the first end of the conductive structure 12 is connected to the first pad 41, which itself needs to be wound from the upper side of the ASIC chip 4 to the lower side of the ASIC chip 4, i.e. the side of the ASIC chip 4 remote from the first surface 16, compared to the second pad 42 leading to the first surface 16 of the substrate 1 and then to the second surface 17, both simplifying the connection of the ASIC chip 4 to the substrate 1 and reducing the size of the package structure.

Alternatively, as shown in fig. 5 to 10, the second pads 42 are provided in plural numbers, the number of the conductive structures 12 is the same as the number of the second pads 42, and each of the second pads 42 is electrically connected to the second surface 17 through each of the conductive structures 12 in one-to-one correspondence.

Specifically, in practical applications, the connection of the ASIC chip 4 to an external circuit generally requires a plurality of second pads 42 to achieve a specific function. As shown in fig. 5 to 9, the ASIC chip 4 is provided with four second pads 42, and leads from the inside of the substrate 1 to the second surface 17 of the substrate 1 through VDD trace 421, DATA trace 422, CLK trace 423 and L/R trace 424 (conductive structure 12), respectively, to form the outer pad region 14, where the connection of each of the foregoing traces needs to be respectively connected to one second pad 42 and then approach the first surface 16 of the substrate 1, and further bypass the ASIC chip 4 and then extend in a direction approaching the second surface 17 of the substrate 1, and finally lead to the four outer pad regions 14. I.e. to the outer pad area 14 in the sequence of fig. 6-5-6-8-9-10.

According to a second aspect of the present application there is provided an electronic device comprising the MEMS package structure of the first aspect.

Specifically, in the present embodiment, the MEMS package structure is used in a microphone product or a combination sensor (for example, a combination of pressure and microphone), the ASIC chip 4 based on the package structure is embedded inside the substrate 1 and directly connected to the MEMS chip 3 through the wiring, so that the acoustic performance and Anti-RF capability of microphone work are improved, and at the same time, the size thereof can be reduced and the problems of parasitic capacitance and electric leakage thereof can be avoided, so that when these products are applied to electronic devices, the acoustic performance and reliability of acoustic functions of the products can be improved. The electronic device may be a smart phone, a tablet computer, etc., which is not limited in the present application.

In the description of the present specification, reference to the terms "one embodiment," "some embodiments," "illustrative embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the application. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiments or examples. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

Although embodiments of the present application have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made therein without departing from the spirit and scope of the application as defined by the appended claims and their equivalents.

Claims (10)

1. A MEMS package structure, comprising:

a substrate, wherein a first surface of the substrate is provided with an open pore structure;

the cover body is buckled on the first surface and forms a containing cavity with the substrate;

the MEMS chip is positioned in the accommodating cavity and is arranged on the first surface of the substrate;

The ASIC chip is embedded in the substrate and is provided with a first bonding pad, and the first bonding pad is exposed out of the first surface through the open pore structure so as to be electrically connected with the MEMS chip through the open pore structure wire.

2. The MEMS package structure of claim 1, wherein a plurality of first pads are provided, one of the open-pore structures is provided, and a plurality of the first pads are electrically connected with the MEMS chip through one of the open-pore structure traces, or

The number of the open pore structures corresponding to the number of the first bonding pads is multiple, and the first bonding pads are respectively and correspondingly electrically connected with the MEMS chip through the open pore structure wires.

3. The MEMS package structure of claim 1, wherein the open-cell structure includes, in a thickness direction of the substrate, first openings and second openings that communicate, the first pads are provided in plurality, the number of the first openings is the same as the number of the first pads, and projections of the first openings in the thickness direction of the substrate fall within the second openings;

the first bonding pads are respectively and electrically connected with the MEMS chip through gold wires, and the gold wires penetrate through the first holes in a one-to-one correspondence mode and jointly penetrate through the second holes, so that the first bonding pads are electrically connected with the MEMS chip in a wiring mode.

4. The MEMS package structure of claim 1, wherein a projection of the first pad onto the substrate in a thickness direction of the substrate falls entirely inside the open-cell structure and is spaced apart from an edge of the open-cell structure by 30 μm to 100 μm.

5. The MEMS package structure of claim 1, wherein a projection of the ASIC chip onto the substrate and a projection of the MEMS chip onto the substrate overlap at least partially in a thickness direction of the substrate.

6. The MEMS package structure of claim 1 wherein the substrate includes a conductive structure having a first end located inside the substrate and a second end extending from the inside of the substrate to a second surface of the substrate and forming an exposed outer land area, the second surface being located on an opposite side of the first surface;

the ASIC chip also has a second bonding pad electrically connected with the first end of the conductive structure, and the outer bonding pad region is used for electrically connecting with an external circuit.

7. The MEMS package structure of claim 6, wherein the substrate further comprises an insulating region and a metal region surrounding the insulating region, the conductive structure and the ASIC chip are both located in the insulating region, and the metal region is grounded.

8. The MEMS package of claim 6 wherein the second pad is located on a side of the ASIC chip facing the first surface, the conductive structure bypassing the ASIC chip from a side of the ASIC chip proximate to the first surface to a side remote from the first surface.

9. The MEMS package structure of claim 6, wherein the second pads are provided in plurality, the number of the conductive structures is the same as the number of the second pads, and each of the second pads is electrically connected to the second surface through each of the conductive structures in one-to-one correspondence.

10. An electronic device comprising the MEMS package structure of any one of claims 1-9.