CN120406850A - Data access method and storage device - Google Patents

Abstract

The invention provides a data access method and a storage device. The method includes generating first verification information according to target data and first logic unit information in response to a data access event, wherein the data access event indicates to store the target data to a memory module or read the target data from the memory module, generating second verification information according to the target data and second logic unit information in a second verification position in the memory device, wherein the second verification position is different from the first verification position, performing a verification operation according to the first verification information and the second verification information to obtain a verification result, and performing an operation corresponding to the data access event according to the verification result. Therefore, the accuracy of data transmission can be ensured, and the operation stability of the storage device is further improved.

Description

Data access method and storage device

Technical Field

The present invention relates to the field of storage technologies, and in particular, to a data access method and a storage device.

Background

With the development of technology, the use of memory devices including non-volatile memory modules (e.g., flash memory modules) is becoming increasingly popular. Generally, a host system instructs a storage device to read, store or delete user data stored at a logical address (e.g., a logical block address) by matching an operation instruction with the logical address. Most storage devices support error correction (e.g., decoding) for user data to avoid accessing erroneous user data.

However, storage devices generally lack an integrity verification mechanism for logical addresses. Therefore, when the logic address has an integrity problem, an access error occurs when the memory module is accessed based on the logic address, thereby reducing the operation stability of the memory device.

Disclosure of Invention

The invention provides a data access method and a storage device, which can improve the problems and further improve the operation stability of the storage device.

An embodiment of the present invention provides a data access method for a storage device, wherein the storage device is connected to a host system, the storage device includes a memory module, and the data access method includes generating first verification information at a first verification location inside the storage device according to target data and first logical unit information corresponding to the target data in response to a data access event, wherein the data access event indicates to store the target data to the memory module or read the target data from the memory module, generating second verification information at a second verification location inside the storage device according to the target data and second logical unit information corresponding to the target data, wherein the second verification location is different from the first verification location, performing a verification operation according to the first verification information and the second verification information to obtain a verification result, and performing an operation corresponding to the data access event according to the verification result.

The embodiment of the invention further provides a storage device, which comprises a connection interface, a memory module and a memory controller. The connection interface is used for connecting to a host system. The memory controller is connected to the connection interface and the memory module. The memory controller is configured to generate first verification information at a first verification location within the memory device according to target data and first logical unit information corresponding to the target data in response to a data access event indicating that the target data is stored to or read from the memory module, generate second verification information at a second verification location within the memory device according to the target data and second logical unit information corresponding to the target data, wherein the second verification location is different from the first verification location, perform a verification operation according to the first verification information and the second verification information to obtain a verification result, and perform an operation corresponding to the data access event according to the verification result.

Drawings

FIG. 1 is a schematic diagram of a data storage system shown in accordance with an embodiment of the present invention;

FIG. 2 is a schematic diagram of a memory controller shown according to an embodiment of the present invention;

FIG. 3 is a schematic diagram of a managed memory module shown in accordance with an embodiment of the present invention;

FIG. 4 is a schematic diagram of a memory control circuit including a first controller and a second controller according to an embodiment of the present invention;

FIGS. 5 and 6 are schematic diagrams illustrating an operational scenario for a data write event according to embodiments of the present invention;

FIGS. 7-9 are operational context diagrams for data read events, shown in accordance with embodiments of the present invention;

Fig. 10 is a flowchart of a data access method according to an embodiment of the present invention.

Detailed Description

Reference will now be made in detail to the exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings and the description to refer to the same or like parts.

FIG. 1 is a schematic diagram of a data storage system shown in accordance with an embodiment of the present invention. Referring to fig. 1, a data storage system 10 includes a host system 11 and a storage device 12. The storage device 12 may be connected to the host system 11 and may be used to store data from the host system 11. For example, the host system 11 may be a smart phone, a tablet computer, a notebook computer, a desktop computer, an industrial computer, a game machine, a server, or a computer system provided in a specific carrier (e.g., a vehicle, an aircraft, or a ship), or the like, and the type of the host system 11 is not limited thereto. Further, the storage device 12 may include a solid state disk, a USB flash drive, a memory card, or other type of non-volatile storage device.

The memory device 12 includes a connection interface 121, a memory module 122, and a memory controller 123. The connection interface 121 is used to connect the storage device 12 to the host system 11. For example, connection interface 121 may support an embedded multimedia card (embedded Multi-MEDIA CARD, EMMC), universal flash memory (Universal Flash Storage, UFS), peripheral component interconnect Express (PERIPHERAL COMPONENT INTERCONNECT EXPRESS, PCI Express), non-volatile memory Express (Non-Volatile Memory Express, NVM Express), serial advanced technology attachment (SERIAL ADVANCED Technology Attachment, SATA), universal serial bus (Universal Serial Bus, USB), or other types of connection interface standards. Accordingly, storage device 12 may communicate (e.g., exchange signals, instructions, and/or data) with host system 11 via connection interface 121.

The memory module 122 is used for storing data. For example, the memory module 122 may include one or more rewritable non-volatile memory modules. Each of the rewritable non-volatile memory modules may include one or more memory cell arrays. Memory cells in a memory cell array store data in the form of voltages (also referred to as threshold voltages). For example, the memory module 122 may include a single level memory cell (SINGLE LEVEL CELL, SLC) NAND-type flash memory module, a second level memory cell (Multi LEVEL CELL, MLC) NAND-type flash memory module, a third level memory cell (TRIPLE LEVEL CELL, TLC) NAND-type flash memory module, a fourth level memory cell (Quad LEVEL CELL, QLC) NAND-type flash memory module, and/or other memory modules having the same or similar characteristics.

The memory controller 123 is connected to the connection interface 121 and the memory module 122. Memory controller 123 may be considered a control core of storage device 12 and may be used to control storage device 12. For example, the memory controller 123 may be used to control or manage the operation of the storage device 12 in whole or in part. For example, the memory controller 123 may include a central processing unit (Central Processing Unit, CPU), or other programmable general purpose or special purpose microprocessor, digital signal Processor (DIGITAL SIGNAL Processor, DSP), programmable controller, application SPECIFIC INTEGRATED Circuits (ASIC), programmable logic device (Programmable Logic Device, PLD), or other similar device or combination of devices. In an embodiment, the memory controller 123 may comprise a flash memory controller.

Memory controller 123 may send a sequence of instructions to memory module 122 to access memory module 122. For example, memory controller 123 may send a sequence of write instructions to memory module 122 to instruct memory module 122 to store data in a particular memory location. For example, memory controller 123 can send a sequence of read instructions to memory module 122 to instruct memory module 122 to read data from a particular memory location. For example, memory controller 123 can send a sequence of erase instructions to memory module 122 to instruct memory module 122 to erase data stored in a particular memory cell. In addition, memory controller 123 may send other types of instruction sequences to memory module 122 to instruct memory module 122 to perform other types of operations, as the invention is not limited. The memory module 122 may receive a sequence of instructions from the memory controller 123 and access memory locations within the memory module 122 according to the sequence of instructions.

FIG. 2 is a schematic diagram of a memory controller according to an embodiment of the invention. Referring to fig. 1 and 2, the memory controller 123 includes a host interface 21, a memory interface 22, and a memory control circuit 23. The host interface 21 is used to connect to the host system 11 through the connection interface 121 to communicate with the host system 11. The memory interface 22 is used to connect to the memory module 122 to access the memory module 122.

The memory control circuit 23 is connected to the host interface 21 and the memory interface 22. The memory control circuit 23 may be used to control or manage the operation of the memory controller 123 in whole or in part. For example, the memory control circuit 23 may communicate with the host system 11 through the host interface 21 and access the memory module 122 through the memory interface 22. For example, the memory control circuit 23 may include a control circuit such as an embedded controller or a microcontroller. In the following embodiment, the explanation of the memory control circuit 23 is equivalent to the explanation of the memory controller 123.

In one embodiment, memory controller 123 may also include buffer memory 24. The buffer memory 24 is connected to the memory control circuit 23 and is used for buffering data. For example, buffer memory 24 may be used to buffer instructions from host system 11, data from host system 11, and/or data from memory module 122.

In an embodiment, the memory controller 123 may also include a decoding circuit 25. The decoding circuit 25 is connected to the memory control circuit 23 and performs encoding and decoding of data to ensure the correctness of the data. For example, the decoding circuit 25 may support various encoding/decoding algorithms such as Low DENSITY PARITY CHECK codes (LDPC codes), BCH codes, reed-solomon codes (RS codes), and Exclusive OR (XOR) codes. In one embodiment, the memory controller 123 may also include various circuit modules of other types (e.g., power management circuits, etc.), which are not limiting.

FIG. 3 is a schematic diagram illustrating managing memory modules according to an embodiment of the invention. Referring to fig. 1 to 3, the memory module 122 includes a plurality of physical units 301 (1) to 301 (B). Each physical unit comprises a plurality of memory cells and is used for nonvolatile memory data.

In one embodiment, a physical unit may include one or more physical programming units. In one embodiment, a physical erase unit may include one or more physical program units.

In one embodiment, a physical programmer may include a plurality of physical sectors (sectors). For example, a physical sector may have a data size of 512 Bytes (Bytes), and a physical programming unit may include 32 physical sectors. However, the data capacity of one physical fan and/or the total number of physical fans included in one physical programming unit can be adjusted according to the practical requirements, and the present invention is not limited thereto. In one embodiment, a physical programmer may be considered a physical page. For example, the storage capacity of one physical programming unit may be 16 kilobytes, and the present invention is not limited thereto.

In one embodiment, one physical programmer is the minimum unit of synchronous write data in the memory module 122. For example, when performing a programming operation (also referred to as a write operation) on a physical programming unit to write data into the physical programming unit, a plurality of memory cells in the physical programming unit may be synchronously programmed to store corresponding data. For example, when programming a physical programming unit, a write voltage may be applied to the physical programming unit to change the threshold voltage of at least some of the memory cells in the physical programming unit. For example, the threshold voltage of a memory cell may reflect the bit data stored by the memory cell.

In one embodiment, a plurality of physical program units in a physical erase unit can be erased simultaneously. For example, when performing an erase operation on a physically erased cell, an erase voltage may be applied to a plurality of physically programmed cells in the physically erased cell to change the threshold voltage of at least some of the physically programmed cells. By performing an erase operation on a physically erased cell, data stored in the physically erased cell may be erased. In one embodiment, a physical erased cell may be considered a physical block.

In one embodiment, the memory control circuit 23 can logically associate the physical units 301 (1) to 301 (A) and 301 (A+1) to 301 (B) to the data area 31 and the idle area 32, respectively. The physical units 301 (1) -301 (a) in the data area 31 all store data (also referred to as user data) from the host system 11. For example, any entity in the data area 31 may store valid (valid) data and/or invalid (invalid) data. In addition, none of the physical units 301 (a+1) -301 (B) in the spare area 32 stores data (e.g., valid data).

In one embodiment, if a certain physical unit does not store valid data, the physical unit may be associated with the idle area 32. In addition, the physical cells in the spare area 32 may be erased to erase the data in the physical cells. In one embodiment, the physical units in the idle region 32 are also referred to as idle physical units. In one embodiment, the free area 32 is also referred to as a free pool (free pool).

In one embodiment, when data is to be stored, the memory control circuit 23 may select one or more physical units from the idle area 32 and instruct the memory module 122 to store the data in the selected physical units. After storing the data in the physical unit, the physical unit may be associated with the data area 31. In other words, one or more physical units may be used alternately between the data area 31 and the idle area 32.

In one embodiment, the memory control circuit 23 may configure a plurality of logic units 302 (1) -302 (C) to map physical units (i.e., physical units 301 (1) -301 (A)) in the data area 31. For example, a logical unit may correspond to a logical block address (Logical Block Address, LBA) or other logical management unit. One logical unit may be mapped to one or more physical units.

In one embodiment, if a physical unit is currently mapped by any logical unit, the memory control circuit 23 may determine that the data currently stored in the physical unit includes valid data. Conversely, if a physical unit is not currently mapped by any logical unit, the memory control circuit 23 may determine that the physical unit does not currently store any valid data.

In one embodiment, the memory control circuit 23 may record the mapping relationship between the logical unit and the physical unit in at least one management table (also referred to as a logical-to-physical mapping table). In one embodiment, the memory control circuit 23 instructs the memory module 122 to perform data reading, writing or erasing operations according to the information in the management table (i.e. the logical-to-physical mapping table).

In one embodiment, the memory control circuit 23 may detect a data access event. The data access event indicates access to particular data (also referred to as target data). For example, the data access event may be used to indicate that target data is stored to the memory module 122 or that target data is read from the memory module 122.

In one embodiment, if the data access event is a data write event for target data, the data access event may be used to indicate that target data is stored to the memory module 122. Or in an embodiment, if the data access event is a data read event for target data, the data access event may be used to indicate that target data is read from the memory module 122.

In one embodiment, in response to the data access event, the memory control circuit 23 may dynamically generate the verification information (also referred to as the first verification information) according to the target data and the logic unit information (also referred to as the first logic unit information) corresponding to the target data at a certain verification location (also referred to as the first verification location) inside the memory device 12. For example, the first logical unit information may reflect a logical unit to which the target data belongs (e.g., at least one of the logical units 302 (1) -302 (C) of fig. 3).

In one embodiment, in the first verification position, the memory control circuit 23 may perform a logic operation (also referred to as a first logic operation) on the target data and the first logic unit information to obtain the first verification information. Or from another point of view, the first verification information may reflect an operation result (also referred to as a first operation result) of performing a first logical operation on the target data and the first logical unit information.

In one embodiment, the first check information includes a cyclic redundancy check (Cyclic redundancy check, CRC) code. For example, in the first logic operation, the memory control circuit 23 may input the target data and the first logic unit information to a generation algorithm of the cyclic redundancy check code to dynamically generate the first check information.

Thereafter, the first verification information may be used to verify the integrity of at least one of the target data and logical unit information (e.g., first logical unit information) corresponding to the target data. In an embodiment, the first verification information may further include other types of verification information, as long as the description of the embodiment of the present invention is consistent.

In one embodiment, in response to the data access event, the memory control circuit 23 may further dynamically generate another verification information (also referred to as a second verification information) according to the target data and another logic unit information (also referred to as a second logic unit information) corresponding to the target data at another verification location (also referred to as a second verification location) inside the memory device 12. It should be noted that the second verification location must be different from the first verification location.

In one embodiment, in the second verification position, the memory control circuit 23 may perform a logic operation (also referred to as a second logic operation) on the target data and the second logic unit information to obtain the second verification information. Or from another perspective, the second check information may reflect an operation result (also referred to as a second operation result) of performing a second logical operation on the target data and the second logical unit information.

In an embodiment, the second parity information also includes a Cyclic Redundancy Check (CRC) code. For example, in the second logical operation, the memory control circuit 23 may input the target data and the second logical unit information to the cyclic redundancy check code generation algorithm to dynamically generate the second check information. Thereafter, the second verification information may be used to verify the integrity of at least one of the target data and logical unit information (e.g., second logical unit information) corresponding to the target data. It should be noted that, in an embodiment, the second verification information may further include other types of verification information, so long as the description of the embodiment of the present invention is consistent.

In one embodiment, the storage device 12 may include a plurality of controllers. For example, the storage device 12 may include a first controller and a second controller. The first controller may be configured to communicate with the host system 11.

For example, the first controller may be configured to parse instructions or signals from the host system 11 and may be configured to transfer data to the host system 11. The second controller may be used to control the memory module 122. For example, the second controller may be used to control access operations of the memory device 12 to the memory module 122. For example, the access operation includes a read operation, a write operation, an erase operation, or other operations, and the present invention is not limited.

In one embodiment, the first verification location is located at the first controller and the second verification location is located at the second controller. That is, the first verification information is dynamically generated by the first controller according to the target data and the first logic unit information. In addition, the second verification information is dynamically generated by the second controller according to the target data and the second logic unit information.

In one embodiment, the first controller and the second controller may be included in the memory control circuit 23 of FIG. 2 synchronously. In one embodiment, the first controller is also referred to as a host controller and/or the second controller is also referred to as a storage controller. In one embodiment, at least one of the first controller and the second controller may also be independent of the memory control circuit 23 of fig. 2.

In one embodiment, after the first verification information and the second verification information are obtained, the memory control circuit 23 may perform a verification operation according to the first verification information and the second verification information to obtain a verification result. For example, this verification result may reflect the operation result of the verification operation. Then, the memory control circuit 23 may perform an operation corresponding to the aforementioned data access event according to the verification result.

In an embodiment, the verification operation is used to confirm whether the first verification information is identical to the second verification information. For example, the memory control circuit 23 may compare the first verification information and the second verification information to obtain the verification result. For example, the verification result may reflect whether the first verification information is identical to the second verification information.

In one embodiment, if the verification result is that the first verification information is identical to the second verification information, the memory control circuit 23 may determine that the verification result is a specific result (also referred to as a first result). In other words, the first result may reflect that the first verification information is identical to the second verification information.

In one embodiment, if the verification result is that the first verification information is different from the second verification information, the memory control circuit 23 may determine that the verification result is another result (also referred to as a second result). In other words, the second result may reflect that the first verification information is different from the second verification information.

In an embodiment, the first check information is identical to the second check information, which may mean that a Cyclic Redundancy Check (CRC) code in the first check information is identical to a Cyclic Redundancy Check (CRC) code in the second check information. In an embodiment, the first check information is different from the second check information, which may mean that a Cyclic Redundancy Check (CRC) code in the first check information is different from a Cyclic Redundancy Check (CRC) code in the second check information.

In one embodiment, the verification operation may also be used to confirm whether the first verification information and the second verification information meet a specific condition. For example, in one embodiment, if the first verification information and the second verification information meet a specific condition, the memory control circuit 23 may determine that the verification result is the first result. Or in an embodiment, if the first verification information and the second verification information do not meet the specific condition, the memory control circuit 23 may determine that the verification result is the second result.

In an embodiment, the first check information and the second check information conform to a specific condition, which may mean that after the first check information and the second check information are substituted into a specific algorithm, the output of the specific algorithm conforms to an expectation. In an embodiment, the first check information and the second check information do not meet a specific condition, which may mean that after the first check information and the second check information are substituted into a specific algorithm, the output of the specific algorithm does not meet the expectations.

In an embodiment, according to the verification result, the memory control circuit 23 may perform a preset operation corresponding to the data access event or perform an error process corresponding to the aforementioned data access event.

In one embodiment, if the data access event is a data write event for the target data and the verification result is the first result, the memory control circuit 23 may write the target data and the second logical unit information into the memory module 122 in response to the write command from the host system 11.

Or if the data access event is a data write event for target data and the verification result is a second result, the memory control circuit 23 may perform error processing corresponding to the write instruction. For example, in error processing corresponding to the write instruction, the memory control circuit 23 may send error information to the host system 11 to notify the host system 11 that writing of the target data has failed.

In one embodiment, if the data access event is a data read event for target data and the verification result is a first result, the memory control circuit 23 may transmit the target data read from the memory module 122 to the host system 11 in response to a read instruction from the host system 11.

Or if the data access event is a data read event for the target data and the verification result is a second result, the memory control circuit 23 may perform error processing corresponding to the read instruction. For example, in error processing corresponding to the read instruction, the memory control circuit 23 may send error information to the host system 11 to notify the host system 11 that the reading of the target data is failed. In addition, the implementation details of the error processing can be adjusted according to the practical requirements.

The following describes the operation performed by the first controller and the second controller in the memory control circuit 23 when the data access event is a data write event or a data read event for the target data, respectively, according to a plurality of embodiments.

FIG. 4 is a schematic diagram of a memory control circuit including a first controller and a second controller according to an embodiment of the present invention. Referring to fig. 4, it is assumed that the memory control circuit 23 includes a controller 41 (i.e., a first controller or referred to as a host controller) and a controller 42 (i.e., a second controller or referred to as a storage controller). The controller 41 may be configured to communicate with the host system 11. The controller 42 may be used to control the memory module 122. In addition, both controllers 41 and 42 can access the buffer memory 24. For example, both controllers 41 and 42 may cache data into the buffer memory 24 or read data from the buffer memory 24.

In one embodiment, the first verification location is located at the controller 41 and the second verification location is located at the controller 42. In this case, the first check information is dynamically generated by the controller 41 according to the target data and the first logical unit information. The second verification information is dynamically generated by the controller 42 according to the target data and the second logical unit information.

Thus, the method provided by the embodiment calculates the first check information and the second check information according to the target data and the first logic unit information/the second logic unit information, and uses the first check information and the second check information for security check. The accuracy of target data transmission is ensured, the reliability of data transmission is improved, the accuracy of a logic address is ensured, and the corresponding relation between target data written into a storage device and the logic address is ensured.

In one embodiment, the first verification location is located at the controller 42 and the second verification location is located at the controller 41. In this case, the first verification information is dynamically generated by the controller 42 based on the target data and the first logical unit information. The second verification information is dynamically generated by the controller 41 based on the target data and the second logical unit information.

Fig. 5 and 6 are schematic diagrams illustrating an operation scenario for a data writing event according to an embodiment of the present invention. Referring to fig. 5, after obtaining a write command 51 corresponding to a data write event from the host system 11, the controller 41 may obtain data 52 (i.e., target data) and logical unit information 53 (i.e., first logical unit information) from the write command 51. For example, assuming that logical unit information 53 reflects logical unit A, write instruction 51 may be used to instruct storage of data 52 pertaining to logical unit A.

After retrieving the data 52 and the logical unit information 53, the controller 41 may perform a logical operation 54 (i.e., a first logical operation) on the data 52 and the logical unit information 53 to dynamically generate the check information 55 (i.e., the first check information). The controller 41 may store the data 52 and the dynamically generated verification information 55 in the buffer memory 24. In addition, the controller 41 may transmit the logical unit information 53 to the controller 42 as the logical unit information 61 (i.e., the second logical unit information) in fig. 6.

Referring to fig. 6, in the embodiment of fig. 5, the controller 42 may obtain the logic unit information 61 according to the logic unit information 53 from the controller 41. In particular, the information content of the logical unit information 61 may be the same or different from the information content of the logical unit information 53.

For example, in an ideal case, the information content of the logical unit information 61 would be the same as the information content of the logical unit information 53. However, in a real situation, the information content of the logical unit information 61 may be different from the information content of the logical unit information 53, affected by channel noise. If the information content of the logical unit information 61 is different from the information content of the logical unit information 53, then a subsequent access behavior (e.g., write operation 66) to the memory module 122 based on the logical unit information 61 may occur, such as a failure to execute or a storage of erroneous data.

In one embodiment, the controller 42 may read the data 52 and the check information 55 from the buffer memory 24. The controller 42 may perform a logic operation 62 (i.e., a second logic operation) on the logical unit information 61 and the data 52 to dynamically generate the verification information 63 (i.e., the second verification information). After generating the verification information 63, the controller 42 may perform a verification operation 64 according to the verification information 55 and the verification information 63 to obtain a verification result 65.

In one embodiment, if the verification result 65 is a first result (e.g., the verification information 55 is the same as the verification information 63), the controller 42 may perform the write operation 66 in response to the write instruction 51. For example, in write operation 66, controller 42 may write data 52 and logical unit information 61 to memory module 122.

However, in one embodiment, if the verification result 65 is a second result (e.g., the verification information 55 is different from the verification information 63), the controller 41 may perform the error process 67 corresponding to the write instruction 51. For example, in error handling 67, controller 41 may send an error message to host system 11 to inform host system 11 that writing to data 52 was failed. Thus, it is ensured that the data (e.g., data 52) ultimately written to the memory module 122 is indeed the data required by the write command 51, thereby effectively improving the operational stability of the memory device 12.

Fig. 7-9 are operational context diagrams for data read events, according to embodiments of the present invention. Referring to fig. 7, after a read command 71 corresponding to a data read event is obtained from the host system 11, the controller 41 may obtain the logic unit information 72 (i.e. the first logic unit information) from the read command 71. For example, assuming that logical unit information 72 reflects logical unit B, read instruction 71 may be used to instruct reading of data belonging to logical unit B.

After obtaining the logical unit information 72, the controller 41 may obtain the physical unit information 73 corresponding to the logical unit information 72. For example, entity unit information 73 reflects entity unit C, and logical unit B maps to entity unit C. For example, controller 41 may query a management table (e.g., a logical-to-physical mapping table) based on logical unit information 72 to obtain physical unit information 73. Controller 41 may then communicate entity unit information 73 to controller 42.

Referring to fig. 8, following the embodiment of fig. 7, after obtaining the physical unit information 73, the controller 42 may access the memory module 122 according to the physical unit information 73 to obtain the data 81 (i.e. the target data) and the logical unit information 82 (i.e. the second logical unit information) from the memory module 122. The logical unit information 82 may reflect the logical unit to which the data 81 belongs. In particular, the information content of the logical unit information 82 may be the same or different than the information content of the logical unit information 72.

For example, in an ideal case, the information content of the logical unit information 82 would be the same as the information content of the logical unit information 72. However, in real-world situations, the information content of the logical unit information 82 may be different from the information content of the logical unit information 72, subject to channel noise. If the information content of the logical unit information 82 is different from the information content of the logical unit information 72, then there is a high probability that the currently read data 81 is not actually indicative of the read data by the read instruction 71. Therefore, if the information content of the logical unit information 82 is different from the information content of the logical unit information 72, a data read error may occur if the data 81 is transmitted to the host system 11.

In one embodiment, after reading the data 81 and the logical unit information 82 from the memory module 122, the controller 42 may perform a logical operation 83 (i.e., a second logical operation) on the data 81 and the logical unit information 82 to dynamically generate the check information 84 (i.e., the second check information). The controller 41 may store the data 81 and the dynamically generated verification information 84 into the buffer memory 24.

Referring to fig. 9, in the embodiment of fig. 8, the controller 41 may obtain the data 81 and the dynamically generated check information 84 from the buffer memory 24. The controller 41 may perform a logic operation 91 (i.e., a first logic operation) on the logical unit information 72 and the data 81 to dynamically generate the verification information 92 (i.e., the first verification information). After generating the verification information 92, the controller 41 may perform a verification operation 93 according to the verification information 92 and the verification information 84 to obtain a verification result 94.

In one embodiment, if the verification result 94 is a first result (e.g., the verification information 92 is identical to the verification information 84), the controller 42 may perform a transfer operation 95 in response to the read command 71. For example, in a transfer operation 95, the controller 41 may transfer the data 81 to the host system 11 in response to the read command 71. However, in one embodiment, if the verification result 94 is a second result (e.g., the verification information 92 is different from the verification information 84), the controller 41 may perform an error process 96 corresponding to the write instruction 71. For example, in error handling 96, controller 41 may send an error message to host system 11 to inform host system 11 that the read for data 81 was failed. Thus, the data (e.g., data 81) finally transmitted back to the host system 11 is ensured to be the data required by the read command 71, thereby effectively improving the operation stability of the storage device 12.

Fig. 10 is a flowchart of a data access method according to an embodiment of the present invention. Referring to fig. 10, in step S1001, first verification information is generated at a first verification location inside a storage device according to target data and first logic unit information corresponding to the target data in response to a data access event, wherein the data access event indicates to store the target data to a memory module or read the target data from the memory module.

In step S1002, second verification information is generated from the target data and second logic unit information corresponding to the target data at a second verification location inside the storage device, wherein the second verification location is different from the first verification location.

In step S1003, a verification operation is performed according to the first verification information and the second verification information to obtain a verification result.

In step S1004, an operation corresponding to the data access event is performed according to the verification result.

However, the steps in fig. 10 are described in detail above, and will not be described again here. It should be noted that each step in fig. 10 may be implemented as a plurality of program codes or circuits, and the present invention is not limited thereto. In addition, the method of fig. 10 may be used with the above exemplary embodiment, or may be used alone, and the present invention is not limited thereto.

In summary, the data access method and the storage device according to the embodiments of the present invention can allow the corresponding access operation to be performed on the premise of ensuring that the logical unit information used by the storage device is consistent with the logical unit information indicated by the host system. Therefore, the end-to-end access error (namely, error detection or error correction not aiming at user data simply) caused by the inconsistency between the logic unit information used by the storage device and the logic unit information indicated by the host system can be reduced, and the operation stability of the storage device is further improved.

It should be noted that the above embodiments are merely for illustrating the technical solution of the present invention and not for limiting the same, and although the present invention has been described in detail with reference to the above embodiments, it should be understood by those skilled in the art that the technical solution described in the above embodiments may be modified or some or all of the technical features may be equivalently replaced, and these modifications or substitutions do not make the essence of the corresponding technical solution deviate from the scope of the technical solution of the embodiments of the present invention.

Claims (20)

1. A data access method, characterized in that it is used for a storage device, wherein the storage device is connected to a host system, the storage device includes a memory module, and the data access method comprises: generating first verification information at a first verification location within the storage device based on target data and first logical unit information corresponding to the target data in response to a data access event, wherein the data access event indicates storing the target data into the memory module or reading the target data from the memory module; generating second verification information at a second verification location within the storage device according to the target data and second logical unit information corresponding to the target data, wherein the second verification location is different from the first verification location; Performing a verification operation according to the first verification information and the second verification information to obtain a verification result; and An operation corresponding to the data access event is executed according to the verification result. 2. The data access method according to claim 1, wherein the storage device includes a first controller and a second controller, the first verification position is located at the first controller, the second verification position is located at the second controller, the first controller is communicatively connected to the host system, and the second controller is used to control the memory module. 3. The data access method according to claim 1 , wherein the first verification information reflects a first operation result of a first logical operation performed on the target data and the first logical unit information, and the second verification information reflects a second operation result of a second logical operation performed on the target data and the second logical unit information. 4 . The data access method according to claim 1 , wherein the first verification information and the second verification information both comprise cyclic redundancy check codes. 5 . The data access method according to claim 1 , wherein the verification operation is used to confirm whether the first verification information is the same as the second verification information. 6. The data access method according to claim 1 , wherein the step of performing the verification operation according to the first verification information and the second verification information to obtain the verification result comprises: The first verification information and the second verification information are compared to obtain the verification result. 7. The data access method according to claim 1, further comprising: If the data access event is a data write event for the target data, a first controller within the storage device obtains the first logical unit information from a write instruction corresponding to the data write event; and The first controller transmits the first logical unit information to a second controller in the storage device as the second logical unit information. 8. The data access method according to claim 7, wherein executing the operation corresponding to the data access event according to the verification result comprises: If the verification result is the first result, writing the target data and the second logic unit information into the memory module in response to the write command; and If the verification result is the second result, error processing corresponding to the write instruction is performed. 9. The data access method according to claim 1, further comprising: If the data access event is a data read event for the target data, a first controller within the storage device obtains the first logical unit information from a read instruction corresponding to the data read event; obtaining, by the first controller, physical unit information corresponding to the first logical unit information; and A second controller in the storage device obtains the target data and the second logical unit information from the memory module according to the physical unit information. 10. The data access method according to claim 9, wherein executing the operation corresponding to the data access event according to the verification result comprises: If the verification result is the first result, transmitting the target data to the host system in response to the read command; and If the verification result is the second result, error processing corresponding to the read instruction is performed. 11. A storage device, comprising: A connection interface for connecting to a host system; a memory module; and a memory controller connected to the connection interface and the memory module, The memory controller is configured to: generating first verification information at a first verification location within the storage device based on target data and first logical unit information corresponding to the target data in response to a data access event, wherein the data access event indicates storing the target data into the memory module or reading the target data from the memory module; generating second verification information at a second verification location within the storage device according to the target data and second logical unit information corresponding to the target data, wherein the second verification location is different from the first verification location; Performing a verification operation according to the first verification information and the second verification information to obtain a verification result; and An operation corresponding to the data access event is executed according to the verification result. 12. The storage device according to claim 11, wherein the memory controller includes a first controller and a second controller, the first verification position is located in the first controller, the second verification position is located in the second controller, the first controller is used to communicate with the host system, and the second controller is used to control the memory module. 13. The storage device according to claim 11, wherein the first verification information reflects a first operation result of a first logical operation performed on the target data and the first logical unit information, and the second verification information reflects a second operation result of a second logical operation performed on the target data and the second logical unit information. 14 . The storage device according to claim 11 , wherein the first check information and the second check information both comprise cyclic redundancy check codes. 15 . The storage device of claim 11 , wherein the verification operation is used to confirm whether the first verification information is the same as the second verification information. 16. The storage device according to claim 11 , wherein the memory controller performs the verification operation according to the first verification information and the second verification information to obtain the verification result comprises: The first verification information and the second verification information are compared to obtain the verification result. 17. The storage device according to claim 11, wherein the memory controller is further configured to: If the data access event is a data write event for the target data, a first controller within the memory controller obtains the first logical unit information from a write instruction corresponding to the data write event; and The first controller transmits the first logic unit information to a second controller in the memory controller as the second logic unit information. 18. The storage device according to claim 17, wherein, according to the verification result, executing the operation corresponding to the data access event comprises: If the verification result is the first result, writing the target data and the second logic unit information into the memory module in response to the write command; and If the verification result is the second result, error processing corresponding to the write instruction is performed. 19. The storage device according to claim 11, wherein the memory controller is further configured to: If the data access event is a data read event for the target data, a first controller within the storage device obtains the first logical unit information from a read instruction corresponding to the data read event; obtaining, by the first controller, physical unit information corresponding to the first logical unit information; and A second controller in the storage device obtains the target data and the second logical unit information from the memory module according to the physical unit information. 20. The storage device according to claim 19, wherein the memory controller performs the operation corresponding to the data access event according to the verification result, comprising: If the verification result is the first result, transmitting the target data to the host system in response to the read command; and If the verification result is the second result, error processing corresponding to the read instruction is performed.