CN120201815A - Back contact cell, photovoltaic module and method for preparing back contact cell - Google Patents
Back contact cell, photovoltaic module and method for preparing back contact cell Download PDFInfo
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- CN120201815A CN120201815A CN202510678753.6A CN202510678753A CN120201815A CN 120201815 A CN120201815 A CN 120201815A CN 202510678753 A CN202510678753 A CN 202510678753A CN 120201815 A CN120201815 A CN 120201815A
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
- H10F77/00—Constructional details of devices covered by this subclass
- H10F77/10—Semiconductor bodies
- H10F77/14—Shape of semiconductor bodies; Shapes, relative sizes or dispositions of semiconductor regions within semiconductor bodies
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
- H10F10/00—Individual photovoltaic cells, e.g. solar cells
- H10F10/10—Individual photovoltaic cells, e.g. solar cells having potential barriers
- H10F10/14—Photovoltaic cells having only PN homojunction potential barriers
- H10F10/146—Back-junction photovoltaic cells, e.g. having interdigitated base-emitter regions on the back side
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
- H10F71/00—Manufacture or treatment of devices covered by this subclass
- H10F71/121—The active layers comprising only Group IV materials
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
- H10F77/00—Constructional details of devices covered by this subclass
- H10F77/10—Semiconductor bodies
- H10F77/12—Active materials
- H10F77/122—Active materials comprising only Group IV materials
- H10F77/1223—Active materials comprising only Group IV materials characterised by the dopants
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Abstract
The application discloses a back contact battery piece, a photovoltaic module and a preparation method of the back contact battery piece, and belongs to the technical field of photovoltaics. The back contact battery piece comprises a silicon wafer, a first doping layer and a second doping layer, wherein the doping types of the first doping layer and the second doping layer are opposite, the first doping layer is located in a first doping area, the second doping layer is located in a second doping area, the first doping area and the second doping area are staggered along the direction parallel to the plane of the silicon wafer, the first doping layer is a first diffusion structure formed by diffusion of a doping source on the back surface of the silicon wafer, the distance between one surface of the first diffusion structure, which is close to the silicon wafer, and one surface of the second doping layer, which is far away from the silicon wafer, is a preset distance, and the thickness of the silicon wafer located in the first doping area is larger than that of the silicon wafer located in the second doping area. The battery piece realizes effective isolation between two doped layers with opposite doping types through the silicon wafer with enough thickness, and an isolation region is not required to be etched by laser.
Description
Technical Field
The application belongs to the technical field of photovoltaics, and particularly relates to a back contact battery piece, a photovoltaic module and a preparation method of the back contact battery piece.
Background
The PN junction and the metal Contact of the Back Contact (BC) battery are designed on the Back of the battery, and the Back Contact (BC) battery is different from the traditional crystalline silicon battery in that the front of the BC battery is not shielded by a grid line, so that incident light can be utilized to the maximum extent, optical loss is reduced, and the conversion efficiency of the battery is improved.
BC cells are typically provided with isolation regions in the P-type and N-type conductive regions to prevent direct contact of the PN junctions, resulting in cell shorting failure. The isolation region is mainly prepared by high-precision laser patterning technology, the alignment of the subsequent metallization technology is directly influenced by the laser etching precision, the attenuation of the battery performance is easily caused by the minimum deviation, and if the isolation region has a communication defect, the short circuit is caused, so that the battery is invalid.
The existing BC battery has the defects of narrow process window, large fluctuation of process yield and limited photoelectric conversion efficiency.
Disclosure of Invention
The present application aims to solve at least one of the technical problems existing in the prior art. Therefore, the application provides the back contact battery piece, the photovoltaic module and the preparation method of the back contact battery piece, the effective isolation between different doped regions can be realized without laser etching isolation regions, the process compatibility window is obviously widened, and the production stability and the battery efficiency are effectively improved.
In a first aspect, the present application provides a back contact battery sheet comprising:
The silicon wafer comprises a silicon wafer, a first doping layer and a second doping layer, wherein the doping types of the first doping layer and the second doping layer are opposite, the first doping layer is located in a first doping region, the second doping layer is located in a second doping region, and the first doping region and the second doping region are staggered in a direction parallel to a plane where the silicon wafer is located and have no interval;
The first doping layer is a first diffusion structure formed by diffusion of a doping source on the back surface of the silicon wafer, the distance between one surface of the first diffusion structure, which is close to the silicon wafer, and one surface of the second doping layer, which is far away from the silicon wafer, is a preset distance, and the thickness of the silicon wafer in the first doping region is larger than that of the silicon wafer in the second doping region.
According to the back contact battery piece, the first doping layer is prepared by using the doping source diffusion in the first doping region, the second doping layer is arranged in the second doping region, no interval exists between the adjacent first doping region and the second doping region, the thickness of the silicon wafer positioned in the first doping region is larger than that of the silicon wafer positioned in the second doping region, the distance between the surface of the first diffusion structure, which is close to the silicon wafer, and the surface of the second doping layer, which is far away from the silicon wafer, is set to be a preset distance, the silicon wafer with enough thickness is used for realizing effective isolation between the two doping layers with opposite doping types, a laser etching isolation region is not needed, a process compatibility window is remarkably widened, and the production stability and the battery efficiency are effectively improved.
According to the back contact battery piece, the second doping layer comprises a second tunneling layer and a second doping crystal silicon layer which are sequentially stacked along the direction deviating from the silicon wafer;
The distance between the surface of the first diffusion structure, which is close to the silicon wafer, and the surface of the second doped crystal silicon layer, which is far away from the silicon wafer, is the preset distance.
According to one embodiment of the present application, the second doped layer is a second diffusion structure formed by diffusing a doping source on the back surface of the silicon wafer, and a distance between a surface of the first diffusion structure, which is close to the silicon wafer, and a surface of the second diffusion structure, which is far away from the silicon wafer, is the preset distance.
According to one embodiment of the application, the preset distance is 10 μm-15 μm.
According to one embodiment of the application, the area of the first doped region is greater than or equal to the area of the second doped region.
According to one embodiment of the application, the silicon wafer is an N-type silicon wafer or a P-type silicon wafer.
In a second aspect, the present application provides a photovoltaic module comprising:
the back contact battery sheet as described in the first aspect above.
In a third aspect, the present application provides a method for preparing a back contact battery sheet, the method comprising:
Carrying out surface treatment on the silicon wafer;
Preparing a first doping layer on the back surface of the silicon wafer;
removing the first doped layer and part of the silicon wafer of the second doped region, so that the thickness of the silicon wafer positioned in the first doped region is larger than that of the silicon wafer positioned in the second doped region, and the first doped region and the second doped region are staggered along the direction parallel to the plane of the silicon wafer without interval;
Preparing a second doped layer in the second doped region, wherein the doping types of the first doped layer and the second doped layer are opposite, the first doped layer is a first diffusion structure formed by diffusing a doping source on the back surface of the silicon wafer, and the distance between one surface of the first diffusion structure, which is close to the silicon wafer, and one surface of the second doped layer, which is far away from the silicon wafer, is a preset distance.
According to the preparation method of the back contact battery piece, the first doping layer is prepared through doping source diffusion, after the first doping layer and part of the silicon wafer in the second doping region are removed, the second doping layer is arranged in the second doping region, no interval exists between the adjacent first doping region and the second doping region, the thickness of the silicon wafer in the first doping region is larger than that of the silicon wafer in the second doping region, the distance between the surface of the first diffusion structure, which is close to the silicon wafer, and the surface of the second doping layer, which is far away from the silicon wafer, is set to be a preset distance, and the silicon wafer with enough thickness is used for realizing effective isolation between the two doping layers with opposite doping types, so that a laser etching isolation region is not needed, a process compatible window is remarkably widened, and the production stability and the battery efficiency are effectively improved.
According to one embodiment of the application, the preset distance is 10 μm-15 μm.
According to one embodiment of the application, preparing a first doped layer on the silicon wafer backlight surface comprises:
Performing diffusion on the back surface of the silicon wafer to form a first diffusion structure, and forming a first protective film layer on one surface of the first diffusion structure, which is away from the silicon wafer;
removing the first doped layer and part of the silicon wafer of the second doped region, wherein the method comprises the following steps:
Removing the first protective film layer of the second doped region by laser;
And wet etching the first doped layer of the second doped region and part of the silicon wafer.
Additional aspects and advantages of the application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the application.
Drawings
The foregoing and/or additional aspects and advantages of the application will become apparent and may be better understood from the following description of embodiments taken in conjunction with the accompanying drawings in which:
fig. 1 is a schematic structural diagram of a back contact battery sheet according to an embodiment of the present application;
FIG. 2 is a schematic diagram of a back contact battery cell according to an embodiment of the present application;
FIG. 3 is a third schematic diagram of a back contact battery plate according to an embodiment of the present application;
fig. 4 is a schematic flow chart of a method for manufacturing a back contact battery sheet according to an embodiment of the present application;
Fig. 5 is a schematic diagram of an intermediate structure of a back contact battery sheet according to an embodiment of the present application;
FIG. 6 is a schematic diagram of a second intermediate structure of a back contact battery sheet according to an embodiment of the present application;
fig. 7 is a third schematic diagram of an intermediate structure of a back contact battery sheet according to an embodiment of the present application.
Reference numerals:
the silicon wafer 100, the first doped region 110, the second doped region 120,
The semiconductor device comprises a first doping layer 210, a first protective film layer 211, a second doping layer 220, a second tunneling layer 221, a second doped crystalline silicon layer 222, a second diffusion structure 223, a passivation layer 230, an anti-reflection layer 240, a first electrode 310 and a second electrode 320.
Detailed Description
Embodiments of the present application are described in detail below, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to like or similar elements or elements having like or similar functions throughout. The embodiments described below by referring to the drawings are illustrative only and are not to be construed as limiting the application.
The back contact battery piece, the photovoltaic module and the preparation method of the back contact battery piece provided by the embodiment of the application are described in detail through specific embodiments and application scenes thereof by combining the attached drawings.
As shown in fig. 1, the back contact battery plate according to the embodiment of the present application includes a silicon wafer 100, and a first doped layer 210 and a second doped layer 220 with opposite doping types disposed on the back surface of the silicon wafer 100.
The silicon wafer 100 has two opposite surfaces, a light-facing surface facing the light source and a light-backing surface facing away from the light source.
In actual implementation, the silicon wafer 100 may be an N-type silicon wafer or a P-type silicon wafer.
It can be appreciated that the doping types of the N-type silicon wafer and the P-type silicon wafer are opposite, and meanwhile, the silicon wafers 100 with the two doping types have differences in terms of photoinduced attenuation characteristics, electrical performance, efficiency, cost and the like, and the N-type silicon wafer or the P-type silicon wafer can be selected as the silicon substrate of the back contact battery piece according to specific requirements.
The first doped layer 210 and the second doped layer 220 have opposite doping types, the first doped layer 210 corresponds to a P region for transporting holes, the second doped layer 220 corresponds to an N region for transporting electrons, the first doped layer 210 corresponds to an N region for transporting electrons, and the second doped layer 220 corresponds to a P region for transporting holes.
In this embodiment, the first doped layer 210 is located in the first doped region 110, the second doped layer 220 is located in the second doped region 120, and the first doped region 110 and the second doped region 120 are staggered with no space along a direction parallel to the plane of the silicon wafer 100.
In actual implementation, one of the first doped layer 210 and the second doped layer 220 is used for collecting holes and transmitting electrons to the corresponding electrode, and the other is used for collecting electrons and transmitting electrons to the corresponding electrode, so as to realize separation and collection of photo-generated carriers.
It is understood that the photo-generated current formed by the first doped layer 210 and the second doped layer 220 is collected by the metal electrode, the first electrode 310 contacts the first doped layer 210, and the second electrode 320 contacts the second doped layer 220, so as to realize the selective separation of electrons and holes, and lead out the photo-generated current.
The first electrode 310 and the second electrode 320 may have a thin gate, a main gate, or a gate line structure.
In practical implementation, the back contact cell may further be provided with a passivation layer 230, an anti-reflection layer 240, and other structures to reduce carrier recombination and increase light absorption, and on the backlight surface, the first electrode 310 is in contact with the first doped layer 210 through the passivation layer 230 and the anti-reflection layer 240, and the second electrode 320 is in contact with the second doped layer 220 through the passivation layer 230 and the anti-reflection layer 240.
The passivation layer 230 may be made of aluminum oxide (Al 2O3), the thickness of the passivation layer 230 may be 2nm to 10nm, the anti-reflection layer 240 may be a single-layer structure or a multi-layer structure of a silicon nitride (SiNx), silicon oxide (SiOx) and silicon oxynitride (SiOxNy) layer, and the thickness of the anti-reflection layer 240 may be 10nm to 100nm.
It should be noted that, the first doped regions 110 and the second doped regions 120 are staggered in a direction parallel to the plane of the silicon wafer 100 without any space, and when the back contact cell is manufactured, no laser etching isolation region is needed between the first doped regions 110 and the second doped regions 120 between adjacent first doped regions 110 and second doped regions 120.
For example, as shown in fig. 1, the first doped regions 110 and the second doped regions 120 are staggered in a right-to-left direction parallel to the plane of the silicon wafer 100, and there is no space between the first doped regions 110 and the second doped regions 120.
It should be noted that, the thickness of the silicon wafer 100 located in the first doped region 110 is greater than the thickness of the silicon wafer 100 located in the second doped region 120, and the first doped layer 210 located in the first doped region 110 and the second doped layer 220 located in the second doped region 120 form a height difference in a direction perpendicular to the plane of the silicon wafer 100 (i.e., the thickness direction of the silicon wafer 100), so that the first doped layer 210 and the second doped layer 220 may be spaced apart in the thickness direction.
In this embodiment, the first doped layer 210 is a first diffusion structure formed by diffusing a doping source on the backlight surface of the silicon wafer 100.
In practical implementation, a doping source can be used for diffusing on the backlight surface of the silicon wafer 100, a first diffusion structure is formed by diffusing along the thickness direction of the backlight surface towards the light surface, the preparation equipment is simple, the process is mature, and parameters such as diffusion time, temperature, gas flow and the like can be controlled in the preparation process, so that the doping depth and concentration distribution of the first diffusion structure can be controlled.
Wherein, the distance between the surface of the first diffusion structure close to the silicon wafer 100 and the surface of the second doped layer 220 far from the silicon wafer 100 is a preset distance.
It should be noted that, the surface of the first diffusion structure near the silicon wafer 100 is related to the doping depth of the first diffusion structure, and the process parameters such as the diffusion temperature, time, and impurity source concentration are regulated and controlled, so that the depth of impurity diffusion can be controlled, that is, the doping depth is controllable, the impurity boundary of the first diffusion structure near the silicon wafer 100 can be approximated to a plane, that is, the surface of the first diffusion structure near the silicon wafer 100, and the distance between the surface of the first diffusion structure near the silicon wafer 100 and the surface of the second doped layer 220 far from the silicon wafer 100 is a preset distance, and the silicon wafer 100 with enough thickness is reserved for the first doped layer 210 and the second doped layer 220 in the thickness direction (from top to bottom in fig. 1), so that the process precision requirements such as the diffusion temperature, time, impurity source concentration can be reduced while effective electrical isolation is realized.
In the embodiment of the application, the thickness of the silicon wafer 100 located in the first doped region 110 is greater than the thickness of the silicon wafer 100 located in the second doped region 120, the first doped layer 210 located in the first doped region 110 and the second doped layer 220 located in the second doped region 120 form a height difference in the thickness direction of the silicon wafer 100, and for the first diffusion structure formed by the first doped layer 210 serving as a diffusion doping source, the distance between the surface of the first diffusion structure, which is close to the silicon wafer 100, and the surface of the second doped layer 220, which is far away from the silicon wafer 100, is set to be a preset distance, and the silicon wafer 100 with a sufficient thickness (i.e., a preset distance) realizes effective isolation between two doped layers with opposite doping types, so that short circuits caused by contact of doped layers with different doping types can be prevented.
Meanwhile, the first doped layer 210 and the second doped layer 220 are isolated through the silicon wafer 100 with enough thickness, no space exists between the adjacent first doped region 110 and the second doped region 120, and when the back contact battery piece is manufactured, a laser etching isolation region is not needed between the first doped region 110 and the second doped region 120, so that the laser etching precision requirement in the manufacturing process can be reduced, the process compatible window is remarkably widened, and the production stability and the battery efficiency are effectively improved.
According to the back contact battery piece provided by the embodiment of the application, the first doping layer 210 is prepared by using the doping source diffusion in the first doping region 110, the second doping layer 220 is arranged in the second doping region 120, no interval exists between the adjacent first doping region 110 and the second doping region 120, the thickness of the silicon wafer 100 positioned in the first doping region 110 is larger than that of the silicon wafer 100 positioned in the second doping region 120, the distance between the surface of the first diffusion structure close to the silicon wafer 100 and the surface of the second doping layer 220 far away from the silicon wafer 100 is set to be a preset distance, the silicon wafer 100 with enough thickness is used for realizing effective isolation between the two doping layers with opposite doping types, a laser etching isolation region is not needed, a process compatible window is remarkably widened, and the production stability and the battery efficiency are effectively improved.
In the embodiment of the present application, the first doped layer 210 is a first diffusion structure formed by diffusing a doping source on the backlight surface of the silicon wafer 100, the second doped layer 220 may be a second diffusion structure 223 formed by diffusing a doping source on the backlight surface of the silicon wafer 100, and the second doped layer 220 may also be a stacked layer structure.
1. The second doped layer 220 is a stacked level structure.
In some embodiments, the second doped layer 220 includes a second tunneling layer 221 and a second doped crystalline silicon layer 222 sequentially stacked in a direction away from the silicon wafer 100, and a distance between a side of the first diffusion structure near the silicon wafer 100 and a side of the second doped crystalline silicon layer 222 away from the silicon wafer 100 is a preset distance.
The second tunneling layer 221 may be made of silicon dioxide (SiO 2), the second tunneling layer 221 contacts the silicon wafer 100, and the second tunneling layer 221 and the second doped crystalline silicon layer 222 may form a passivation contact structure, which is helpful for reducing the recombination of carriers and reducing the contact recombination loss.
As shown in fig. 2, the first doped layer 210 is a first diffusion structure formed by diffusing a doping source on a backlight surface of the silicon wafer 100, the second doped layer 220 includes a second tunneling layer 221 and a second doped crystalline silicon layer 222 sequentially stacked along a direction away from the silicon wafer 100, and a distance between a surface of the first diffusion structure, which is close to the silicon wafer 100, and a surface of the second doped crystalline silicon layer 222, which is far away from the silicon wafer 100, is a preset distance h.
In this embodiment, the first doped layer 210 located in the first doped region 110 and the second doped layer 220 located in the second doped region 120 form a height difference in the thickness direction of the silicon wafer 100, the distance between the side of the first diffusion structure close to the silicon wafer 100 and the side of the second doped silicon layer 222 far from the silicon wafer 100 is set to be a preset distance h, and isolation between the first diffusion structure and the second doped silicon layer 222 is achieved through the silicon wafer 100 with a sufficient thickness, so that the contact of the P region N region is prevented from causing a short circuit.
2. The second doped layer 220 is a diffusion structure.
In some embodiments, the second doped layer 220 is a second diffusion structure 223 formed by diffusing the dopant on the back light surface of the silicon wafer 100, and the distance between the surface of the first diffusion structure close to the silicon wafer 100 and the surface of the second diffusion structure 223 far from the silicon wafer 100 is a preset distance.
In this embodiment, the second diffusion structure 223 may be formed by diffusing the dopant source on the back light surface of the silicon wafer 100 and diffusing the dopant source in the thickness direction of the back light surface toward the light surface.
It can be appreciated that the first doped layer 210 and the second doped layer 220 are diffusion structures formed by diffusing diffusion sources on the backlight surface of the silicon wafer 100, and the same preparation process can be selected during preparation, so as to reduce the production complexity and the production cost.
In actual implementation, the doping depth and concentration distribution of the first and second diffusion structures 223 may be controlled by controlling parameters such as diffusion time, temperature, and gas flow rate.
As shown in fig. 3, the first diffusion structure is located in the first doped region 110, the second diffusion structure 223 is located in the second doped region 120, and the distance between the surface of the first diffusion structure close to the silicon wafer 100 and the surface of the second diffusion structure 223 far from the silicon wafer 100 is a preset distance h.
In this embodiment, the first doped layer 210 located in the first doped region 110 and the second doped layer 220 located in the second doped region 120 form a height difference in the thickness direction of the silicon wafer 100, the distance between the surface of the first diffusion structure close to the silicon wafer 100 and the surface of the second diffusion structure 223 far from the silicon wafer 100 is a preset distance h, and isolation between the first diffusion structure and the second diffusion structure 223 is achieved through the silicon wafer 100 with a sufficient thickness, so that the contact of the P region N region is prevented from causing a short circuit.
For example, the first doped layer 210 is a first diffusion structure obtained by using boron as a doping source for diffusion, namely a P region, the second doped layer 220 is a second diffusion structure 223 obtained by using phosphorus as a doping source for diffusion, namely an N region, and the distance between the surface of the first diffusion structure close to the silicon wafer 100 and the surface of the second diffusion structure 223 far from the silicon wafer 100 is a preset distance h, so that the P region N region is isolated by the silicon wafer 100 with a sufficient thickness, and short circuit is effectively prevented.
In some embodiments, the predetermined distance is 10 μm to 15 μm.
In this embodiment, for the first doped region 110 and the second doped region 120 where no lateral spacer is provided, the first doped layer 210 and the second doped layer 220 are isolated by reserving the silicon wafer 100 with a thickness of 10 μm-15 μm in the longitudinal direction (i.e. the thickness direction of the silicon wafer 100), the area ratio of the effective photoelectric conversion region (the first doped region 110 and the second doped region 120) on the silicon wafer 100 can be increased without providing the lateral spacer by preventing the P region N region from being contacted to cause a short circuit by the silicon wafer 100 with a sufficient thickness, and the thickness difference of 10 μm-15 μm will not cause a great influence on the subsequent electrode printing and solder ribbon soldering processes.
In some embodiments, the area of the first doped region 110 is greater than or equal to the area of the second doped region 120.
In this embodiment, the total area of the first doped regions 110 on the silicon wafer 100 may be greater than or equal to the total area of the second doped regions 120, or the area of a single first doped region 110 in the silicon wafer 100 may be greater than or equal to the area of a single second doped region 120.
In practical implementation, the area ratio of the first doped region 110 and the second doped region 120 may be designed by comprehensively considering the electrical performance, the optical loss, the process feasibility, etc., wherein the area of the first doped region 110 may be set according to the number of carriers collected by the first doped layer 210, and the area of the second doped region 120 may be set according to the number of carriers collected by the second doped layer 220.
For example, the first doped layer 210 is a first diffusion structure obtained by diffusing a boron doped source, i.e., a P region, the first doped layer 210 is a second diffusion structure 223 obtained by diffusing a phosphorus doped source, i.e., an N region, and the total area of the first doped region 110 is larger than the total area of the second doped region 120 on the silicon wafer 100, so that the hole collection efficiency is balanced by using a slightly larger P region area.
The embodiment of the application also provides a photovoltaic module.
The photovoltaic module comprises the back contact cell sheet.
In actual implementation, a plurality of back contact battery pieces can be interconnected through welding strips to form a battery string, and a series of packaging processes are carried out to obtain the photovoltaic module.
According to the photovoltaic module provided by the embodiment of the application, the back contact battery piece in the photovoltaic module is provided with the first doped layer 210 by using the doping source diffusion in the first doped region 110, the second doped region 120 is provided with the second doped layer 220, no interval exists between the adjacent first doped region 110 and the second doped region 120, the thickness of the silicon wafer 100 positioned in the first doped region 110 is larger than that of the silicon wafer 100 positioned in the second doped region 120, the distance between the surface of the first diffusion structure close to the silicon wafer 100 and the surface of the second doped layer 220 far away from the silicon wafer 100 is set as the preset distance, the silicon wafer 100 with enough thickness is used for realizing effective isolation between the two doped layers with opposite doping types, a laser etching isolation region is not needed, a process compatible window is remarkably widened, and the production stability and the battery efficiency are effectively improved.
The embodiment of the application also provides a preparation method of the back contact battery piece, which can be used for preparing the back contact battery piece.
As shown in fig. 4, the method for manufacturing the back contact battery sheet includes a step 410, a step 420, a step 430 and a step 440.
Step 410, performing surface treatment on the silicon wafer 100.
In actual implementation, the silicon wafer 100 may be an N-type silicon wafer or a P-type silicon wafer.
In this step, the silicon wafer 100 may be subjected to surface treatment processes such as cleaning and texturing, so as to facilitate the subsequent preparation of the structures such as the first doped layer 210.
For example, the silicon wafer 100 is an N-type silicon wafer with resistivity of 0.3 Ω·cm-7Ω·cm, the N-type silicon wafer is placed in an alkali polishing groove type machine, and the original silicon wafer 100 is polished on both sides by alkali etching to form a tower foundation.
Wherein the size of the tower foundation can be 10-20 mu m, the treatment time of the alkali tank can be set to be 50-500 s, the treatment temperature can be set to be 50-90 ℃, the alkali concentration is set to be 0.5-2%, and the additive concentration is set to be 0.5-1%.
It should be noted that, the first doped region 110 and the second doped region 120 may be divided into a staggered arrangement along a direction parallel to the plane of the silicon wafer 100, where the first doped region 110 is used to form the first doped layer 210, and the second doped region 120 is used to form the second doped layer 220.
Step 420, preparing the first doped layer 210 on the backlight surface of the silicon wafer 100.
The first doped layer 210 is a first diffusion structure formed by diffusing a doping source on the backlight surface of the silicon wafer 100.
In this step, the first diffusion structure is formed by using the doping source to diffuse in the entire area of the backlight surface of the silicon wafer 100 (including the first doping region 110 and the second doping region 120), and the first diffusion structure is distributed in the first doping region 110 and the second doping region 120.
It will be appreciated that during the cell fabrication process, the first doped layer 210 may be distributed between the first doped region 110 and the second doped region 120, leaving only the first doped layer 210 of the first doped region 110 in the fabricated back contact cell.
Step 430, removing the first doped layer 210 and a portion of the silicon wafer 100 of the second doped region 120.
In the step, the first doped layer 210 of the second doped region 120 is removed, and then a portion of the silicon wafer 100 of the second doped region 120 is removed, so that the thickness of the silicon wafer 100 located in the first doped region 110 is greater than the thickness of the silicon wafer 100 located in the second doped region 120.
Step 440, preparing the second doped layer 220 in the second doped region 120.
Wherein the doping types of the first doping layer 210 and the second doping layer 220 are opposite, and the distance between the surface of the first diffusion structure close to the silicon wafer 100 and the surface of the second doping layer 220 far from the silicon wafer 100 is a preset distance.
In this step, the thickness of the silicon wafer 100 located in the first doped region 110 is greater than the thickness of the silicon wafer 100 located in the second doped region 120, the second doped layer 220 is prepared in the second doped region 120, and the first doped layer 210 located in the first doped region 110 and the second doped layer 220 located in the second doped region 120 form a height difference in a direction perpendicular to the plane of the silicon wafer 100 (i.e., the thickness direction of the silicon wafer 100), so that the first doped layer 210 and the second doped layer 220 may be spaced apart in the thickness direction.
The first doped layer 210 and the second doped layer 220 are isolated through the silicon wafer 100 with enough thickness (i.e. a preset distance), so that short circuit caused by contact of doped layers with different doping types can be prevented, no interval exists between the adjacent first doped region 110 and the second doped region 120, when the back contact battery piece is prepared, a laser etching isolation region is not needed between the first doped region 110 and the second doped region 120, the requirement on the laser etching precision in the preparation process can be reduced, the process compatible window is remarkably widened, and the production stability and the battery efficiency are effectively improved.
According to the preparation method of the back contact battery piece provided by the embodiment of the application, the first doped layer 210 is prepared by doping source diffusion, after the first doped layer 210 and part of the silicon wafer 100 in the second doped region 120 are removed, the second doped layer 220 is arranged in the second doped region 120, no interval exists between the adjacent first doped region 110 and the second doped region 120, the thickness of the silicon wafer 100 positioned in the first doped region 110 is larger than that of the silicon wafer 100 positioned in the second doped region 120, the distance between the surface of the first diffusion structure close to the silicon wafer 100 and the surface of the second doped layer 220 far away from the silicon wafer 100 is set as a preset distance, the silicon wafer 100 with enough thickness is used for realizing effective isolation between the two doped layers with opposite doping types, a laser etching isolation region is not needed, a compatible process window is remarkably widened, and the production stability and the battery efficiency are effectively improved.
In some embodiments, the predetermined distance is 10 μm to 15 μm.
In some embodiments, preparing the first doped layer 210 on the back light side of the silicon wafer 100 includes:
Performing diffusion on the backlight surface of the silicon wafer 100 to form a first diffusion structure, and forming a first protective film layer 211 on the surface, away from the silicon wafer 100, of the first diffusion structure;
removing the first doped layer 210 and a portion of the silicon wafer 100 of the second doped region 120 includes:
Removing the first protective film layer 211 of the second doped region 120 by laser;
the first doped layer 210 of the second doped region 120 and a portion of the silicon wafer 100 are wet etched.
As shown in fig. 5, the first doped layer 210 is formed in the entire area of the back surface of the silicon wafer 100, the first diffusion structure is formed first, and then the first protective film 211 is formed on the surface of the first diffusion structure facing away from the silicon wafer 100.
It is understood that the first protection film layer 211 may protect the first diffusion structure, and in the process of preparing the first doping layer 210, the first protection film layer 211 may be formed on a surface of the first diffusion structure facing away from the silicon wafer 100 after the first diffusion structure is formed.
For example, boron trichloride (BCl 3) or boron tribromide (BBr 3) is used as a boron doping source, a first diffusion structure is formed by diffusing on the backlight surface of the silicon wafer 100, after diffusion is completed, technological parameters are adjusted, a first protection film layer 211 is formed on one surface of the first diffusion structure, which is far away from the silicon wafer 100, and the first protection film layer 211 is borosilicate glass (BSG).
For another example, a phosphorus doping source is used to diffuse on the backlight surface of the silicon wafer 100 to form a first diffusion structure, after diffusion is completed, the technological parameters are adjusted, and a first protection film layer 211 is formed on one surface of the first diffusion structure, which is away from the silicon wafer 100, and the first protection film layer 211 is phosphosilicate glass (PSG).
As shown in fig. 6, the first protection film 211 of the second doped region 120 may be removed by laser to expose the first doped layer 210 of the second doped region 120, and as shown in fig. 7, the first doped layer 210 of the second doped region 120 and a portion of the silicon wafer 100 may be etched by wet method to facilitate the subsequent preparation of the second doped layer 220.
It is understood that wet etching refers to the selective removal of portions of the silicon wafer 100 by chemical reaction with the surface of the material in an acid (e.g., hydrofluoric acid) or alkali to form the desired electrical structure.
In this embodiment, after the laser removes the first protection film 211 of the second doped region 120, the first doped layer 210 of the second doped region 120 is exposed, and the first doped layer 210 of the second doped region 120 is removed by an acid solution or an alkali solution, where the first doped layer 210 of the first doped region 110 is protected by the first protection film 211 and is not etched.
In practical implementation, after the first doped layer 210 of the second doped region 120 is removed, the silicon wafer 100 of the second doped region 120 is continuously removed, where the etching depth h=10μm-15 μm of the silicon wafer 100 is such that the distance between the surface of the first diffusion structure close to the silicon wafer 100 and the surface of the second doped layer 220 far from the silicon wafer 100 is the preset distance h=10μm-15 μm, and effective isolation between the two doped layers with opposite doping types is achieved through the silicon wafer 100 with sufficient thickness.
It will be appreciated that the second doped layer 220 may be prepared in the second doped region 120 by removing the first doped layer 210 of the second doped region 120 and a portion of the silicon wafer 100.
In some embodiments, the second doped layer 220 includes a second tunneling layer 221 and a second doped crystalline silicon layer 222 sequentially stacked in a direction away from the silicon wafer 100, and a distance between a side of the first diffusion structure near the silicon wafer 100 and a side of the second doped crystalline silicon layer 222 away from the silicon wafer 100 is a preset distance.
In other embodiments, the second doped layer 220 is a second diffusion structure 223 formed by diffusing the dopant on the back light surface of the silicon wafer 100, and the distance between the surface of the first diffusion structure close to the silicon wafer 100 and the surface of the second diffusion structure 223 far from the silicon wafer 100 is a predetermined distance.
The terms first, second and the like in the description and in the claims, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged, as appropriate, such that embodiments of the present application may be implemented in sequences other than those illustrated or described herein, and that the objects identified by "first," "second," etc. are generally of a type, and are not limited to the number of objects, such as the first object may be one or more. Furthermore, in the description and claims, "and/or" means at least one of the connected objects, and the character "/", generally means that the associated object is an "or" relationship.
In the description of the present application, it should be understood that the terms "longitudinal," "transverse," "thickness," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," "outer," and the like indicate an orientation or a positional relationship based on that shown in the drawings, merely for convenience in describing the present application and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present application.
In the description of the application, a "first feature" or "second feature" may include one or more of such features.
In the description of the present application, "plurality" means two or more.
In the description of the application, a first feature "above" or "below" a second feature may include both the first and second features being in direct contact, and may also include the first and second features not being in direct contact but being in contact with each other by another feature therebetween.
In the description of the application, a first feature being "above," "over" and "on" a second feature includes the first feature being directly above and obliquely above the second feature, or simply indicates that the first feature is higher in level than the second feature.
In the description of the present specification, reference to the terms "one embodiment," "some embodiments," "illustrative embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the application. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiments or examples. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
Although embodiments of the present application have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made therein without departing from the spirit and scope of the application as defined by the appended claims and their equivalents.
Claims (10)
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