CN120048820A - Bridge chip and preparation method thereof, packaging structure and preparation method thereof - Google Patents
Bridge chip and preparation method thereof, packaging structure and preparation method thereof Download PDFInfo
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- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
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- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
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Abstract
本发明涉及一种桥接芯片及其制备方法、封装结构及其制备方法，涉及半导体技术领域，该桥接芯片及其制备方法中，形成的桥接芯片的两侧分别具有第一重布线结构与第二重布线结构，将硅桥基片设置在了中间，形成了桥接结构。第一介电层与第二介电层设置在最外侧，保护焊盘不被损坏。采用该桥接芯片形成封装结构时，该结构的桥接芯片在后续进行桥接时采用第一焊盘与第二焊盘与其他结构直接接触来实现桥接，避免了硅桥基片与外部结构的直接接触，研磨时金属材料不会迁移进入硅桥基片的硅基板中，避免了桥接芯片的短路问题，提高了封装结构的良品率。
The present invention relates to a bridge chip and a preparation method thereof, a packaging structure and a preparation method thereof, and relates to the field of semiconductor technology. In the bridge chip and the preparation method thereof, the two sides of the formed bridge chip have a first rewiring structure and a second rewiring structure respectively, and a silicon bridge substrate is arranged in the middle to form a bridge structure. The first dielectric layer and the second dielectric layer are arranged on the outermost side to protect the pad from being damaged. When the bridge chip is used to form a packaging structure, the bridge chip of the structure uses the first pad and the second pad to directly contact with other structures during subsequent bridging to achieve bridging, avoiding direct contact between the silicon bridge substrate and the external structure. During grinding, the metal material will not migrate into the silicon substrate of the silicon bridge substrate, avoiding the short circuit problem of the bridge chip, and improving the yield rate of the packaging structure.
Description
Technical Field
The present application relates to the field of semiconductor technologies, and in particular, to a bridge chip, a method for manufacturing the bridge chip, a package structure, and a method for manufacturing the package structure.
Background
Packaging processes are critical processes in semiconductor manufacturing for protecting chips, making electrical connections, and ensuring device performance.
In the existing packaging process, the bridge chip plays a role in electrical connection. When the packaging structure is prepared, the bridge chip needs to be ground, and the conductive through holes in the bridge chip are exposed to realize electrical connection, and at the moment, the grinding can cause metal materials in the conductive through holes to migrate into the bridge chip due to the fact that the conductive through holes of the bridge chip are positioned in the silicon material, so that the packaging structure is short-circuited.
Disclosure of Invention
Based on this, it is necessary to provide a bridge chip and a manufacturing method thereof, a package structure and a manufacturing method thereof, aiming at the problem of short circuit of the package structure caused by migration of metal materials.
To achieve the above object, in one aspect, the present invention provides a bridge chip, including:
The device comprises a silicon bridge substrate, a first re-wiring structure and a second re-wiring structure, wherein the first re-wiring structure and the second re-wiring structure are respectively positioned at two sides of the silicon bridge substrate;
The first rewiring structure comprises a first bonding pad and a first dielectric layer, wherein the first bonding pad is positioned on one side of the silicon bridge substrate, the first dielectric layer is positioned on one side of the first bonding pad far away from the silicon bridge substrate, and the first dielectric layer covers the first bonding pad;
The second redistribution structure comprises a second bonding pad and a second dielectric layer, wherein the second bonding pad is positioned on one side of the silicon bridge substrate far away from the first redistribution structure, the second dielectric layer is positioned on one side of the second bonding pad far away from the silicon bridge substrate, and the second dielectric layer covers the second bonding pad.
In another aspect, the present invention further provides a package structure, including:
The bridge chip comprises a first chip and a first plastic sealing layer surrounding the first chip, wherein the first chip is a chip structure provided by the application after the first dielectric layer and the second dielectric layer are removed from the bridge chip;
the second chip is positioned on one side of the first chip and the first plastic sealing layer and is connected with the first chip;
The second plastic layer is positioned on one side of the second chip far away from the first chip and covers the second chip.
In one embodiment, the package structure further includes:
A third rewiring structure located between the first chip and the second chip;
and a fourth re-wiring structure located at a side of the first chip away from the second chip.
In another aspect, the present invention further provides a method for preparing a bridge chip, including:
Providing a silicon bridge substrate;
Forming a first rerouting structure on one side of the silicon bridge substrate, wherein the first rerouting structure comprises a first bonding pad and a first dielectric layer covering the first bonding pad;
forming a second redistribution structure on the other side of the silicon bridge substrate, wherein the second redistribution structure comprises a second bonding pad and a second dielectric layer covering the second bonding pad;
the silicon bridge substrate after the first and second redistribution structures are formed is cut to form bridge chips.
In one embodiment, before forming the second redistribution structure on the other side of the silicon bridge substrate, the method includes:
providing a first carrier plate;
Bonding the first rewiring structure to the first carrier plate;
and carrying out thinning treatment on one side of the silicon bridge substrate far away from the first rewiring structure by taking the first carrier plate as a support, so as to expose the conductive through hole structure of the silicon bridge substrate.
In one embodiment, before the dicing forms the silicon bridge substrate after the first and second redistribution structures, the dicing includes:
attaching a first cutting film on one side of the second dielectric layer far away from the first carrier plate;
And removing the first carrier plate.
In one embodiment, before the cutting forms the silicon bridge substrate after the first and second redistribution structures, the method further comprises:
attaching a second cutting film on one side of the second dielectric layer far away from the first carrier plate;
Removing the first carrier plate;
A third dicing film formed on a side of the first dielectric layer away from the second dicing film, and removing the second dicing film;
And attaching a first cutting film on one side of the second dielectric layer far away from the first carrier plate, and removing the third cutting film.
In one embodiment, the dicing forms the silicon bridge die after the first and second redistribution structures, comprising:
cutting the silicon bridge substrate after the first and second redistribution structures are formed based on the first cutting film.
On the other hand, the invention also provides a preparation method of the packaging structure, which comprises the following steps:
Providing a second carrier plate;
a third chip is mounted on one side of the second carrier plate, a first plastic sealing layer surrounding the third chip is formed, and the bridge chip provided by the application is formed;
grinding one side, far away from the second carrier, of the third chip and the first plastic sealing layer to expose a first bonding pad of the third chip;
Attaching a second chip on one side of the third chip far away from the second carrier plate, and forming a second plastic sealing layer covering the second chip;
removing the second carrier plate by taking the second plastic sealing layer as a support to expose the second dielectric layer of the third chip;
and grinding the second dielectric layer and the first plastic sealing layer to expose the second bonding pad of the third chip.
In one embodiment, after the grinding the third chip and the side of the first plastic sealing layer away from the second carrier to expose the first bonding pad of the third chip, the method includes:
Forming a third rewiring structure on one side of the third chip far away from the second carrier plate;
And forming a fourth re-wiring structure on one side of the third chip far away from the second chip.
Compared with the prior art, the technical scheme has the following advantages:
In the bridge chip and the preparation method thereof, the two sides of the formed bridge chip are respectively provided with a first rewiring structure and a second rewiring structure, and a silicon bridge substrate is arranged in the middle to form the bridge structure. The first dielectric layer and the second dielectric layer are arranged at the outermost side, and the bonding pad is protected from being damaged. The bridging chip of the structure adopts the first bonding pad and the second bonding pad to be in direct contact with other structures to realize bridging when bridging is carried out subsequently, so that the direct contact between the silicon bridging substrate and an external structure is avoided, the silicon bridging substrate is not contacted during grinding, and the possibility that metal materials enter the silicon bridging substrate is avoided.
In the packaging structure and the preparation method thereof, as the third chip is the bridging chip, the first and second rerouting structures are positioned at two sides of the silicon bridge substrate, and the structures of the first bonding pad, the second bonding pad and the two sides are adopted for bridging, so that the direct contact with the silicon bridge substrate is avoided, and therefore, when the second dielectric layer is ground, the metal material cannot migrate into the silicon substrate of the silicon bridge substrate, the problem of short circuit of the bridging chip is avoided, and the yield of the packaging structure is improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments or the conventional techniques of the present application, the drawings required for the descriptions of the embodiments or the conventional techniques will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present application, and other drawings may be obtained according to the drawings without inventive effort for those skilled in the art.
Fig. 1 is a schematic diagram of a preparation flow of a bridge chip according to an embodiment of the present application;
FIG. 2 is a schematic diagram of a structure of a silicon bridge substrate according to an embodiment of the present application;
FIG. 3 is a schematic diagram of a structure of a first redistribution structure formed on a silicon bridge substrate according to an embodiment of the present application;
Fig. 4 is a schematic structural diagram of the first carrier after bonding according to an embodiment of the present application;
FIG. 5 is a schematic diagram of a structure of a substrate with a silicon bridge formed according to an embodiment of the present application;
Fig. 6 is a schematic structural diagram after forming a second redistribution structure according to an embodiment of the present application;
Fig. 7 is a schematic structural diagram of the first dicing film according to an embodiment of the application;
FIG. 8 is a schematic diagram of the structure of FIG. 7 after the first carrier is removed;
Fig. 9 is a schematic structural diagram of a second dicing film according to an embodiment of the application;
fig. 10 is a schematic structural diagram of a third dicing film according to an embodiment of the present application;
fig. 11 is a schematic structural diagram of a bridge chip formed by cutting according to an embodiment of the present application;
fig. 12 is a schematic structural diagram of a silicon bridge substrate after bonding a first carrier according to an embodiment of the present application;
FIG. 13 is a schematic diagram of a structure after thinning a silicon-based initial substrate according to an embodiment of the present application;
FIG. 14 is a schematic view of a structure after exposing a conductive initial structure according to an embodiment of the present application;
FIG. 15 is a schematic diagram of a structure after etching a silicon-based initial substrate according to an embodiment of the present application;
fig. 16 is a schematic structural diagram of a protective material layer formed according to an embodiment of the present application;
FIG. 17 is a schematic diagram of a structure after forming a silicon bridge substrate according to an embodiment of the present application;
FIG. 18 is a schematic diagram of another embodiment of a structure of a silicon-based initial substrate after etching;
FIG. 19 is a schematic view of another embodiment of the present application after forming a protective material layer;
fig. 20 is a schematic structural diagram of a bridge chip according to an embodiment of the present application;
Fig. 21 is a schematic diagram of a manufacturing flow of a package structure according to an embodiment of the present application;
Fig. 22 is a schematic structural diagram of a second carrier according to an embodiment of the present application;
Fig. 23 is a schematic structural diagram of a third chip mounted and a first package layer formed according to an embodiment of the present application;
FIG. 24 is a schematic diagram of a structure after removing the first dielectric layer according to an embodiment of the present application;
fig. 25 is a schematic structural diagram after forming a third triple wiring structure according to an embodiment of the present application;
fig. 26 is a schematic structural diagram of a second chip mounted and a second package layer formed according to an embodiment of the present application;
Fig. 27 is a schematic structural diagram of the second carrier removed according to an embodiment of the present application;
FIG. 28 is a schematic diagram of a structure after removing the second dielectric layer according to an embodiment of the present application;
Fig. 29 is a schematic view of a structure after forming a fourth re-wiring structure according to an embodiment of the present application;
Fig. 30 is a schematic structural diagram of a conductive structure according to an embodiment of the present application;
Fig. 31 is a schematic structural diagram of a third pad according to an embodiment of the present application;
fig. 32 is a schematic structural diagram of a first chip according to an embodiment of the present application.
Reference numerals illustrate 01-silicon bridge substrates; 0111-silicon-based initial substrate; 011-a silicon substrate; 012-wiring layer, 0131-conductive initial structure, 0131-conductive via structure, 02-first re-wiring structure, 021-first bonding pad, 022-first insulating layer, 023-first dielectric layer, 031-first carrier plate, 032-first stripping layer, 033-first adhesive layer, 041-protective material layer, 04-protective layer, 05-second re-wiring structure, 051-second bonding pad, 052-second insulating layer, 053-second dielectric layer, 06-first cutting film, 061-first adhesive layer, 062-first cutting layer, 063-first tightening ring, 07-second cutting film, 071-second adhesive layer, 072-second cutting layer, 073-second tightening ring, 08-third cutting film, 081-third adhesive layer, 082-third cutting layer, 083-third tightening ring, 09-second carrier plate, 10-second stripping layer, 11-second adhesive layer, 12-second metal chip, 13-third sealing layer, 063-first sealing layer, 07-second tightening ring, 07-second cutting film, 071-third adhesive layer, 072-second sealing layer, 072-third sealing layer, 083-third sealing layer, 09-second carrier plate, 10-second stripping film, 11-second sealing layer, 12-second metal chip, 13-third sealing layer, 16-third sealing layer, 17-third sealing layer, and 17-third sealing structure.
Detailed Description
In order that the application may be readily understood, a more complete description of the application will be rendered by reference to the appended drawings. Embodiments of the application are illustrated in the accompanying drawings. This application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
It will be understood that when a layer is referred to as being "on," "adjacent to," "connected to" another layer, it can be directly on, adjacent to, or connected to the other layer, or intervening layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," or "directly connected to" another layer, there are no intervening layers present.
As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," and/or the like, specify the presence of stated features, integers, steps, operations, elements, components, or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or groups thereof.
The application will be further described in detail with reference to the drawings and detailed description below in order to make the objects, features and advantages of the application more comprehensible.
The present application provides a bridge chip (as shown in fig. 20), which includes:
the first rerouting structure 02 and the second rerouting structure 05 are respectively positioned at two sides of the silicon bridge substrate 01;
The first rerouting structure 02 comprises a first bonding pad 021 and a first dielectric layer 023, wherein the first bonding pad 021 is positioned on one side of the silicon bridge base 01, the first dielectric layer 023 is positioned on one side of the first bonding pad 021 far away from the silicon bridge base 01, and the first dielectric layer 023 covers the first bonding pad 021;
The second re-wiring structure 05 includes a second pad 051 and a second dielectric layer 053, the second pad 051 is located at a side of the silicon bridge substrate 01 far from the first re-wiring structure 02, the second dielectric layer 053 is located at a side of the second pad 051 far from the silicon bridge substrate 01, and the second dielectric layer 053 covers the second pad 051.
Specifically, the silicon bridge substrate 01 may communicate with the first pad 021 of the first redistribution structure 02 and the second pad 051 of the second redistribution structure 05. The first dielectric layer 023 may protect the first pad 021 and the second dielectric layer 053 may protect the second pad 051.
In this embodiment, the bridge chip has a first redistribution structure 02 and a second redistribution structure 05 on two sides, respectively, and the silicon bridge substrate 01 is disposed in the middle, thereby forming a bridge structure. The first dielectric layer 023 and the second dielectric layer 053 are disposed at the outermost sides, protecting the pads from damage. The bridging chip of the structure adopts the first bonding pad 021 and the second bonding pad 051 to be in direct contact with other structures to realize bridging when bridging is carried out subsequently, so that the direct contact between the silicon bridging substrate 01 and an external structure is avoided, the silicon bridging substrate 01 is not contacted during grinding, and the possibility that metal materials enter the silicon bridging substrate 01 is reduced.
Based on the bridge chip, the application also provides a preparation method of the bridge chip, please refer to fig. 1, fig. 1 is a schematic diagram of a preparation flow of the bridge chip according to an embodiment of the application, wherein the preparation steps of the bridge chip include:
s10, providing a silicon bridge substrate 01 (shown in FIG. 5).
The silicon bridge substrate 01 may be a silicon substrate structure provided with a conductive via structure 013, and is not particularly limited. Note that the silicon bridge substrate 01 in fig. 5 is only an example.
The first re-wiring structure 02 is formed on one side of the silicon bridge substrate 01, and the first re-wiring structure 02 includes a first pad 021 and a first dielectric layer 023 (shown in fig. 3) covering the first pad 021.
In this step, a first bonding pad 021 is formed on one side of the silicon bridge substrate 01, and the first bonding pad 021 may be made of a metal conductive material and may be connected with the silicon bridge substrate 01 to realize circuit conduction. A first insulating layer 022 is further provided between the first pads 021 for preventing short circuits. The material of the first insulating layer 022 may be a photosensitive resin material. Then, a first dielectric layer 023 is formed on the side of the first bonding pad 021 far from the silicon bridge substrate 01, and the material of the first dielectric layer 023 can be photosensitive resin material.
Note that the photosensitive resin material may include, but is not limited to, a Polyimide (PI) material.
It should be noted that the first rerouting structure may include a plurality of interconnect wiring layers (not shown in the figure), where the plurality of interconnect wiring layers are connected to each other to achieve conduction, which is only an example.
And S30, forming a second redistribution structure 05 on the other side of the silicon bridge substrate 01, wherein the second redistribution structure 05 comprises a second bonding pad 051 and a second dielectric layer 053 (shown in fig. 6) covering the second bonding pad 051.
In this step, the second redistribution structure 05 is formed on the side of the silicon bridge substrate 01 facing away from the first redistribution structure 02, including forming the second pads 051 first, and a second insulating layer 052 is further disposed between the second pads 051, for preventing short-circuiting. The material of the second insulating layer 052 may be a photosensitive resin material. A second dielectric layer 053 is then formed on a side of the second pad 051 remote from the silicon bridge substrate 01, and the material of the second dielectric layer 053 may be a photosensitive resin material. At this time, the first pads 021 and the second pads 051 are communicated through the silicon bridge chip 01.
S40, dicing the silicon bridge substrate 01 after the first and second redistribution structures 02 and 05 are formed to form bridge chips (as shown in fig. 11).
In this step, the silicon bridge substrate 01 after the first and second redistribution structures 02 and 05 are formed is cut as necessary to form a plurality of bridge chips.
In this embodiment, the bridge chip is formed with a first redistribution structure 02 and a second redistribution structure 05 on both sides, respectively, with a silicon bridge substrate 01 disposed in the middle, to form a bridge structure. The first dielectric layer 023 and the second dielectric layer 053 are disposed at the outermost sides, protecting the pads from damage. The bridging chip of this structure adopts first pad 021 and second pad 051 and other structures direct contact to realize bridging when bridging in the follow-up, has avoided the direct contact of silicon bridge substrate 01 and external structure, just also can not contact silicon bridge substrate 01 when grinding, has avoided the possibility that the metal material got into silicon bridge substrate 01.
In another embodiment of the present application, before step S30, it includes:
S301, a first carrier plate 031 is provided.
The first carrier 031 may be a carrier for supporting, including but not limited to a glass carrier.
S302, bonding the first redistribution structure 02 to the first carrier plate 031.
The silicon bridge substrate 01 may be formed during the process of preparing the first and second redistribution structures 02 and 05. That is, a silicon bridge substrate may be provided first, where the silicon bridge substrate may include a silicon substrate 0111, a wiring layer 012, and a conductive initial structure 0131, where the wiring layer 012 is located on one side of the silicon substrate 0111, and the conductive initial structure 0131 extends inward from the side of the silicon substrate 0111 where the wiring layer 012 is located (as shown in fig. 2). Then after forming the first re-wiring structure 02 on one side of the silicon bridge substrate (as shown in fig. 3), the silicon bridge substrate 01 is formed before forming the second re-wiring structure 05.
Before this, a first release layer 032 and a first adhesive layer 033 may be formed on one side of the first carrier 031 in sequence, and then the first dielectric layer 023 of the first redistribution structure 02 is bonded to the first carrier 031 through the first adhesive layer 033 (as shown in fig. 4).
And S303, carrying out thinning treatment on one side of the silicon bridge substrate far away from the first rerouting structure 02 by taking the first carrier 031 as a support, so as to expose a conductive through hole structure 013 (shown in fig. 5) of the silicon bridge substrate 01.
In this step, before forming the second re-wiring structure 05, the conductive via structure 013 in the silicon bridge substrate 01 needs to be exposed, so that conduction between the first re-wiring structure 02 and the second re-wiring structure 05 is achieved. Therefore, the first carrier 031 can be used as a support to thin the silicon bridge substrate.
The thinning process of the silicon bridge substrate 01 may be performed by two different processes when the conductive via structure 013 is exposed.
In one process, after the first redistribution structure 02 is bonded to the first carrier 031 (as shown in fig. 12), a first pre-thinning is performed on a side of the silicon-based initial substrate 0111 away from the first carrier 031 to increase a process rate (as shown in fig. 13). Then, a Chemical Mechanical Polishing (CMP) process is used to expose the conductive initial structure 0131 (as shown in fig. 14), and then, a dry etching is used to etch a portion of the silicon-based initial substrate 0111, so that the thickness of the remaining silicon-based initial substrate 0111 is smaller than the height of the conductive initial structure 0131, at this time, the protruding portion of the conductive initial structure 0131 is exposed to the outside, and the remaining silicon-based initial substrate 0111 is a silicon substrate 011 (as shown in fig. 15). A protective material layer 041 is then formed overlying the conductive initial structure 0131 and the silicon substrate 011 using a Plasma Enhanced Chemical Vapor Deposition (PECVD) process (as shown in fig. 16). The material of the protective material layer 041 may include, but is not limited to, silicon oxide, silicon nitride, or silicon oxynitride, etc., and the protective material layer 041 may avoid damage to the silicon substrate 011 by subsequent grinding. Thereafter, the conductive initial structure 0131 and the protective material layer 041 are subjected to a grinding process to grind the protruding portions of the conductive initial structure 0131 flat, the remaining conductive initial structure 0131 forming a conductive via structure 013, and the remaining protective material layer 041 forming a protective layer 04 (as shown in fig. 17). At this point, the conductive via structure 013 is exposed. By adopting the process, the non-uniformity of the through silicon via process and the chemical mechanical polishing process can be avoided.
In another process, after the first redistribution structure 02 is bonded to the first carrier 031 (as shown in fig. 12), a first pre-thinning is performed on a side of the silicon-based initial substrate 0111 away from the first carrier 031 to increase a process rate (as shown in fig. 13). Then, a portion of the silicon-based initial substrate 0111 is etched by dry etching, so that the thickness of the remaining silicon-based initial substrate 0111 is smaller than the height of the conductive initial structure 0131, and the silicon-based initial substrate 0111 on the outer side of the conductive initial structure 0131 still covers the conductive initial structure 0131 (as shown in fig. 18). A protective material layer 041 is then formed overlying the conductive initial structure 0131 and the silicon-based initial substrate 0111 using a Plasma Enhanced Chemical Vapor Deposition (PECVD) process (as shown in fig. 19). The material of the protective material layer 041 may include, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, etc., and the protective material layer 041 may avoid damage to the silicon-based initial substrate 0111 caused by subsequent grinding. Thereafter, the conductive initial structure 0131 and the protective material layer 041 are subjected to a grinding process to grind the protruding portions of the conductive initial structure 0131 flat, the remaining conductive initial structure 0131 forming a conductive via structure 013, and the remaining protective material layer 041 forming a protective layer 04 (as shown in fig. 17). At this point, the conductive via structure 013 is exposed. The conductive initial structure 0131 is not exposed before the protective layer 04 is formed by adopting the process, the process is cleaner, SF 6 gas is adopted for etching in dry etching, and the whole etching rate is relatively high.
Note that both processes may expose the conductive via structure 013, which may be selected as desired.
In this embodiment, the first carrier 031 can be provided as a supporting layer, so as to thin the silicon bridge substrate 01 based on the first carrier 031, and further expose the conductive via structure 013 to realize the conduction between the first redistribution structure 02 and the second redistribution structure 05.
In another embodiment of the present application, before step S40, the method includes:
S4011, attaching a first dicing film 06 (as shown in fig. 7) on a side of the second dielectric layer 053 away from the first carrier 031;
S4012, removing the first carrier 031 (as shown in fig. 8).
Specifically, the first dicing film 06 may be a DAF film. Attaching the first dicing film 06 includes attaching the first adhesive layer 061, the first dicing layer 062, and the first tightening ring 063, peeling the first demolding layer 032 by a laser demolding process after attaching the first dicing film 06 to remove the first carrier 031, and cleaning to remove the first adhesive layer 033 and other impurities.
In this embodiment, attaching the first cutting film 06 can avoid the risk of cracking during subsequent cutting.
In another embodiment of the present application, before step S40, the method further includes:
S4021, attaching a second cutting film 07 on one side of the second dielectric layer 053 far away from the first carrier 031 (as shown in FIG. 9);
s4022, removing the first carrier plate 031;
S4023 a third dicing film 08 formed on a side of the first dielectric layer 023 remote from the second dicing film, and the second dicing film 07 is removed (as shown in fig. 10);
The first dicing film 06 is attached to a side of the second dielectric layer 053 away from the first carrier 031, and the third dicing film 08 is removed (as shown in fig. 8).
Specifically, the first dicing film 06, the second dicing film 07, and the third dicing film 08 may be DAF films. Attaching the second dicing film 07 includes attaching a second adhesive layer 071, a second dicing layer 072, and a second tensioner 073, and after attaching the second dicing film 07, peeling the first film-removing layer 032 by a laser film-removing technique to remove the first carrier 031, and cleaning to remove the first adhesive layer 033 and other impurities.
In this embodiment, when the first carrier 031 is removed, the second dicing film 07 may be wrinkled, which affects subsequent dicing and causes cracking. Therefore, attaching the third dicing film 08 to the side of the first dielectric layer 023 remote from the second dicing film 07 includes attaching the third adhesive layer 081, the third dicing layer 082, and the third stretcher 083. Then the second cutting film 07 is removed, then the first cutting film 06 is attached to the side, far away from the first carrier 031, of the second dielectric layer 053, and then the third cutting film 08 is removed, and the attached first cutting film 06 is not wrinkled at this time, so that subsequent cutting is not affected, and generation of splinters is further avoided.
In another embodiment of the present application, step S40 includes:
The silicon bridge substrate 01 (shown in fig. 11) after the first and second redistribution structures 02 and 05 are formed is cut based on the first cutting film.
In the present embodiment, the silicon bridge substrate 01 after the first and second redistribution structures 02 and 05 are formed is cut based on the first cutting film, and the problem of occurrence of cracking at the time of cutting can be reduced. And the yield of the bridge chips formed after cutting is improved.
It should be noted that the bridge chip is formed by the preparation method, and the specific details thereof can be referred to each other.
Based on the above structure of the bridge chip, the present application further provides a package structure, referring to fig. 30, the package structure includes:
The first chip 20 and the first plastic layer 14 surrounding the first chip 20, wherein the first chip 20 is a chip structure of the bridge chip provided by the application after the first dielectric layer 023 and the second dielectric layer 053 are removed (as shown in fig. 32);
the second chip 16 is positioned on one side of the first chip 20 and the first plastic sealing layer 14 and is connected with the first chip 20;
The second plastic layer 17 is located on one side of the second chip 16 away from the first chip 20 and covers the second chip 16.
Specifically, the first chip 20 is a bridge chip provided by the present application, and the first dielectric layer 023 and the second dielectric layer 053 are removed, that is, the first chip 20 exposes the first bonding pad 021 and the second bonding pad 051.
The first plastic layer 14 surrounds the first chip 20 and the metal posts 12, and the second chip 16 is a functional chip and is mounted on the side of the first chip 20 provided with the first bonding pads 021. A third re-wiring structure 15 is formed on the side of the first chip 20 where the first pads 021 are disposed, for connecting the first pads 021 and the second chip 16. The second plastic layer 17 covers the second chip 16 for protecting the second chip 16.
A fourth re-wiring structure 18 and a third pad 19 are further provided on the side of the first chip 20 where the second pad 051 is provided, the fourth re-wiring structure 18 is used for connecting the second pad 051 and the third pad 19, and the third pad 19 is used for connecting an external circuit.
In the present embodiment, the first chip 20 in the package structure is formed of the bridge chip in the present application. The first bonding pad 021, the second bonding pad 051 and the structures on two sides are adopted for bridging, so that direct contact with the silicon bridge substrate 01 is avoided, the problem of short circuit of a bridging chip is further avoided, and the yield of the packaging structure is improved.
In another embodiment of the present application, the package structure further includes:
A third re-wiring structure 15 located between the first chip 20 and the second chip 16;
The fourth rewiring structure 18 is located on a side of the first chip 20 remote from the second chip 16.
Specifically, the third re-wiring structure 15 is connected to the first pads 021 to bridge the structures on both sides. The third re-wiring structure 15 may be provided with a multi-layered metal interconnection structure, and a photosensitive resin material may be provided between the metal interconnection structures. It should be noted that the number of the substrates, only a part of the structure is schematically shown in the figure.
After removing the second carrier 09 and exposing the second pads 051, the fourth re-wiring structure 18 may be formed on the side of the first chip 20 remote from the second chip 16 to achieve high-density interconnection. It should be noted that the fourth re-wiring structure 18 may include a third dielectric layer 181, and the third dielectric layer 181 may include a via 182, where the via 182 exposes at least the second pad 051 and the metal pillar 12.
In this embodiment, the third redistribution structure 15 may further implement high-density interconnection, and improve interconnection performance. The fourth re-wiring structure 18 may be formed to connect the second pads 051 to achieve interconnection of the two-sided structure, and improve interconnection performance.
Based on the packaging structure, the application also provides a preparation method of the packaging structure, and the electrical connection realized by the bridge chip is adopted. Referring to fig. 21, the manufacturing steps of the package structure include:
s11, providing a second carrier 09 (as shown in fig. 22).
The second carrier 09 may be a carrier for support including, but not limited to, a glass carrier.
And S12, attaching a third chip 13 to one side of the second carrier 09, and forming a first plastic layer 14 surrounding the third chip 13, wherein the third chip 13 is a bridge chip provided by the application (as shown in FIG. 23).
The third chip 13 is a bridge chip provided by the application. The material of the first plastic layer 14 may include, but is not limited to, an Epoxy Molding Compound (EMC).
It should be noted that before the third chip 13 is attached, the second release layer 10 and the second adhesive layer 11 may be formed on one side of the second carrier 09 in sequence, then the metal pillars 12 are formed on the second adhesive layer 11, the metal pillars 12 are used for implementing electrical connection, then the third chip 13 is attached to the second adhesive layer 11, and the first plastic layer 14 also surrounds the metal pillars 12 to protect the third chip 13 and the metal pillars 12.
And S13, grinding the third chip 13 and the side, away from the second carrier 09, of the first plastic sealing layer 14 to expose the first bonding pads 021 (shown in FIG. 24) of the third chip 13.
Grinding may include, but is not limited to, a chemical mechanical polishing process. During polishing, part of the metal posts 12, part of the first plastic layer 14 and the first dielectric layer 023 of the third chip 13 are polished simultaneously, and the first pads 021 are exposed after the first dielectric layer 023 is polished. Subsequent connection of the second chip 16 may be achieved after the first pads 021 are exposed.
And S14, attaching a second chip 16 on the side, far away from the second carrier 09, of the third chip 13, and forming a second plastic layer 17 (shown in FIG. 26) covering the second chip 16.
The second chip 16 may be a functional chip, and the second chip 16 may be mounted by flip-chip mounting, or may be mounted by hybrid bonding, etc., without limitation. The first pad 021 of the third chip 13 is conducted with the second chip 16. The second molding layer 17 covers the second chip 16 to protect the second chip 16. The material of the second plastic layer 17 may include, but is not limited to, an Epoxy Molding Compound (EMC).
It should be noted that, after forming the second molding layer 17, a ring cutting process is further included to remove a portion of the second molding layer 17 so as to facilitate the area of the second carrier 09.
The second carrier 09 is removed with the second molding layer 17 as a support to expose the second dielectric layer 053 of the third chip 13 (as shown in fig. 27).
The second plastic layer 17 is used as a supporting layer, and the second stripping layer 10 is stripped by adopting a laser stripping process to remove the second carrier plate 09, and is cleaned to remove the second adhesive layer 11 and other impurities.
The second dielectric layer 053 and the first molding layer 14 are polished to expose the second pads 051 of the third chip 13 (as shown in fig. 28).
The second dielectric layer 053 and the first molding layer 14 are polished, which may include, but is not limited to, a chemical mechanical polishing process. When the second dielectric layer 053 is polished, even if the metal column 12 and the metal material on the second bonding pad 051 migrate, the metal material will not enter the silicon substrate 011 of the silicon bridge substrate 01 on the second insulating layer 052 of the second redistribution structure 05, thereby avoiding the short circuit problem of the bridge chip and improving the yield of the packaging structure.
In this embodiment, since the third chip 13 is a bridge chip in the present application, the first redistribution structure 02 and the second redistribution structure 05 are located at two sides of the silicon bridge substrate 01, and the structures of the first bonding pad 021, the second bonding pad 051 and two sides are adopted to bridge, so that direct contact with the silicon bridge substrate 01 is avoided, so that when the second dielectric layer 053 is ground, metal materials cannot migrate into the silicon substrate 011 of the silicon bridge substrate 01, the problem of short circuit of the bridge chip is avoided, and the yield of the package structure is improved.
In another embodiment of the present application, after step S13, the method includes:
forming a third re-wiring structure 15 on a side of the third chip 13 away from the second carrier 09 (as shown in fig. 25);
A fourth re-wiring structure 18 is formed on a side of the third chip 13 away from the second chip 16, and the fourth re-wiring structure 18 includes a third dielectric layer 181 (shown in fig. 29).
Specifically, a third re-wiring structure 15 is formed on a side of the third chip 13 away from the second carrier 09, and the third re-wiring structure 15 is connected to the first pads 021 to bridge the structures on both sides.
The third re-wiring structure 15 may be provided with a multi-layered metal interconnection structure, and a photosensitive resin material may be provided between the metal interconnection structures. It should be noted that the number of the substrates, only a part of the structure is schematically shown in the figure.
After removing the second carrier 09 and exposing the second pads 051, a fourth re-wiring structure 18 may be formed on the side of the third chip 13 remote from the second chip 16 to achieve high-density interconnection. It should be noted that the fourth re-wiring structure 18 may include a third dielectric layer 181, and the third dielectric layer 181 may include a via 182, where the via 182 exposes at least the second pad 051 and the metal pillar 12.
Thereafter, a conductive structure 183 (as shown in fig. 30) is formed in the via 182, and a third pad 19 (as shown in fig. 31) is formed on a side of the fourth re-wiring structure 18 remote from the third chip 13, so as to connect to an external circuit.
In this embodiment, the third redistribution structure 15 may further implement high-density interconnection, and improve interconnection performance. The fourth re-wiring structure 18 may be formed to connect the second pads 051 to achieve interconnection of the two-sided structure, and improve interconnection performance.
It should be noted that, the package structure is prepared by a preparation method of the package structure, and specific contents can be referred to each other.
In the description of the present specification, reference to the term "some embodiments," "another embodiment," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.
The technical features of the above embodiments may be arbitrarily combined, and for brevity, all of the possible combinations of the technical features of the above embodiments are not described, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The above examples illustrate only a few embodiments of the application, which are described in detail and are not to be construed as limiting the scope of the claims. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the application, which are all within the scope of the application. Accordingly, the scope of protection of the present application is to be determined by the appended claims.
Claims (10)
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