CN1299198C - Microcontroller architecture with increased code density due to changeable instruction format - Google Patents

Abstract

The invention relates to a microcontroller structure for improving the program code density by changeable instruction format, wherein the memory stores compressed instructions, each compressed instruction is composed of a group prefix and at least one index, and an instruction decompressor decompresses the compressed instruction to be executed into an original instruction format, wherein the instruction decompressor is provided with a plurality of instruction group decoding tables, each instruction group decoding table stores predetermined types of original instructions, the instruction decompressor selects an instruction group decoding table according to the group prefix of the compressed instruction, and takes out the corresponding original instruction of the instruction group decoding table.

Description

Microcontroller architecture with increased code density due to changeable instruction format

technical field

The present invention relates to the micro-controller structure of the embedded system, in particular to a micro-controller structure whose program code density is improved by a changeable instruction format.

Background technique

High integration is one of the very important features of an embedded system (Embedded System), and as the functions processed by embedded devices increase day by day, the capacity of the read-only memory (ROM) also increases accordingly. However, larger ROMs have gradually become a major factor affecting overall system cost, and may also be a bottleneck for instruction fetching, thereby further affecting execution performance.

To solve this problem, the technical challenge is: how to reduce the capacity of the ROM without sacrificing the system functionality and performance? The solutions proposed so far can be classified into two categories: (1) providing a compact version of the original instruction set structure (Compact Subset of the Original ISA), and (2) using the instruction block-oriented compression method (Instruction Blook Oriented Compression Scheme) .

Typical representatives of the aforementioned first scheme are ARM Thumb and SGI MIPS16, which are simplified versions of ARM and MIPS respectively. This kind of method is more commonly used in the instruction length of the original instruction set of 32 bits, and the instruction length of 16 bits is achieved by reducing the number of bits in each field, so it is a simplified version of the original instruction set. Taking MIPS as an example, MIPS instructions are 32-bit fixed-length instruction formats, which are divided into three categories: I (Immediate), J (Jump), and R (Register-to-Register). Taking class I as an example, as shown in Figure 1, it consists of fields of operation code (Opcode), source register (Source Register), target register (Target Register), and immediate value (Immediate Value). Under certain pre-standard conditions, if the length of each field is reduced, the corresponding Type I 16-bit compact version (as shown in MIPS16 in the figure) can be obtained.

From this similar method, the MIPS compact version instruction set MIPS16 can be defined. Therefore, the program code expressed using MIPS16 will reduce its length. In terms of hardware, as shown in FIG. 2 , MIPS16 decompression logic 22 needs to be additionally added to decompress (restore) the MIPS16 instructions extracted in the instruction cache memory 21 into MIPS instructions, and then feed them into the original standard It is executed in MIPS pipeline 23.

The foregoing solution has the following disadvantages: (1) Usually, the simplified instruction set cannot exist alone, and must coexist with the original instruction set structure, thus reducing flexibility. (2) Because it is a simplified version and also a subset, it will increase the number of original program instructions and reduce the compression effect. (3) The hardware implementation is completed sequentially with the assistance of decompression logic, so it may affect the original pipeline design and cause a critical path (Critical Path), thereby reducing the execution speed. (4) Different degrees of compression optimization (Optimization) are not performed for different applications, but the benefits of customization (ustomization) are provided.

In addition, typical representatives of the aforementioned second type of solutions are IBM CodePack and Wolfe CCRP (Compressed Code RISC Processor). In order to achieve the effectiveness of decompression during execution, most of this scheme uses modified Huffman coding as the compression algorithm, uses the Instruction Cache Line as the compression unit, and compresses the compressed Programs are stored in main memory, while instruction cache stores decompressed instructions.

Taking CCRP as an example, Figure 3 shows the organizational structure of the memory system in CCRP. As mentioned above, the instruction memory 31 (Instruction Memory) stores the compressed program code, while the instruction cache memory 32 (Instruction Cache) stores uncompressed instructions; in addition, the cache memory backfill engine 33 (Cache Refill Engine) then Responsible for the action of instruction decompression. When the program is executed, if a cache hit (Cache Hit) occurs, the central processing unit 34 (CPU) directly fetches the uncompressed instruction sequence for execution. However, when a cache memory access miss (Cache Miss) occurs, the cache memory backfill engine 33 will extract the compressed instruction from the instruction memory 31, perform decompression, and then store the decompressed instruction into the instruction In the cache memory 33, then the CPU 34 extracts the instruction just stored from the instruction cache memory 32 to continue execution.

In addition, the memory system also uses a line address table 311 (Line Address Table, LAT) and a cache line address buffer 35 (Cache Line Address Lookaside Buffer, CLB). The row address table 311 is generated by the compression software tool during the compression stage, and is used to map the address of the uncompressed instruction block to the address of the compressed instruction block, so as to solve the control transfer (ControlTransfer) instruction The problem caused by the inconsistency of the branch target address (Branch Target Address). The cache line address mapper 35 is used to assist the use of the line address table 311 to reduce the time required for instruction backfill when the cache memory access misses.

The foregoing solution has the following disadvantages: (1) When the size of the command block decreases, the additional burden of the LAT storage table increases. (2) In the microcontroller (Microcontroller) or lower-level embedded applications, there is no instruction cache memory, so this method is not suitable for these systems. (3) Different degrees of compression optimization are not performed for different applications, but the benefits of customization are provided.

Therefore, it can be seen that the aforementioned known techniques for reducing the size of the program code still have many shortcomings, and cannot meet the actual needs, so there is still a need for improvement.

Contents of the invention

The purpose of the present invention is to provide a micro-controller structure with a changeable instruction format to increase the density of the program code, and to reduce the read-only memory by compressing the instruction without sacrificing the system functionality and execution performance. Capacity requirements, thereby reducing the overall system cost.

To achieve the aforementioned object, the microcontroller structure of the present invention includes:

A memory storing compressed instructions, wherein each compressed instruction is composed of a group prefix and at least one index;

a compressed instruction buffer for storing and buffering instructions fetched from the memory;

The next address logic, according to the current state of the microcontroller, decides whether to fetch the instruction from the memory, or directly send the next instruction in the compressed instruction buffer; and

an instruction decompressor for decompressing the current compressed instruction sent from the compressed instruction buffer into an original instruction format;

Wherein, the instruction decompressor has a plurality of instruction group decoding tables, each instruction group decoding table stores a predetermined type of original instruction, and the instruction decompressor selects an instruction group decoding table according to the group prefix of the compressed instruction , and use the index of the compressed instruction to search and retrieve the corresponding original instruction from the instruction group decoding table.

It includes a decoding and execution unit to decode decompressed instructions into hardware control signals to control the execution core to perform corresponding actions.

The command decoder includes a command group extractor and a multiplexer, the command group extractor is used to decompose the current compressed command sent from the compressed command buffer, so as to control the multiplex according to the group prefix of the compressed command The multiplexer selects an instruction group decoding table, and uses the index of the compressed instruction to search for the corresponding original instruction in the instruction group decoding table, and outputs the multiplexer to the decoder and execution unit for execution.

This memory is a read-only memory.

The compressed instructions stored in the memory are formed by adding an instruction index to a first group prefix, and the instruction index value is used to search a first instruction group decoding table, and the first instruction group decoding table stores the corresponding original instruction.

The compressed instruction stored in the memory is composed of a second group prefix plus an operation code index representing the branch condition code and a displacement index representing the branch destination address, and the operation code index and the displacement index are respectively used for searching The first and second decoding sub-tables of a second instruction group decoding table, the first decoding sub-table stores the branch condition code of the corresponding original instruction, and the second decoding sub-table stores the branch destination bit of the corresponding original instruction site.

The compressed instructions stored in the memory are appended with an operation code index representing an operation code and an immediate index representing an immediate value by a third group prefix, and the operation code index and the immediate index are respectively used to search a third instruction group The third and fourth decoding sub-tables of the decoding table, the third decoding sub-table stores the operation code of the corresponding original instruction, and the fourth decoding sub-table stores the corresponding immediate value of the original instruction.

The memory also stores a program code of a fourth group prefix appending original instructions.

The group prefix is of fixed length.

Instructions that occur more frequently in this memory have shorter group prefixes.

Description of drawings

Below with preferred embodiment and in conjunction with accompanying drawing, the present invention is described in detail, wherein:

Figure 1 shows the mapping relationship between known MIPS and MIPS16 instructions;

Fig. 2 schematically shows the hardware structure of the known MIPS16 system;

Fig. 3 schematically shows the memory system structure of known CCRP;

Figure 4 shows a solution to provide embedded system design using the microcontroller architecture of the present invention;

Fig. 5 shows the relationship between the customized instruction and the decoding table according to the present invention;

Fig. 6 shows the block diagram of microcontroller structure of the present invention;

FIG. 7 shows a block diagram of the instruction decompressor in the microcontroller architecture of the present invention.

Detailed ways

Regarding a preferred embodiment of the structure of the micro-controller that improves the program code density by the changeable instruction format of the present invention, please refer to the structure shown in FIG. 4 to provide a solution for embedded system design. The design is based on the following properties:

(1) In an embedded system, the specific functions of the application program do not change at any time, that is, in the product development stage, the specifications and characteristics of the program are roughly fixed.

(2) In general, both assembly language code and compiler-generated code tend to use only a small number of all available instructions.

Therefore, as shown in Figure 4, in the program development phase (Coding Phase), the aforementioned scheme is the same as the traditional method, and the application program can still be written in an assembly language or a high-level language (for example: C), and the original instruction set (uncompressed ) constitutes the execution file 43. Then, in the encoding (compression) stage (Encoding Phase), the executable file 44 formed by the custom instruction set 46 (compression) and the information available for decoding can be obtained with the assistance of compression software tools (such as: Profiler, Translator). 45, to be further used in the hardware design of the microcontroller structure 41.

The above-mentioned customized instruction set 46 can be classified into different instruction groups (Instruction Group) according to the characteristics of the original instructions (such as frequency of occurrence and instruction format), and then expressed in a more compact manner to achieve the effect of instruction compression. For example: use less number of bits to represent more frequently occurring instructions, and this new customized instruction represents the index value of a certain table; and the micro-controller structure 41 can use the table lookup (Table Lookup) method to correspond to The original command or directly decode the control signal.

FIG. 5 shows an example of the relationship between the aforementioned custom command and the decoding table of the information available for decoding. In this example, it is assumed that the original commands are grouped into four command groups:

G1: R-Group (Instruction without Immediate), this instruction group is usually composed of the simplest instructions, it is not an instruction of control transfer, nor an instruction containing immediate value.

G2: C-Group (Control Transfer), this type refers to the command that contains control transfer, and usually it also contains address fields with different purposes.

G3: I-Group (Instruction with Immediate), this type of instruction is an instruction with immediate value, but not a control transfer instruction.

G4: M-Group (Miscellaneous Instruction), this type refers to unclassified instructions.

For G1-type instructions, the corresponding customized instructions are formed by adding an instruction index (Instruction Index) field to the Group Prefix GI, where the instruction index value is used to search the corresponding GI instruction group decoding table 51, and the corresponding original instructions are stored in the GI instruction group decoding table 51.

For the G2 type instruction, the corresponding customized instruction is composed of the group prefix G2 with an Opcode Index representing the divergent condition code and a Displacement Index field representing the divergent destination address. , and these two index values are respectively used to search two different decoding sub-tables 521 and 522 of the G2 instruction group decoding table 52, and the decoding sub-table 521 stores the branch destination address of the corresponding original instruction. Thus, different information can be mapped to form a complete instruction decoding.

For the G3 type instruction, the corresponding customized instruction is added with an operation code index (Opcode Index) representing the operation code and an immediate index (Immediate Index) representing the immediate value by the group prefix G3, and the two index values They are two different decoding sub-tables 531 and 532 for searching the G3 instruction group decoding table 53 respectively, and the decoding sub-table 531 stores the operation code of the corresponding original instruction, and the decoding sub-table 532 stores the corresponding original The immediate value of the instruction. Thus, different information can be mapped to form a complete instruction decoding.

The G4 type of instruction belongs to the instruction without compression, so this type does not need to be decompressed into the original instruction format with the decoding table, but decoded in the original way. Therefore, the corresponding customized instruction is determined by the group word The first G4 appends the original instruction (Original Instruction).

The aforementioned group prefixes G1-G4 can be of fixed length (for example, 2 bits), or can be codes of variable length, such as assigning shorter codes to those with higher frequency of occurrence according to Huffman coding. Group prefix for commands of type .

The G1-G4 instruction group summarized above is just an example. In actual application, it can be clearly defined according to the characteristics of the application program and hardware implementation considerations, combined with the Profiling information, to define the classification method and total number of instruction groups, Options such as the format and length of the group prefix, and the length of the custom command can be optimized according to different applications to achieve the effect of customization. The obvious limitation is that the instruction length of most customized instructions must be smaller than the length of the original instruction, so as to achieve the effect of instruction compression.

The customized order after the compression is carried out by microcontroller structure 41 of the present invention, and Fig. 6 promptly has shown the block diagram of microcontroller structure 41 of the present invention, and it comprises a memory 61, a compressed instruction buffer 62, next Address logic 63, an instruction decompressor 64, and a decoding and execution unit 65, wherein, the memory 61 is used to store the compressed program code, because the program code of the embedded system does not need to be modified, so the memory 61 is relatively Preferably it is a read only memory (ROM).

The compressed instruction buffer 62 is used by the micro-controller to store and buffer the contents of the blocks fetched from the memory 61 when fetching instructions. Since the instruction length of the customized instruction is smaller than that of the original instruction, the compressed instruction buffer 62 may contain several compressed instructions.

The function of the next address logic 63 is to decide whether to fetch instructions from the memory 61 or directly send the next instruction in the compressed instruction buffer 62 according to the current state of the microcontroller.

The instruction decompressor 64 is used to decompress (restore) the current compressed instruction sent by the compressed instruction buffer 62 into the original instruction format, and then further feed it into the decoding and execution unit 65, and then decode it by the control signal decoder 651. A hardware control signal is issued to control the execution core 652 to perform corresponding actions. The control signal decoder 651 and the execution core 652 are common microcontrollers, so their structures will not be described in detail here.

And by the use of the aforementioned next address logic 63 and the decompressed instruction buffer 62, the microcontroller can correctly extract the instructions to be executed, and its mode of operation is shown in the following steps:

(1) The next address logic 63 knows the address of the next instruction to be accessed according to the current internal state of the microcontroller.

(2) The compressed instruction buffer 62 informs the next address logic 63 of information such as the number of instructions contained therein, so as to determine whether the instruction to be executed exists in the compressed instruction buffer 62 .

(3) If it does not exist in the compressed instruction buffer 62 , the next address logic 63 will send out the address of the instruction to be accessed, so that the memory 61 can fetch the next instruction. Then skip to step (5) for execution.

(4) If it exists in the compressed instruction buffer 62, the compressed instruction buffer 62 selects the correct instruction from the fetched instruction block, and feeds it to the instruction compressor 64 for decompression. Then skip to step (1) for execution.

(5) Store the content of the block extracted from the memory 61 into the internal buffer of the compressed instruction buffer 62 and perform alignment.

(6) Determine the length of the compressed command according to the prefix of the command group.

(7) In this way, the compressed instruction buffer 62 can know how many compressed instructions are included in the instruction block, and the boundary of each compressed instruction. The above related information is notified to the next address logic 63 through the control signal.

The extracted compressed instructions are then decompressed into original instructions by the instruction decompressor 64. FIG. Table 50, and a multiplexer 643, wherein the command group extractor 641 is used to decompose the current compressed command sent by the compressed command buffer 62, so as to control the compressed command according to the content of the group prefix of the compressed command The multiplexer 643 selects an instruction group decoding table 50, and uses the value of the index column of the compressed instruction to search for the corresponding original instruction in the instruction group decoding table 50, and outputs it to the decoder by the multiplexer 643 Execute with execution unit 65 .

In addition, the information of the aforementioned instruction group decoding table 50 can be obtained with the assistance of the compression software tool Translator, and these tables can be implemented using a Programmable Logic Array (PLA), and then programmed in the mass production stage. In addition, since the present invention has classified according to the characteristics of the instructions when ordering new instructions, these decoding tables do not form a single large table, but are composed of some small tables. Based on this feature, the decompression action completed by table query will not cause impact on the hardware, nor will it cause a long access time.

As can be seen from the above description, the present invention can re-order the structure of the instruction set by analyzing and collecting the original instruction code characteristics of the application program during the product development period, so as to reduce the size of the program code, and the new instruction represents the index value of a certain table. The decoding circuit can use the table query method to correspond to the original instruction. Therefore, compared with the known technology, the present invention has the following advantages:

(1) Using a changeable instruction format and one-to-one instruction level compression, it is suitable for lower-level embedded systems (for example: the application of microcontrollers).

(2) According to the requirements of different embedded applications, the customized instruction set structure is used to optimize and compress the original sequences, thereby providing customized benefits.

(3) The result of optimization and compression can obtain higher program code density (Code Density) and less program code, thereby reducing the demand for ROM capacity.

(4) Because the program code density is improved and the instruction extraction utilization rate is increased, the memory bus traffic (Memory Bus Traffic) is reduced, thereby reducing the power consumption of the overall system.

(5) In the product development stage, software and hardware collaborative design (Software/HardwareCodesign) is adopted, thus improving the cost effectiveness (Cost-Effective).

In summary, the present invention shows that it is different from the known technology in terms of purpose, means and effect. It should be noted that the above-mentioned embodiments are only examples for ease of description, and the scope of rights claimed by the present invention should be The scope of the patent application shall prevail, rather than being limited to the above-mentioned embodiments.

Claims (9)

1, a kind of microcontroller architecture that is improved the procedure code closeness by changeable order format is characterized in that, mainly comprises:

One storer stores the instruction after the compression, and wherein, the instruction of each compression is made of the additional at least one index of group's prefix;

One condensed instruction impact damper will be in order to being deposited buffering from the instruction that storer extracted;

Whether one next address logic instructs from memory fetch, or directly the next instruction of condensed instruction impact damper is sent with decision according to the current state of microcontroller; And

One instruction decompressor will be in order to being de-compressed into the presumptive instruction form by the present condensed instruction that this condensed instruction impact damper is sent;

One decoding and performance element is decoded into the hardware controls signal with the instruction that will decompress, and carries out core execution corresponding action to control;

Wherein, this instruction decompressor has a plurality of order bloc decoding tables, each order bloc decoding table stores the presumptive instruction of predefined type, this instruction decompressor is selected an order bloc decoding table according to group's prefix of this condensed instruction, and searches the corresponding presumptive instruction of taking out this order bloc decoding table with the index of this condensed instruction.

2, microcontroller architecture as claimed in claim 1, it is characterized in that, wherein, the instruction decompressor comprises an order bloc extractor and a multiplexer, this order bloc extractor is in order to being decomposed by the present condensed instruction that this condensed instruction impact damper is sent, group's prefix with the foundation condensed instruction is controlled this multiplexer, select an order bloc decoding table, and search with the index of condensed instruction and to take out corresponding presumptive instruction in this order bloc decoding table, and export this decoding and performance element to execution by this multiplexer.

3, microcontroller architecture as claimed in claim 1 is characterized in that, wherein, this storer is a ROM (read-only memory).

4, microcontroller architecture as claimed in claim 1, it is characterized in that, wherein, the stored condensed instruction of this storer is made of the additional instruction index of one first group's prefix, this instruction index value is used to search one first order bloc decoding table, and this first order bloc decoding table is deposited corresponding presumptive instruction.

5, microcontroller architecture according to claim 1, it is characterized in that, wherein, the stored condensed instruction of this storer is made of the operation code index of the additional expression difference condition code of one second group's prefix and the shift index of an expression difference purpose address, this operation code index and this shift index are respectively in order to search first and second decoding sublist of one second order bloc decoding table, this first decoding sublist is deposited the difference condition code of corresponding presumptive instruction, and this second decoding sublist is deposited the difference purpose address of corresponding presumptive instruction.

6, microcontroller architecture as claimed in claim 1, it is characterized in that, wherein, the stored condensed instruction of this storer is represented the index immediately of immediate value by the operation code index and of the additional expression operation code of one the 3rd group's prefix, this operation code index and this immediately index respectively in order to search one the 3rd order bloc decoding table the 3rd and the 4th the decoding sublist, the 3rd decoding sublist is deposited the operation code of corresponding presumptive instruction, and the 4th decoding sublist is deposited the immediate value of corresponding presumptive instruction.

7, microcontroller architecture as claimed in claim 1 is characterized in that, wherein, also stores the procedure code of the additional presumptive instruction of a four group group prefix in this storer.

8, microcontroller architecture as claimed in claim 1 is characterized in that, wherein, this group's prefix is a regular length.

9, microcontroller architecture as claimed in claim 1 is characterized in that, wherein, the higher instruction of the frequency of occurrences has short group's prefix in this storer.

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