CN1295768C - Integrated Circuit or Discrete Components Ultra-thin Footless Packaging Technology and Packaging Structure - Google Patents

Abstract

The invention relates to an integrated circuit or discrete component ultra-thin pin-less packaging process and a packaging structure thereof, which comprises the following process steps: taking a substrate; coating dry ink on the substrate; etching the chip area and the inner pin area of the routing on the substrate; coating a layer of metal, metal activation layer, copper metal or alloy layer on the substrate; plating a silver layer or a nickel layer and a palladium layer on the copper metal or the alloy layer in the inner pin area of the routing; stripping the dry ink layer; coating silver glue on the copper or alloy layer of the chip area; implanting a chip on the silver colloid; routing operation; plastic packaging operation; laser printing; stripping the bottom metal substrate; sticking on the blue glue film; and (5) dividing the envelope. The invention has the advantages of strong weldability, excellent quality, lower cost, smooth production, strong applicability, high efficiency of the cutting machine and the blade, flexible arrangement of multiple chips, no occurrence of various troubles of plastic permeation and environmental protection.

Description

Integrated Circuit or Discrete Components Ultra-thin Footless Packaging Technology and Packaging Structure

Technical field:

The invention relates to an ultra-thin and footless packaging process for integrated circuits or discrete components and a packaging structure thereof. It belongs to the technical field of packaging of integrated circuits or discrete components.

Background technique:

The traditional ultra-thin and footless packaging process of integrated circuits or discrete components and its packaging structure, its packaging type is an array-type assembly that is cut into a single unit. Its substrate type is etched. It mainly has the following deficiencies:

1. Special adhesive tape is required. In order to prevent the plastic from penetrating into the lead frame during high-pressure encapsulation, increasing the risk of solder joint insulation, and if the post-treatment of plastic penetration occurs, it is easy to destroy the metal layer of the solder joint. Affects weldability, so material cost, post-processing cost and quality all have a certain degree of influence.

2. In order to make the wire bonding process and output solder joints can be produced smoothly in this process, expensive palladium materials are plated on both sides of the substrate. In addition to the relatively high cost of electroplating, the wire bonding parameters must also be set for this material Due to the special parameters, the smoothness of the production line is directly affected by the inconsistency of the parameters.

3. The substrate is generally made of CU194, which has a conductivity of only 65% and a relatively slow heat dissipation rate, which is only suitable for general logic or low-power products.

4. Because the use of special chemical tape and the solvent of the tape in various high-temperature processes are easy to vaporize due to high temperature, the aluminum pad that covers the chip, that is, the inner foot of the wire, is indirectly polluted or covered, which often causes instability in the wire bonding ability.

5. Because this product is made of plastic and copper, the same blade and blade rotation speed cannot be used to divide the array integrated circuit or discrete component assembly under different materials, and the two blades cannot be the same, and if When forcing the use of the same blade, that is, the speed parameter, the life of the blade will be greatly reduced. Of course, the maintenance cost and quality will be affected to a certain extent.

6. Due to the limitation of the traditional technology, the solder joints of multiple chips and different outputs can only be arranged in a rigid manner, and the flexibility is obviously greatly reduced.

7. Due to the limitation of the traditional process, the output solder joints are as flat as the bottom of the plastic package, and there is even a risk of depression, while flux, rust remover and other chemicals are all used in surface mounting. It cannot be discharged smoothly, so the solderability will be greatly reduced.

Invention content:

The purpose of the present invention is to overcome the above disadvantages, to provide a welding ability, high quality, low cost, smooth production, strong applicability, cutting tools and blades can play the highest efficiency, flexible arrangement of multi-chip, will not All kinds of troubles caused by plastic penetration, as well as the ultra-thin and footless packaging process and packaging structure of environmentally friendly integrated circuits or discrete components.

The purpose of the present invention is achieved in this way: an ultra-thin and footless packaging process for integrated circuits or discrete components and its packaging structure, including the following process steps:

1) Take a piece of metal substrate with suitable thickness;

2) Dry ink coating is carried out on the metal substrate, and its purpose is to facilitate the subsequent procedure of insulating unnecessary areas in metal plating in necessary areas. The area on the metal substrate that is not coated with dry ink forms the chip area and the inner foot area for wiring;

3) On the metal substrate, etch the chip area and the inner foot area of the wire bonding. The purpose is to facilitate the bottom metal of each metal layer to expose the surface of the ink-colored colloid, so that the bottom of the plastic package can be adhered to the surface. , the adhesion ability is better, and it is not easy to produce the phenomenon of air or empty soldering in the surface adhesion solder joints;

4) Sputter a layer of metal on the metal substrate in the chip area and the wire-bonding inner foot area, and the main function of this metal is to exert the reliability and conductivity of the metal's adhesion ability when performing surface adhesion;

5) Sputter a layer of metal activation layer on the metal layer in the chip area and the wire-bonding inner pin area, and the main function of this metal activation layer is to play the activation role of metal and copper metal or alloy layer in the implementation of the bidirectional surface, so that Two different metal layers above and below the metal activation layer can be tightly bonded;

6) A layer of copper metal or alloy layer is sputtered on the metal activation layer in the chip area and the wire-bonding inner pin area, and the main function of this copper metal or alloy layer is to serve as the real bearing base of the chip, and because it is Copper metal or alloy, so the conductivity and heat dissipation performance are very good;

7) Sputter a layer of silver metal or nickel metal or palladium metal layer on the copper metal or alloy layer in the inner foot area of the wire, and the main function of this metal layer is to play a smooth and firm connection between the metal wire and the inner foot area of the wire perform a tight fit;

8) Peel off the dry ink that was originally on the metal substrate, and prepare for subsequent packaging/testing operations;

9) Coating silver glue on the copper metal or alloy layer in the chip area, so as to facilitate the subsequent wafer adhesion procedure;

10) Implant the chip in the chip area that has just been coated with silver glue, and then perform post-curing of the silver glue according to the characteristics of the silver glue to make a semi-finished product of integrated circuits or discrete components;

11) The semi-finished product that has completed the chip implantation operation is carried out according to the characteristics of the product;

12) Perform plastic encapsulation of the semi-finished products that have been wired;

13) Laser print the semi-finished product that has completed the plastic encapsulation operation on the surface of the plastic encapsulation body;

14) The semi-finished product that has completed the plastic encapsulation operation is stripped off the underlying metal substrate, so that the position of each joint solder joint can be seen completely in the black encapsulation;

15) After peeling off the metal substrate, paste the front side of the product's plastic package on the blue film to prepare for the subsequent colloid cutting operation;

16) After attaching the completed product to the blue adhesive film, the glue can be cut with a cutting machine, so that the integrated circuits or discrete components that were originally connected together in the form of a display assembly, and after cutting each Individual integrated circuits or discrete components can be independent.

The purpose of the present invention can also be achieved in the following way: an ultra-thin package structure for integrated circuits or discrete components, including a chip carrier base, a wire-bonded inner leg carrier base, a chip, metal wires and an encapsulation layer, which is characterized in that :

a) The bottom layer of the chip carrying base and the inner foot carrying base for wiring is a metal layer;

b) On the metal layer of the chip carrying base and the metal layer of the wiring inner pin carrying base, first sputter a layer of metal activation layer, and then sputter a layer of copper metal or alloy layer;

c) A layer of silver metal, nickel metal or palladium metal layer is sputtered on the copper metal or alloy layer of the inner foot of the wiring;

d) Coating a silver glue layer on the copper metal or alloy layer of the chip carrying base;

e) Implanting the chip on the silver glue layer of the chip carrying base;

f) The uppermost chip of the chip carrying base and the upper surface of the silver metal, nickel metal or palladium metal layer on the uppermost layer of the inner foot carrying base of the wire bonding are respectively connected to both ends of the metal wire;

g) Except for the bottom layer of the chip carrier base and the bottom layer of the inner leg carrier base for wire bonding, the periphery of the chip carrier base, the inner leg carrier base for wire bonding, chips and metal wires are all encapsulated with plastic.

The ultra-thin and footless packaging process and packaging structure of the integrated circuit or discrete components of the present invention also adopts an array-type assembly and cuts it into a single unit. The substrate type is to use the substrate to grow other required metals. Compared with the traditional integrated circuit or discrete component packaging process and structure, the present invention has the following advantages:

1. There is no need to use special high-temperature and high-pressure tape materials, so the material cost is low, and there will be no waste of costs such as various troubles of plastic penetration and poor quality.

2. The front side of the substrate for the chip adopts the traditional silver-plating method on the inner foot part of the wire bonding. Make the function of the chip achieve the highest transmission and heat dissipation function, but the cost will not increase.

3. The substrate is made of pure copper or alloy, and its conductivity and heat dissipation can reach almost 100%. In addition to general logic products, it is also very suitable for medium and high power products.

4. There is no need to use any chemical tape at all, so there is no need to consider the problem of pollution.

5. When the new type of package is cut, the part of the package has no materials of different materials to be cut together. Therefore, in the case of only one material, the cutting machine and blade can exert the highest efficiency and quality. Also relatively stable.

6. Due to the adoption of the new packaging technology and structure, the solder joints in the chip area or the wire bonding output can have full capacity and space.

7. With the new packaging structure, you can choose whether to use the output solder joints that protrude from the surface of the package, so that the single-point independent welding can maintain the solderability of the current general chip, and you will not worry about surface mount The instability of time, of course, the quality is more stable than the traditional package type.

Description of drawings:

1 to 19 are schematic diagrams of each process of the ultra-thin and leadless packaging process for integrated circuits or discrete components of the present invention.

FIG. 20 is a schematic diagram of the structure of an ultra-thin package without pins for integrated circuits or discrete components of the present invention.

Detailed ways:

1) Referring to Figure 1, take a piece of metal substrate A with a suitable thickness. The material of the metal substrate can be changed according to the function and characteristics of the chip, such as: alloy or copper;

2) Referring to FIG. 2, dry ink B coating is carried out on the metal substrate A. The area on the metal substrate that is not coated with dry ink forms the chip area C1 and the inner foot area C2 for wiring;

3) Referring to FIG. 3, etch the chip area C1 and the inner foot area C2 of the wiring on the metal substrate;

4) Referring to FIG. 4, a layer of pure metal layer 1 is sputtered on the metal substrates A1 and A2 in the chip area C1 and the wire bonding inner pin area C2;

5) Referring to FIG. 5, on the pure metals 11 and 12 in the chip area C1 and the wire-bonding inner foot area C2, a layer of metal activation layer 2 is sputtered, such as an aluminum layer or a nickel, titanium, silver, or gold layer;

6) Referring to FIG. 6 , on the metal activation layers 21 and 22 in the chip area C1 and the wire bonding inner pin area C2, a layer of pure copper metal or alloy layer 3 is sputtered;

7) Referring to Fig. 7, on the pure copper metal or alloy layers 31, 32 in the chip area C1 and the wire-bonding inner foot area C2, a layer of metal activation layer 41, 42 is sputtered, and the main function of this metal activation layer is to exert The pure copper metal or alloy layer and the silver or nickel layer are activated on the two-way surface, so that the two different metal layers above and below the metal activation layer can be tightly bonded;

8) Referring to FIG. 8, on the metal activation layers 41, 42 in the chip region C1 and the wire-bonding inner pin region C2, a layer of silver metal, nickel metal or palladium metal layer 51, 52 is sputtered;

9) Referring to FIG. 9, the dry ink B previously on the metal substrate A is stripped off;

10) Referring to FIG. 10, silver glue 61 is coated on the silver metal or nickel metal or palladium metal layer 51 in the chip area C1;

11) Referring to Figure 11, the chip area C1 that has just been coated with silver glue is implanted with the chip 7, and after completion, the silver glue is post-cured according to the characteristics of the silver glue to make a display of integrated circuits or discrete components. Aggregate semi-finished products;

12) Referring to Figure 12, the semi-finished product that has completed the chip implantation operation is performed according to the characteristics of the product for wire bonding 8 operations;

13) Referring to Fig. 13, except for the bottom metal layer 1, the semi-finished product that has been wire-bonded is subjected to plastic encapsulation 9 operations, and the plastic encapsulation and post-curing operation is performed according to the characteristics of the plastic, so that the bottom metal layer 1 protrudes from the plastic Encapsulation body 9 outside;

14) Referring to Figure 14, the semi-finished product that has completed the plastic encapsulation and post-curing operations is laser printed 10;

15) Referring to Figure 15, the semi-finished product that has completed plastic encapsulation and post-curing operations is stripped off the underlying metal substrate A;

16) Referring to Figure 16, after the stripping operation of the metal substrate layer is completed, the product function test operation can be carried out, and the test method can not only use the whole chip array assembly probe test method, but also use a single integrated circuit or Test methods for discrete components;

17) Referring to Figure 17, after the metal substrate has been stripped off, attach the colloid front of the product to the blue adhesive film E;

18) Referring to Figure 18, after attaching the completed product to the blue film, the plastic package can be cut with a cutting machine;

19) Referring to Figure 19, use the pick-and-place conversion equipment to suck out the encapsulation of individual integrated circuits or discrete components from the blue adhesive film E one by one, and place them in the plastic carrier tray. Referring to FIG. 20 , the ultra-thin leadless package structure of integrated circuits or discrete components is mainly composed of chip carrier base X, wire-bonded inner leg carrier base Y, chip 7 , metal wire 8 and encapsulation layer 9 . Its characteristics are:

a) The bottom layer of the chip carrying base X and the inner foot carrying base Y for wiring are metal layers 11 and 12;

b) On the metal layers 11, 12 of the chip carrying base X and the metal layer 11, 12 of the wire-bonding inner pin carrying base Y, a layer of metal activation layer 21, 22 is sputtered first, and then a layer of copper metal or alloy layer 31, 32 is sputtered;

c) On the copper metal or alloy layers 31, 32 of the chip carrying base X and the inner leg carrying base Y for bonding, first sputter a layer of metal activation layer 41, 42, and then sputter a layer of silver metal or nickel metal or palladium metal layers 51, 52;

d) On the silver metal or nickel metal or palladium metal layer 51 of the chip carrying base 1, a layer of silver glue layer 61 is coated;

e) chip 7 is implanted on the silver glue layer 61 of the chip carrying base X;

f) The uppermost surface of the chip 7 on the chip carrier base X and the uppermost layer of the silver metal or nickel metal or palladium metal layer 52 on the inner foot carrier base Y for bonding is connected to both ends of the metal wire 8;

g) In addition to the bottom layer 11 of the chip carrier base X and the bottom layer 12 of the inner foot carrier base Y for wire bonding, the periphery of the chip carrier base X, the inner leg carrier base Y for wire bonding, the chip 7 and the metal wire 8 are all encapsulated with plastic 9 encapsulation.

Claims (10)

1. An ultra-thin and footless packaging process for integrated circuits or discrete components, characterized in that it comprises the following process steps: 1) Take a metal substrate (A); 2) Coating dry ink (B) on the metal substrate (A), the area on the metal substrate that is not coated with dry ink forms the chip area (C1) and the inner leg area (C2) for wiring; 3) Etching the chip area (C1) and the inner leg area (C2) for wiring on the metal substrate (D); 4) Sputtering a layer of metal (1) on the metal substrates (A1, A2) in the chip area (C1) and the wire bonding inner foot area (C2); 5) Sputtering a layer of metal activation layer (2) on the metal layers (11) and (12) of the chip area (C1) and the wire bonding inner pin area (C2); 6) Sputtering a layer of copper metal or alloy layer (3) on the metal activation layers (21) and (22) in the chip area (C1) and the wire bonding inner foot area (C2); 7) Sputtering a layer of silver metal, nickel metal or palladium metal layer (52) on the copper metal or alloy layer (32) in the inner leg area (C2) of the wire bonding; 8) peeling off the dry ink layer (B) originally above the metal substrate (A); 9) Coating silver glue (61) on the copper metal or alloy layer (31) in the chip area (C1); 10) Implant the chip (7) in the chip area (C1) that has just been coated with silver glue, and perform post-curing of the silver glue after completion to make an integrated circuit or a semi-finished product of a display assembly of discrete components; 11) Perform wire bonding (8) on the semi-finished product that has completed the chip implantation operation; 12) Perform plastic encapsulation (9) on the semi-finished product that has been wired; 13) Perform laser printing (10) on the surface of the plastic encapsulation (9) of the semi-finished product that has completed the plastic encapsulation; 14) Perform the stripping operation of the bottom metal substrate (A) on the semi-finished product that has completed the plastic encapsulation; 15) After peeling off the metal substrate, paste the colloidal front of the product on the blue adhesive film (E); 16) After attaching the completed product to the blue film, divide the plastic package (9). 2. An ultra-thin and footless packaging process for integrated circuits or discrete components according to claim 1, characterized in that before peeling off the dry ink layer, the copper metal or alloy layer (31) in the chip area (C1) ) is sputtered with a metal activation layer (41) or/and a metal layer (51), which is a silver layer or a nickel layer or a palladium layer. 3. An ultra-thin and footless packaging process for integrated circuits or discrete components according to claim 1 or 2, characterized in that on the copper metal or alloy layer (32) in the inner foot area (C2) of the bonding wire, after sputtering One layer of metal activation layer (42) is sputtered earlier before one layer of silver metal or nickel metal or palladium metal layer (52). 4. An ultra-thin and leadless packaging process for integrated circuits or discrete components according to claim 1, characterized in that the metal activation layer (2) is an aluminum layer or a nickel, titanium, silver, or gold layer. 5. An ultra-thin and footless packaging process for integrated circuits or discrete components according to claim 2, characterized in that the metal activation layer (2) is an aluminum layer or a nickel, titanium, silver, or gold layer. 6. An ultra-thin and footless packaging process for integrated circuits or discrete components according to claim 3, characterized in that the metal activation layer (42) is an aluminum layer or a nickel, titanium, silver, or gold layer. 7. An ultra-thin and leadless packaging process for integrated circuits or discrete components according to claim 1 or 2, characterized in that after the stripping of the metal substrate layer is completed, the product function test is performed. 8. An ultra-thin leadless packaging structure for integrated circuits or discrete components, including a chip carrying base (X), a wire-bonded inner foot carrying base (Y), a chip (7), metal wires (8) and an encapsulation layer ( 9), characterized in that: a) The bottom layer of the chip carrying base (X) and the inner foot carrying base (Y) for wiring is a metal layer (11, 12); b) On the metal layers (11, 12) of the chip carrier base (X) and the wire-bonding inner pin carrier base (Y), first sputter a layer of metal activation layer (2), and then sputter a layer of copper metal or alloy layer (31, 32); c) sputtering a layer of silver metal, nickel metal or palladium metal layer (52) on the copper metal or alloy layer (32) of the inner foot carrying base (Y) for wiring; d) Coating a silver glue layer (61) on the copper metal or alloy layer (31) of the chip carrying base (X); e) chip (7) is implanted on the silver glue layer (61) of the chip carrying base (X); f) The uppermost surface of the uppermost chip (7) of the chip carrying base (X) and the uppermost silver metal or nickel metal or palladium metal layer (52) of the wire-bonding inner foot carrying base (Y) is connected with the metal wire (8) respectively ) connected at both ends; g) In addition to the bottom layer (11) of the chip carrier base (X) and the bottom layer (12) of the inner leg carrier base (Y) for wire bonding, the chip carrier base (X), the inner leg carrier base (Y) for wire bonding, and the chip ( 7) and the periphery of metal wire (8) are all encapsulated with plastics (9). 9. An ultra-thin and footless packaging structure for integrated circuits or discrete components according to claim 8, characterized in that before coating a layer of silver glue (61), the copper metal or alloy in the chip area (C1) On the layer (31), one deck of metal activation layer (41) or/and one deck of metal layer (51) is sputtered earlier, and the metal layer is a silver layer or a nickel layer or a palladium layer. 10. An ultra-thin leadless packaging structure for integrated circuits or discrete components according to claim 8 or 9, characterized in that on the copper metal layer (32) of the inner leg bearing base (Y) of the wire bonding, after sputtering One layer of metal activation layer (42) is sputtered before one layer of silver metal, nickel metal or palladium metal layer (52).

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