CN1262006C - Single electron memory having carbon nano tube structure and process for making it - Google Patents

Abstract

The invention discloses a single-electron dynamic random storage device and a preparation method thereof. The device uses silicon as a substrate, and there is a silicon oxide insulating layer on the substrate, and a nanowire is etched into a metal or polysilicon layer on the silicon oxide insulating layer, and one end of the nanowire is a data wire lead. There are two control gates on both sides of the nanowire parallel to the two sides of the nanowire. The storage unit is the part of the nanowire longer than the control gate, and extends between the two electrodes of the carbon nanotube transistor. The normal operation of the memory can be realized by controlling dozens or even a few electrons, and it is not affected by random background charges, which solves the stability, power consumption, heat dissipation and gate leakage current faced in the development of traditional memory. The problem of ultra-high density storage of information under low power consumption can be realized.

Description

Single-electron memory device prepared by using carbon nanotubes and its preparation method

technical field

The invention belongs to memory devices, in particular to a single-electron memory designed and prepared using carbon nanotubes.

Background technique

Memory accounts for 40% of the world's semiconductor market. Semiconductor products other than memory are updated every 2 years, while memory is a generation every 18 months. Taking the development of dynamic memory (DRAM) as an example, in 1988 Japan The line width of the lines on the silicon chip reached 0.8 microns, and the 4Mb DRAM came out, thus entering the era of ultra-large-scale integration ULSI; in 1992, the 16Mb chip with a line width of 0.5 microns was put into production; in 1994, the 64Mb chip with a line width of 0.35 microns was launched. Chip production; 0.13-micron 4Gb DRAM will soon be realized. However, maintaining the trend of continuous scale reduction is facing an extremely serious challenge, that is, the capacitance in the storage unit cannot be too small. If the capacitance is too small to provide enough electrons to the amplifier, the entire memory will be flooded by noise, and the The reliability of information storage cannot be guaranteed; at the same time, the number of electrons in each storage unit will become smaller and smaller with the further improvement of the integration of storage devices, and the MOS field effect transistors in the memory will gradually become unstable.

In order to continue to maintain the high-speed development of memory devices, people hope to replace traditional memory devices with single-electron memory devices. Metal-oxide-semiconductor field-effect transistor (MOSFET) is used to prepare single-electron dynamic random access memory (J.Appl.Phys.2000, 12, 8594), although this device solves several problems such as power consumption that plague traditional memories, but This device uses the MTJ/MOSFET structure, which limits the further improvement of the integration level, because the size of the MOSFET cannot be too small, otherwise the number of working electrons is too small, which will affect the stability of the device. If the gate of the device is divided into three parts, and the split gate MOSFET is used to reduce the charge required for operation, the device will be less integrated. It can be seen that the existence of MOSFET is an important factor limiting the performance improvement of this kind of dynamic memory. If you want to obtain a DRAM with a higher integration level, you must find a better memory system to replace the MTJ/MOSFET system.

Contents of the invention

The purpose of the present invention is to solve the problems of stability, power consumption, heat dissipation and gate leakage current faced by the development of traditional memory and single-electron memory, in order to further improve the integration of devices and realize information sharing under low power consumption. Ultra-high-density storage, thereby utilizing the Coulomb blocking effect of nanowires to provide a single-electron memory with a carbon nanotube structure.

The invention has a nanowire/carbon nanotube transistor storage structure, and realizes information storage through the Coulomb blocking effect of the nanowire. Therefore, the size of the Coulomb blocking region must enable the storage unit to have two distinct storage states, and the control gate of the nanowire can be used to control the size of the Coulomb blocking region of the nanowire. Assuming that electrons can only reach the storage unit of the memory through multiple quantum dots in the nanowire under an external field, in order to avoid the influence of quantum fluctuations, the tunneling resistance in the nanowire should be larger than the quantum resistance, and the quantum resistance R _q =h/ e ² ≈26kΩ (h is Planck's constant). Assuming that after a certain voltage is applied to the control gate of the nanowire, the width of the Coulomb blocking region in the nanowire is 2V _c , and a bias voltage is applied to the pin of the data line, beyond the Coulomb blocking region, electrons will tunnel through the quantum dots in the nanowire, Until the Coulomb blockage occurs again in the system, according to the different bias voltages applied to the data line pins, the control data line pins can form two voltages with different levels on the storage unit at the other end: +V _c , -V _c . The two stable storage states reflect that the storage unit stores different numbers of electrons. In order to increase the operating frequency of the device and reduce power consumption, it is hoped that the number of electrons should be as small as possible, but it must be ensured that there are obvious and distinguishable differences between the two stable states. , that is, the readout of data can be realized, and such a memory device can realize the mutual transition between two stable storage states as long as it controls a few electrons. The voltage of the memory cell is expressed by the following formula:

$\mathrm{<span\; class="notranslate">\; V</span>}<span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; Q</span>}}{{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; \&Sigma;</span>}}}$

Among them, Q is the charge number in the storage unit, and C _∑ is the total capacitance of the storage unit. For this system, the storage capacitance mainly includes two parts: the capacitance C _s between the storage unit and the substrate; the capacitance C _t between the storage unit and the carbon nanotube. Assuming that the voltage of the storage cell is 0 when the charge is neutral, the state of the charge -ne is stored in the storage cell (n represents the number of extra electrons relative to the charge neutral, which can be positive or negative, and the different signs represent the entry and exit of electrons), so we can get:

$\mathrm{<span\; class="notranslate">\; V</span>}<span\; class="notranslate">\; =</span>\frac{<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; ne</span>}}{{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; the\; s</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; t</span>}}}$

The thickness of the oxide layer is very thin, C _s >>C _t in the system, $C_{\mathrm{the\; s}}=\frac{\mathrm{\&epsiv;S}}{d}.$ ε is the dielectric constant, S is the area of the memory cell, and d is the thickness of the oxide layer between the memory cell and the substrate. The voltage of the memory cell is affected by the size of the Coulomb blocking area in the nanowire, and its two stable states are at the edge of the Coulomb blocking area, that is, |V|=V _c , so:

$\frac{\mathrm{<span\; class="notranslate">\; e</span>}}{\mathrm{<span\; class="notranslate">\; \&epsiv;</span>}}<span\; class="notranslate">\; \&Center\; Dot;</span>\frac{<span\; class="notranslate">\; |</span>\mathrm{<span\; class="notranslate">\; no</span>}<span\; class="notranslate">\; |</span>\mathrm{<span\; class="notranslate">\; d</span>}}{{\mathrm{<span\; class="notranslate">\; SV</span>}}_{\mathrm{<span\; class="notranslate">\; c</span>}}}<span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; 1</span>}$

For a memory, e and ε can be regarded as constants, and the variable ranges of d and _Vc among the other four variables are very small. In order to reduce the charge required for work, the area S of the memory cell must be reduced as much as possible. The storage unit of this device is a part of the nanowire, this part does not have the control gate of the nanowire to deplete, and the area can be made very small; at the same time, due to the fluctuation of the potential energy in this part of the nanowire, there is no electron storage in a part of the area, so The equivalent capacitance of the memory cell is smaller than the result of the geometrical calculation, so that a small charge can cause a large voltage change on the memory cell.

The storage unit on the nanowire is also the gate of the carbon nanotube transistor, which can be used to change the carrier concentration in the carbon nanotube. In the case of constant source-drain voltage, the gate can be used to control the density of the carbon nanotube. current. The state information in the memory cell can be read out by measuring the current in the carbon nanotube.

There are two basic conditions for the normal operation of the single-electron memory of the present invention: 1) the Coulomb blocking region can be controlled to appear in the nanowire through the voltage applied to the control gate of the nanowire, and this region should be large enough; 2) the storage unit is used as a carbon nanotube The gate of the transistor has two stable storage states, and the difference between the drain currents corresponding to these two stable states (with different gate voltages) must be large enough to ensure that the memory can accurately read the data stored in the system and information.

In order to further improve the storage performance of the single-electron memory of the present invention, it is necessary to strictly control the values of several basic parameters in the process of preparation and use. First of all, the larger the Coulomb blocking area of the nanowire, the better, which can make the two storage states have obvious differences and facilitate data readout. In order to achieve such a goal, the width of the nanowire should be minimized; at the same time, the operating voltage (the voltage on the control gate of the nanowire) should be appropriately increased, because the size of the Coulomb blocking area increases with the voltage of the control gate of the nanowire. increase and increase. But if the nanowire is very thin and the operating voltage is high, the device may not work, that is to say, the nanowire is completely exhausted at this time, and no current can pass through this nanowire. Second, the smaller the storage unit, the better. Finally, maximize the capacitance between the carbon nanotubes and the memory cell (which is also the gate of the carbon nanotube transistor). For a given nanowire and operating voltage, the magnitude of the Coulomb blocking region 2V _c is constant. The capacitance C _t between the carbon nanotube and the memory cell is:

C _t =2πεL/log(2h/r)

where ε is the dielectric constant, L is the width of the memory cell, r is the diameter of the single-walled carbon nanotube, and h is the distance between the carbon nanotube and the memory cell. A voltage change of 2V _c causes charges in the carbon nanotubes

$\mathrm{<span\; class="notranslate">\; \&Delta;Q</span>}<span\; class="notranslate">\; /</span>\mathrm{<span\; class="notranslate">\; Q</span>}<span\; class="notranslate">\; \&Proportional;</span>{\mathrm{<span\; class="notranslate">\; 2</span>}\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; c</span>}}{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; t</span>}}<span\; class="notranslate">\; /</span>\mathrm{<span\; class="notranslate">\; L</span>}<span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; 4</span>}\mathrm{<span\; class="notranslate">\; \&pi;\&epsiv;</span>}{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; c</span>}}<span\; class="notranslate">\; /</span>\mathrm{<span\; class="notranslate">\; log</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 2</span>}\mathrm{<span\; class="notranslate">\; h</span>}<span\; class="notranslate">\; /</span>\mathrm{<span\; class="notranslate">\; r</span>}<span\; class="notranslate">\; )</span>$

The relative change is:

Where Q is the total number of charge carriers in the carbon nanotubes. The larger ΔQ/Q is, that is, the greater the change of the carrier concentration in the carbon nanotube is, the greater the current change caused by the change of the gate voltage is. In order to improve the accuracy of the memory read process, ΔQ/Q must be increased as much as possible. For a given nanowire and operating voltage, V _c is constant, in order to increase ΔQ/Q, it is necessary to decrease h and increase r. It can be seen that in the preparation process, the distance between the storage unit and the carbon nanotubes needs to be reduced, and single-walled carbon nanotubes with larger diameters should be used. In order to optimize the storage performance of the device, various factors affecting the memory have to be considered comprehensively, because the improvement of a storage performance index is often at the expense of other performances.

The purpose of the present invention is achieved like this:

In the single-electron memory provided by the present invention, silicon is used as a substrate, and a silicon oxide insulating layer is prepared by dry oxygen or wet oxygen oxidation. nanowire and carbon nanotube transistors. The nanowire has a multi-tunnel junction structure, and the function of the memory can be realized by utilizing the Coulomb blocking effect of this structure and capacitive coupling with a carbon nanotube transistor at the same time. Nanowires, control gates, memory cells and electrode areas are all formed by etching the metal or silicon layer on the oxide layer. One end is a small rectangular data line pin. The width of the nanowire is 1 nanometer to 1 nanometer. The length is 10 nanometers to 1 millimeter, and the height is 1 nanometer to 1 micrometer; there are two control gates parallel to the nanowire on both sides of the nanowire, and the width of the nanowire and the control gate is 1 nanometer to 1 millimeter. The length of the control gate of the nanowire is smaller than the length of the nanowire, so only a part of the nanowire can be depleted by the control gate of the nanowire, and the section of the nanowire that is not depleted constitutes the memory cell of the memory, and this section is not depleted by the control gate. The depleted part extends between the two electrode regions formed by etching; a carbon nanotube is placed on the insulating layer close to the storage unit, and the distance from the storage unit is 1 nanometer to 500 microns. The electrodes of the carbon nanotube transistors are prepared at both ends of the memory, or an electrode layer is prepared on the two electrode regions, and the carbon nanotubes are placed on it to form the carbon nanotube transistor part of the memory. The storage unit is not only the storage part of the charge, but also the gate of the carbon nanotube transistor, and the amount of stored charge affects the current between the two electrodes of the carbon nanotube transistor.

The substrate also includes a catalyst area, the catalyst area is located inside an electrode, and the carbon nanotube has good ohmic contact with the two electrodes.

The memory preparation method provided by the present invention comprises the following steps:

1) Using silicon as the substrate of the device, a layer of polysilicon is grown by molecular beam epitaxy, and the polysilicon is doped, or a layer of metal is deposited by electron beam evaporation, and a layer of metal is deposited by electron beam lithography and etching. Preparation of nanowires, control gates, memory cells and electrode regions, all of which are formed by etching the metal or silicon layer on the oxide layer;

2) Take a carbon nanotube and place it on the electrode area prepared by etching, use the atomic force microscope (AFM) to locate the carbon nanotube, and use FIB technology to deposit platinum on the two poles of the carbon nanotube as the carbon nanotube transistor. electrode, that is, to prepare the memory carbon nanotube transistor part; or prepare the electrode first and then position the carbon nanotube to prepare the nanotube transistor part; or use the in-situ growth technology of the carbon nanotube to realize the preparation and positioning of the carbon nanotube, and A carbon nanotube transistor portion is formed.

3) The device is packaged using conventional semiconductor technology, and the preparation of the single-electron memory of the present invention is completed.

The advantage of the present invention is that: the method for preparing the single-electron memory of the present invention avoids excessive doping processes and reduces preparation steps.

Since the device uses carbon nanotube transistors instead of traditional MOSFETs, the unique electrical, mechanical and chemical properties of carbon nanotubes can be fully utilized, so the designed memory structure has higher storage density than previous single-electron memories based on MTJ/MOSFET designs , which are not affected by random background charges and can work at higher temperatures. At the same time, the chemical inertness and good toughness of carbon nanotubes determine that the device has a very long service life. These advantages make the present invention can well solve the difficulties faced in the development process of memory. Compared with other types of memory, it has many advantages. advantages.

Traditional dynamic random access memory (DRAM) requires a transistor and a capacitor to store a bit, and its storage density is limited by the size of the storage capacitor, which is caused by the working principle of DRAM. The static random access memory SRAM needs 4 to 6 transistors to store a bit. It can be seen that the single-electron random storage of the present invention can have a higher storage density, because there is no traditional transistor in the device, which avoids the difficulties brought about by further reduction in scale, such as gate leakage. Simultaneously this DRAM based on carbon nanotube has very low power consumption, and it does not need to control a large amount of electrons to realize the change between the switch state of memory like traditional DRAM, single electronic memory of the present invention only needs to control A few or even dozens of electrons can realize the conversion of the device between the two states, so the heat dissipation of this kind of memory is very low, which ensures that the improvement of the integration of the device will not be limited by the heat dissipation problem. Compared with traditional memory, it has obvious advantages. Using such a low-power single-electron memory device can solve the energy crisis faced by the development of traditional DRAM.

The traditional metal-oxide-semiconductor field-effect transistor (MOSFET) needs to be doped in the source and drain regions to form the source and drain, so it is impossible to make the MOSFET small, so the existence of MOSFET in single-electron memory is largely The improvement of device integration is limited, and the advantages of single-electron memory cannot be displayed to the maximum extent. The single-electron memory of the present invention can make the size very small by using the carbon nanotube transistor. The device of the present invention uses a section of nanowires that are not depleted by the control gate of the nanowires as a memory unit. Compared with the previously designed memory based on the MTJ/MOSFET structure, the geometric size is smaller, and at the same time due to the potential energy in this part of the nanowires Fluctuations, the part actually used to store charge is even smaller. The advantage of using a small capacitor to store charges is that it reduces the number of charges required for the memory to work, that is, the number of charges that need to be controlled by the memory cell to change between -V _c and +V _c on the edge of Coulomb blocking is very small. The advantage of doing this is that the size of each storage unit is reduced, which can further increase the storage density.

Since the memory provided by the present invention can use carbon nanotubes as lead wires on each electrode, the circuit capacitance and RC time can be small, and the integrated device has a high operating frequency, which can reach more than 100 GHz.

In a word, the single-electron memory of the present invention has the following advantages over the traditional memory: 1) high operating frequency, 2) high storage density, 3) low power consumption, and 4) small heat dissipation.

Description of drawings

FIG. 1 is a three-dimensional schematic view of the single-electron memory of the present invention.

FIG. 2 is a schematic plan view of the single-electron memory of the present invention.

Figure 3 is the relationship between the electrostatic chemical potential of the nanowire and the Fermi energy level of the storage unit and the data line pin in the case of no bias applied to the data line pin of the memory.

Figure 4. The relationship between the electrostatic chemical potential of the memory and the Fermi energy level of the memory cell and the data line pin when the negative bias voltage is applied to the data line pin of the memory. Electrons enter the memory cell from the data line pin, so that the memory cell is finally at -V _c .

Figure 5. The relationship between the electrostatic chemical potential of the nanowire and the Fermi energy level of the memory unit and the data line pin when the data line pin is positively biased. The electrons escape from the memory unit, and the storage unit is finally at +V _c .

Fig. 6 is the variation curve of the drain current of the carbon nanotube transistor with the gate voltage under ideal conditions.

Figure 7 The state of the voltage pulse and drain current of the data line pin when the memory writes and reads "0" and "1".

Fig. 8 is a schematic diagram of the structure of the memory device prepared by the in-situ growth technology of carbon nanotubes.

Marked in the figure:

1-Data line pin 2-Nanowire control grid 3-Nanowire

4-electrode area 5-single-walled carbon nanotubes 6-storage unit

7-Oxide layer 8-SOI substrate 9-Catalyst area

Detailed ways

Example 1:

According to Fig. 1, the single-electron memory with carbon nanotube structure of the present invention is fabricated.

Choose (001) oriented silicon as the substrate 8, use the oxygen oxidation method, the oxidation temperature is 900°C, oxidize a 25 nm thick silicon dioxide insulating layer 7, and prepare a silicon dioxide insulating layer 7 by molecular beam epitaxy (MBE). A polysilicon layer with a thickness of 20 nanometers is heavily doped with arsenic to form an n-type semiconductor layer with a doping concentration of 5×10 ^{13 -2} .

In the prepared silicon layer, the electrode area 4, the data line pin 1, the control grid 2 of the nanowire and the nanowire 3 are prepared by using the electron beam photolithography method and the dry etching technology. The pin width of the data line is 80 nanometers; the size of the control gate of each nanowire is 80 nanometers wide and 80 nanometers long; the length of the nanowire is 120 nanometers long and 40 nanometers wide; Width. Platinum electrodes were fabricated using focused ion beam (FIB) technology, including two carbon nanotube transistor electrodes with a thickness of 30 nanometers, a width of 30 nanometers, and a length of 50 nanometers, with an interval of 60 nanometers between them.

A single-walled carbon nanotube 5 with a diameter of 1 nanometer and a length of 150 nanometers is precisely positioned using an atomic force microscope AFM, so that the two ends of the tube are placed at the two ends of the electrode of the carbon nanotube transistor, between the carbon nanotube 5 and the memory unit 6 The distance is 3 nm. Finally, the device is packaged.

Example 2:

According to Fig. 1, the single-electron memory with carbon nanotube structure of the present invention is fabricated.

(001)-oriented silicon is selected as the substrate 8, and a silicon dioxide insulating layer 7 with a thickness of 25 nanometers is oxidized by using a dry oxygen oxidation method at an oxidation temperature of 900°C. A gold layer with a thickness of 30 nm was prepared by electron beam evaporation.

In the prepared gold layer, the electrode area 4, the data line pin 1, the control gate 2 of the nanowire and the nanowire 3 are prepared by electron beam photolithography and etching technology. The pin width of the data line is 90 nanometers; the size of the control gate of each nanowire is 100 nanometers wide and 100 nanometers long; the length of the nanowire is 160 nanometers long and 40 nanometers wide; wide; gold electrode 4, including two 30 nanometers thick, 50 nanometers wide, 50 nanometers long electrodes of carbon nanotube transistors, the distance between the two is 40 nanometers.

The positioning of the carbon nanotubes 5 is the same as that in Embodiment 1.

Example 3:

According to Fig. 8, the single-electron memory with carbon nanotube structure of the present invention is fabricated.

Choose (001) oriented silicon as substrate 8, use dry oxygen oxidation method, oxidation temperature is 900°C, oxidize a silicon dioxide insulating layer 7 with a thickness of 25 nanometers, and prepare a silicon dioxide insulating layer 7 by molecular beam epitaxy (MBE). A polysilicon layer with a thickness of 20 nanometers is heavily doped with arsenic to form an n-type semiconductor layer with a doping concentration of 6×10 ^{13 -2} .

In the prepared silicon layer, the data wire pin 1 , the control grid 2 of the nanowire and the nanowire 3 are prepared by using an electron beam photolithography method and a dry etching technology. The pin width of the data line is 80 nanometers; the size of the control gate of each nanowire is 80 nanometers wide and 80 nanometers long; the length of the nanowire is 110 nanometers long, 30 nanometers wide, and 45 nanometers high; the geometric size of the memory cell is 30 nanometers long and 30 nm wide. Using photolithography, evaporation and height-stripping techniques, a gold electrode 4 is prepared, including two carbon nanotube transistor electrodes with a thickness of 20 nanometers, a width of 50 nanometers, and a length of 100 nanometers, with a distance of 90 nanometers between them. Place catalysts (Fe, Co, Ni and their alloys) on the inner side of the electrode 4 of the carbon nanotube transistor with the probe manipulation technology of the atomic force microscope, and grow the carbon nanotube 5 in situ so that it is in contact with the electrode 4 of the carbon nanotube transistor. The two inner sides of the contact, as shown in Figure 8. Finally, the device is packaged.

Example 4:

Part of the preparation method of the nanowires is the same as in Example 2, the preparation and positioning of the carbon nanotubes are the same as in Example 3, and the device is shown in FIG. 8 .

Example 5:

On the single-electron memories prepared in Example 1, 2, 3 or 4, carbon nanotubes are used as the leads on the electrodes.

Its three-dimensional structure of the device prepared according to the above embodiments 1 and 2 is shown in Figure 1, and Figure 2 is its schematic plan view, which mainly contains two basic components: a nanowire (MTJ) with a multi-tunnel junction structure; nanotube transistors. The nanowire is controlled by the control gate 2 of the nanowire on both sides. When the device is working, multiple quantum dots are formed in the nanowire. The properties of the nanowire are not affected by the specific position and size of each quantum dot. By applying a bias voltage to the control gate of the nanowire, the Coulomb blocking phenomenon of the nanowire can be observed. One end of the nanowire is connected to the pin of the data line, and the other end forms a capacitance because there is no depletion effect of the control gate of the nanowire. In the Coulomb blocking region, this capacitance can be regarded as isolated, that is, there is no leakage current. Applying a voltage pulse to pin 1 of the data wire pushes the device beyond the Coulomb blockade region, so that two stable voltage values appear at the other end of the nanowire. It can be seen that the part of the nanowires 6 without the depletion of the control gate of the nanowires is the storage unit of the memory, and the difference in the number of charges corresponds to different storage states. Place a single-walled carbon nanotube 5 on the two electrodes 4 of the carbon nanotube transistor, this part has just formed a carbon nanotube transistor structure, and the storage unit 6 is also the gate of this carbon nanotube transistor at the same time, if two The voltage difference between the electrodes remains constant, so the current between the two electrodes can be changed through the gate 6, that is to say, the magnitude of the current between the two electrodes reflects the different storage states of the memory.

By controlling the data line pin, two voltages with different heights can be formed at the memory cell at the other end. FIG. 3 shows a situation where there is no additional electronic storage in the storage unit 6 of the device. It can be assumed that the voltages of the storage unit 6 and the data line pin 1 are both 0 at this time. Figure 4 shows the state where the bias voltage of the data line pin 1 exceeds the coulomb blockage area of the nanowire 3. At this time, electrons enter the storage unit 6 from the data line pin 1, and the nanowire can be approximated as a section of resistance. The final result is to make N electrons Reaching storage unit 6 brings the system to the edge of Coulomb blockade. If the voltage of the data line pin 1 is removed, the storage unit 6 is stable at the state of -V _c due to the presence of Coulomb blockade. Similarly, when a voltage of +V _c is applied to the data line pin 1 (as shown in FIG. 5 ), electrons will flow from the storage unit 6 to the data line pin 1, and finally the storage unit 6 reaches a stable state of +V _c .

Figure 6 shows the relationship between the source-drain current and the gate voltage of a typical single-walled carbon nanotube transistor. Due to the existence of the nanowire Coulomb blocking region, the gate (storage unit 6) is between +V _c and - Two stable storage states are obtained at V _c , and the carriers in the carbon nanotubes are holes, so the corresponding drain current at -V _c is larger.

The working condition of the single-electron memory of the present invention is shown in FIG. 7 . A bias voltage is applied on the control gate of the nanowire to squeeze the nanowire, and a square wave pulse is input to the data line pin. The magnitude of the pulse voltage can make the system exceed the Coulomb blockade area. At this time, the electrons will enter and exit the storage unit through the nanowire, so that The memory cell forms two stable memory states with different voltage values at the edge of the Coulomb blockade region. At the same time, the memory cell is also the gate of the carbon nanotube transistor, so the drain current corresponds to two currents of different magnitudes (that is, "1" or "0" stored in the memory cell).

Claims (8)

1. a single-electron memory that utilizes made of carbon nanotubes comprises: as substrate, an oxide layer is arranged on this substrate with silicon, layer of metal or polysilicon layer are arranged on the oxide layer of substrate, prepare a nano wire, control gate thereon; Described nano wire is processed to form through etching by metal on the oxide layer that is positioned at substrate or polysilicon layer, one end of nano wire is a data pin, there are two control gates parallel with nano wire the both sides of nano wire, it is characterized in that: also comprise a memory cell and a carbon nanometer transistor, memory cell is the nano wire part longer than control gate, this part also extends between two electrode districts of carbon nano-crystal body pipe, memory cell is 1 nanometer to 500 micron apart from the distance of carbon nano-tube, and memory cell also is the grid of carbon nanometer transistor simultaneously.

2. want the 1 described single-electron memory that utilizes made of carbon nanotubes as right, it is characterized in that: described carbon nanometer transistor comprises a carbon nano-tube and is positioned at metal on the oxide layer of substrate or two electrode districts that polysilicon layer is processed to form through etching that wherein a carbon nano-tube is taken and is placed on two electrode districts.

3. want the 1 described single-electron memory that utilizes made of carbon nanotubes as right, it is characterized in that: the width of described nano wire is 1 nanometer to 1 micron, and length is 10 nanometers to 1 millimeter, highly is 1 nanometer to 1 micron.

4. want the 1 described single-electron memory that utilizes made of carbon nanotubes as right, it is characterized in that: the groove width of described control gate and nano wire is 1 nanometer to 1 millimeter.

5. want the 1 described single-electron memory that utilizes made of carbon nanotubes as right, it is characterized in that: described carbon nano-tube is a Single Walled Carbon Nanotube.

6. want the 1 described single-electron memory that utilizes made of carbon nanotubes as right, it is characterized in that: adopt the lead-in wire of carbon nano-tube as each electrode.

7. want the 1 described single-electron memory that utilizes made of carbon nanotubes as right, it is characterized in that: carbon nano-tube can directly be placed on the electrode of carbon nanometer transistor; Also can be to comprise a catalyst zone on substrate, described catalyst zone be positioned at the inboard of an electrode of carbon nano-crystal body pipe, and the electrode of carbon nano-tube two ends and carbon nanometer transistor has ohmic contact.

8. one kind prepares the method for utilizing the single-electron memory of made of carbon nanotubes as claimed in claim 1, it is characterized in that: may further comprise the steps:

1) with the substrate of silicon as device, utilize the method for molecular beam epitaxy to grow one deck polysilicon, polysilicon is mixed up, perhaps utilize the method for electron beam evaporation to deposit layer of metal, utilize electron beam lithography method and etching method preparing electrode district in the memory, nano wire, memory cell and control gate part through etching by metal on the oxide layer or silicon layer;

2) carbon nano-tube is placed on by the metal on the oxide layer or silicon layer and prepares in the memory on the electrode district through etching, utilize atomic force microscope AFM that carbon nano-tube is positioned, and utilize focused ion beam technology at the two poles of the earth of carbon nano-tube deposition platinum, as the electrode of carbon nanometer transistor, promptly prepare memory carbon nanometer transistor part; Perhaps preparing electrode earlier relocates carbon nano-tube and prepares the nanotube transistor part; The preparation and the location that perhaps utilize the in-situ growth technology of carbon nano-tube to realize carbon nano-tube, and form the carbon nanometer transistor part;

3) adopt conventional semiconductor technology that device is encapsulated.

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