CN113985955B - Bandgap reference circuit and control method - Google Patents
Bandgap reference circuit and control method Download PDFInfo
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- CN113985955B CN113985955B CN202111462894.2A CN202111462894A CN113985955B CN 113985955 B CN113985955 B CN 113985955B CN 202111462894 A CN202111462894 A CN 202111462894A CN 113985955 B CN113985955 B CN 113985955B
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- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is DC
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices
- G05F1/565—Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor
- G05F1/567—Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor for temperature compensation
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Abstract
本发明涉及一种带隙基准电路及控制方法，该带隙基准电路包括：恒流电源模块和补偿模块，恒流电源模块至少包括启动单元和电流镜单元，补偿模块包括至少一个增强型MOS管和至少一个耗尽型MOS管，PMOS管MP5的漏极与补偿模块中的第一增强型MOS管的漏极相连，第一增强型MOS管的源极与第二耗尽型MOS管的漏极相连；或PMOS管MP5的漏极与补偿模块中的第一耗尽型MOS管的漏极相连，第一耗尽型MOS管的源极与第二增强型MOS管的漏极相连，解决了现有采用BJT管的发射极‑基极电压的负温特性构建零温的带隙基准存在电路功耗大、电路复杂的问题，达到了实现电压零温的同时降低功耗和减小电路面积的效果。
The invention relates to a bandgap reference circuit and a control method. The bandgap reference circuit comprises: a constant current power supply module and a compensation module. The constant current power supply module comprises at least a start-up unit and a current mirror unit. The compensation module comprises at least one enhancement MOS tube and at least one depletion MOS tube. The drain of a PMOS tube MP5 is connected to the drain of a first enhancement MOS tube in the compensation module, and the source of the first enhancement MOS tube is connected to the drain of a second depletion MOS tube; or the drain of the PMOS tube MP5 is connected to the drain of a first depletion MOS tube in the compensation module, and the source of the first depletion MOS tube is connected to the drain of the second enhancement MOS tube. The problem of large circuit power consumption and complex circuit in the existing zero-temperature bandgap reference constructed by using the negative temperature characteristic of the emitter-base voltage of a BJT tube is solved, and the effect of reducing power consumption and circuit area while realizing voltage zero temperature is achieved.
Description
Technical Field
The invention relates to the technical field of power supply, in particular to a band gap reference circuit and a control method.
Background
The band gap reference voltage source is an indispensable component in an analog integrated circuit, and plays a vital role in the design of integrated circuits such as a lithium battery protection chip, an LED driving chip, a linear voltage regulator (LDO), a power management chip, an analog-to-digital converter (ADC), a digital-to-analog converter (DAC), a dynamic memory (DRAM), a Flash memory and the like.
Fig. 1 is a circuit diagram of a bandgap reference voltage source in the prior art, as shown in fig. 1, in which a bandgap reference voltage source in the prior art uses the negative temperature characteristic of the emitter-base voltage of a bipolar transistor (BJT) to construct a zero-temperature bandgap reference, that is, two bipolar transistors are used to bias the bandgap reference voltage source under different current densities, positive temperature current is generated through the difference between the base-emitter voltages of the two transistors, the positive temperature current flows through a certain number of resistors to generate positive temperature voltage, and the positive temperature voltage is superimposed with the base-emitter voltage (negative temperature voltage) of the bipolar transistor, so as to obtain a reference voltage independent of temperature.
In the prior art, a bipolar transistor is adopted as the band gap reference circuit, the working current is large, the power consumption is high, meanwhile, the base electrode of the bipolar transistor can flow current, and extra loss is caused.
Disclosure of Invention
The invention aims to provide a band gap reference circuit and a control method, which are used for solving the defects in the prior art, and the technical problem to be solved by the invention is realized by the following technical scheme.
In a first aspect, an embodiment of the present invention provides a bandgap reference circuit, where the bandgap reference circuit includes a constant current power supply module and a compensation module, the constant current power supply module includes at least a start-up unit and a current mirror unit, the compensation module includes at least one enhancement type MOS tube and at least one depletion type MOS tube, the enhancement type MOS tube and the depletion type MOS tube are connected in series, the start-up unit is connected with the current mirror unit, and a source electrode of a PMOS tube MP5 in the current mirror unit is connected with a preset voltage;
The drain electrode of the PMOS tube MP5 is connected with the drain electrode of the first enhancement type MOS tube in the compensation module, and the source electrode of the first enhancement type MOS tube is connected with the drain electrode of the second depletion type MOS tube;
Or the drain electrode of the PMOS tube MP5 is connected with the drain electrode of the first depletion type MOS tube in the compensation module, and the source electrode of the first depletion type MOS tube is connected with the drain electrode of the second enhancement type MOS tube.
Optionally, the compensation module comprises an enhanced NMOS tube and a plurality of depletion NMOS tubes,
The drain electrode of the PMOS tube MP5 is connected with the drain electrode of a first depletion type NMOS tube in the compensation module, the source electrode of the first depletion type NMOS tube is connected with the drain electrode of a second enhancement type NMOS tube, and the source electrode of the second enhancement type NMOS tube is connected with the drain electrode of a third depletion type NMOS tube until being connected to an N depletion type NMOS tube in series, wherein N is a natural number larger than 0.
Optionally, the source of the third depletion NMOS transistor and the drain of the fourth depletion NMOS transistor are connected in series,
The source electrode of the fourth depletion type NMOS tube is connected in series with the drain electrode of the fifth depletion type NMOS tube,
The source of the fifth depletion type NMOS tube is connected in series with the drain of the sixth depletion type NMOS tube,
The source of the sixth depletion type NMOS transistor is connected in series with the drain of the seventh depletion type NMOS transistor,
The source of the seventh depletion type NMOS transistor is connected in series with the drain of the eighth depletion type NMOS transistor,
The source of the eighth depletion type NMOS transistor is connected in series with the drain of the ninth depletion type NMOS transistor,
The source of the ninth depletion type NMOS transistor is connected in series with the drain of the tenth depletion type NMOS transistor,
The source of the tenth depletion type NMOS transistor is connected in series with the drain of the eleventh depletion type NMOS transistor,
The source of the eleventh NMOS transistor M11 (depletion NMOS transistor) is grounded.
Optionally, the compensation module comprises a depletion NMOS tube and a plurality of enhancement NMOS tubes,
The drain electrode of the PMOS tube MP5 is connected with the drain electrode of a first enhanced NMOS tube in the compensation module, the source electrode of the first enhanced NMOS tube is connected with the drain electrode of a second depletion type NMOS tube, and the source electrode of the second depletion type NMOS tube is connected with the drain electrode of a third enhanced NMOS tube until being connected to an Mth enhanced NMOS tube in series, wherein M is a natural number larger than 0.
Optionally, the compensation module comprises an enhanced PMOS tube and a plurality of depletion type PMOS tubes,
The drain electrode of the PMOS tube MP5 is connected with the drain electrode of a first depletion type PMOS tube in the compensation module, the source electrode of the first depletion type PMOS tube is connected with the drain electrode of a second enhancement type PMOS tube, and the source electrode of the second enhancement type PMOS tube is connected with the drain electrode of a third depletion type PMOS tube until the drain electrode of the second enhancement type PMOS tube is connected to an X depletion type PMOS tube in series, wherein X is a natural number larger than 0.
Optionally, the compensation module comprises a depletion type PMOS tube and a plurality of enhancement type PMOS tubes,
The drain electrode of the PMOS tube MP5 is connected with the drain electrode of the first enhancement type PMOS tube in the compensation module, the source electrode of the first enhancement type PMOS tube is connected with the drain electrode of the second depletion type PMOS tube, and the source electrode of the second depletion type PMOS tube is connected with the drain electrode of the third enhancement type PMOS tube until the drain electrode of the second depletion type PMOS tube is connected to the Y enhancement type PMOS tube in series, wherein Y is a natural number larger than 0.
Optionally, the current mirror unit includes a MOS tube MP1, a MOS tube MP2, a MOS tube MN1, a MOS tube MN2, a MOS tube MP3, and a MOS tube MP5, where the MOS tube MP1 and the MOS tube MP2 are current mirror structures, the MOS tube MN1 and the MOS tube MN2 are current mirror structures, and the MOS tube MP3 and the MOS tube MP5 are current mirror structures;
the starting unit comprises an MOS tube MP3, an MOS tube MN4, an MOS tube MN5, an MOS tube MP4, an MOS tube MN6 and an MOS tube MN7.
Optionally, a fuse is connected in parallel to the serial branch of the enhancement type MOS tube or the serial branch of the depletion type MOS tube.
Optionally, the compensation module includes one depletion NMOS and one enhancement NMOS, or two depletion NMOS and one enhancement NMOS.
In a second aspect, an embodiment of the present invention provides a control method of a bandgap reference circuit, the control method including:
acquiring a negative temperature voltage value of a grid source voltage of a depletion type MOS tube and the grid source voltage of an enhancement type MOS tube;
determining positive temperature coefficient voltage according to the difference value of the negative temperature voltage value and the gate-source voltage;
determining a positive temperature current according to the positive temperature coefficient voltage and the linear region resistance of the enhancement MOS tube;
determining a positive temperature voltage according to the positive temperature current and the linear region resistance of the enhanced MOS tube;
And adjusting the proportionality coefficient according to the positive temperature voltage and the negative temperature voltage of the depletion type MOS tube gate source voltage so that the zero temperature coefficient of the voltage is smaller than a preset value.
The embodiment of the invention has the following advantages:
The band gap reference circuit comprises a constant current power supply module and a compensation module, wherein the constant current power supply module at least comprises a starting unit and a current mirror unit, the compensation module comprises at least one enhancement type MOS tube and at least one depletion type MOS tube, the enhancement type MOS tube and the depletion type MOS tube are connected in series, the starting unit is connected with the current mirror unit, a source electrode of a PMOS tube MP5 in the current mirror unit is connected with a preset voltage, a drain electrode of the PMOS tube MP5 is connected with a drain electrode of a first enhancement type MOS tube in the compensation module, a source electrode of the first enhancement type MOS tube is connected with a drain electrode of a second depletion type MOS tube, or a drain electrode of the PMOS tube MP5 is connected with a drain electrode of the first depletion type MOS tube in the compensation module, the problems that the existing band gap reference circuit adopting the negative temperature characteristic of an emitter-base voltage of a BJT tube to construct zero temperature has large power consumption and complex circuit power consumption are solved, and the effect of reducing the area of the circuit is achieved while zero temperature of the voltage is realized.
Drawings
FIG. 1 is a schematic diagram of a conventional bandgap reference voltage source circuit of the prior art;
FIG. 2 is a schematic diagram of a bandgap reference circuit connection in accordance with an embodiment of the present invention;
FIG. 3 is a schematic circuit diagram of a series branch of depletion NMOS and enhancement NMOS transistors according to an embodiment of the present invention;
FIG. 4 is a circuit diagram of a series branch of depletion NMOS and enhancement NMOS transistors according to another embodiment of the present invention;
FIG. 5 is a circuit diagram of a depletion NMOS transistor and enhancement NMOS transistor series branch of another embodiment of the present invention;
FIG. 6 is a circuit diagram of a series branch of depletion type PMOS tubes and enhancement type PMOS tubes according to one embodiment of the present invention;
FIG. 7 is a circuit diagram of a series branch of depletion type PMOS tubes and enhancement type PMOS tubes according to yet another embodiment of the present invention.
Detailed Description
It should be noted that, without conflict, the embodiments of the present application and features of the embodiments may be combined with each other. The application will be described in detail below with reference to the drawings in connection with embodiments.
Referring to FIG. 2, a schematic diagram of a bandgap reference circuit according to an embodiment of the present invention is shown, where the bandgap reference circuit includes a constant current power module and a compensation module, the constant current power module at least includes a start-up unit and a current mirror unit, the compensation module includes at least one enhancement MOS tube and at least one depletion MOS tube, the enhancement MOS tube and the depletion MOS tube are connected in series, the start-up unit is connected with the current mirror unit, and a source electrode of a PMOS tube MP5 in the current mirror unit is connected with a preset voltage, namely VDD;
The drain electrode of the PMOS tube MP5 is connected with the drain electrode of the first enhancement type MOS tube in the compensation module, and the source electrode of the first enhancement type MOS tube is connected with the drain electrode of the second depletion type MOS tube;
or the drain electrode of the PMOS tube MP5 is connected with the drain electrode of the first depletion type MOS tube in the compensation module, and the source electrode of the first depletion type MOS tube is connected with the drain electrode of the second enhancement type MOS tube.
Specifically, the embodiment of the invention provides a band gap reference circuit, which comprises a group of constant current power supplies (constant gm current source), namely constant current power supply modules, wherein the constant current power supply modules cannot change along with voltage, each constant current power supply module comprises a starting unit and a current mirror unit, the starting units are connected with the current mirror units, each current mirror unit comprises a MOS tube MP1, a MOS tube MP2, a MOS tube MN1, a MOS tube MN2, a MOS tube MP3 and a MOS tube MP5, the MOS tubes MP1 and MP2 are of a current mirror structure, the MOS tubes MN1 and MN2 are of a current mirror structure, and the MOS tubes MP3 and MP5 are of a current mirror structure;
The starting unit comprises an MOS tube MP3, an MOS tube MN4, an MOS tube MN5, an MOS tube MP4, an MOS tube MN6 and an MOS tube MN7.
The compensation module includes at least one enhancement type MOS tube and at least one depletion type MOS tube, the enhancement type MOS tube and the depletion type MOS tube are connected in series, and the compensation module may include one enhancement type MOS tube and a plurality of depletion type MOS tubes, or may include one depletion type MOS tube and a plurality of enhancement type MOS tubes, in the embodiment of the present invention, a plurality of enhancement type MOS tubes refers to two or more MOS tubes, which may be NMOS tubes or PMOS tubes, without being limited specifically herein.
As an alternative implementation manner, the compensation module may include a depletion type MOS tube and a plurality of enhancement type MOS tubes, where the drain electrode of the PMOS tube MP5 is connected to the drain electrode of the first enhancement type MOS tube in the compensation module, the source electrode of the first enhancement type MOS tube is connected to the drain electrode of the second depletion type MOS tube, and the source electrode of the second depletion type MOS tube is connected to the drain electrode of the third depletion type MOS tube, and in this way, is connected in series to the plurality of depletion type MOS tubes;
As another alternative implementation mode, the device comprises an enhancement type MOS tube and a plurality of depletion type MOS tubes, wherein the drain electrode of the PMOS tube MP5 is connected with the drain electrode of a first depletion type MOS tube in the compensation module, the source electrode of the first depletion type MOS tube is connected with the drain electrode of a second enhancement type MOS tube, and the source electrode of the second enhancement type MOS tube is connected with the drain electrode of a third enhancement type MOS tube, and in this way, the device is connected with the enhancement type MOS tubes in series.
The transistor group formed by the enhancement type MOS tubes connected in series and the depletion type MOS tubes is added to compensate the constant current power supply module.
As shown in fig. 4, the depletion NMOS and enhancement NMOS series branch circuit of the embodiment of the present invention is formed by connecting one enhancement NMOS (M2) in series with multiple depletion NMOS (M1, M3, M4, M5, M6, M7, M8, M9, M10, M11), overlapping NMOS gate-source voltages Vgs, and adjusting the scaling factor to achieve a voltage zero temperature coefficient.
Specifically, the compensation module comprises an enhanced NMOS tube and a plurality of depletion NMOS tubes,
The drain electrode of the PMOS tube MP5 is connected with the drain electrode of a first depletion type NMOS tube in the compensation module, the source electrode of the first depletion type NMOS tube is connected with the drain electrode of a second enhancement type NMOS tube, and the source electrode of the second enhancement type NMOS tube is connected with the drain electrode of a third depletion type NMOS tube until being connected to an N depletion type NMOS tube in series, wherein N is a natural number larger than 0.
Specifically, the source of the third depletion type NMOS tube and the drain of the fourth depletion type NMOS tube are connected in series,
The source electrode of the fourth depletion type NMOS tube is connected in series with the drain electrode of the fifth depletion type NMOS tube,
The source of the fifth depletion type NMOS tube is connected in series with the drain of the sixth depletion type NMOS tube,
The source of the sixth depletion type NMOS transistor is connected in series with the drain of the seventh depletion type NMOS transistor,
The source of the seventh depletion type NMOS transistor is connected in series with the drain of the eighth depletion type NMOS transistor,
The source of the eighth depletion type NMOS transistor is connected in series with the drain of the ninth depletion type NMOS transistor,
The source of the ninth depletion type NMOS transistor is connected in series with the drain of the tenth depletion type NMOS transistor,
The source of the tenth depletion type NMOS transistor is connected in series with the drain of the eleventh depletion type NMOS transistor,
The source of the eleventh depletion type NMOS transistor is grounded.
In fig. 4, the MP5 drain of the constant current source is connected to the drain of the first NMOS transistor M1 (depletion type), the source of the first NMOS transistor M1 (depletion type) is connected in series with the drain of the second NMOS transistor M2 (enhancement type), the source of the second NMOS transistor M2 (enhancement type) is connected in series with the drain of the third NMOS transistor M3 (depletion type), the source of the third NMOS transistor M3 (depletion type) is connected in series with the drain of the fourth NMOS transistor M4 (depletion type), the source of the fourth NMOS transistor M4 (depletion type) is connected in series with the drain of the fifth NMOS transistor M5 (depletion type), the source of the fifth NMOS transistor M5 (depletion type) is connected in series with the drain of the sixth NMOS transistor M6 (depletion type), the source of the sixth NMOS transistor M6 (depletion type) is connected in series with the drain of the seventh NMOS transistor M7 (depletion type), the source of the seventh NMOS tube M7 (depletion type) is connected in series with the drain of the eighth NMOS tube M8 (depletion type), the source of the eighth NMOS tube M8 (depletion type) is connected in series with the drain of the ninth NMOS tube M9 (depletion type), the source of the ninth NMOS tube M9 (depletion type) is connected in series with the drain of the tenth NMOS tube M10 (depletion type), the source of the tenth NMOS tube M10 (depletion type) is connected in series with the drain of the eleventh NMOS tube M11 (depletion type), the source of the eleventh NMOS tube M11 (depletion type) is grounded, the current is converted into the voltage, and the superposition compensation of the positive temperature coefficient voltage generated by the enhancement NMOS tube and the grid source voltage with the negative temperature coefficient of the depletion type NMOS tube is realized, so that the zero temperature coefficient voltage after superposition is output.
As shown in fig. 5, the compensation module includes a depletion NMOS and a plurality of enhancement NMOS, the drain of the PMOS MP5 is connected to the drain of the first enhancement NMOS in the compensation module, the source of the first enhancement NMOS is connected to the drain of the second depletion NMOS, and the source of the second depletion NMOS is connected to the drain of the third enhancement NMOS until being connected in series to the mth enhancement NMOS, where M is a natural number greater than 0.
Namely, in the embodiment of the invention, a depletion type NMOS tube and an enhancement type NMOS tube series branch circuit is provided, and the depletion type NMOS tube (M2) is connected in series with a plurality of enhancement type NMOS tubes (M1, M3, M4, M5, M6, M7, M8, M9, M10 and M11) to form, the gate-source voltage Vgs of the NMOS tubes is overlapped, the proportionality coefficient is adjusted, and the zero temperature coefficient of the voltage is realized.
As shown in fig. 6, optionally, the compensation module includes an enhancement PMOS transistor and a plurality of depletion PMOS transistors,
The drain electrode of the PMOS tube MP5 is connected with the drain electrode of a first depletion type PMOS tube in the compensation module, the source electrode of the first depletion type PMOS tube is connected with the drain electrode of a second enhancement type PMOS tube, and the source electrode of the second enhancement type PMOS tube is connected with the drain electrode of a third depletion type PMOS tube until being connected to an X depletion type PMOS tube in series, wherein X is a natural number larger than 0.
Specifically, under the process of only depletion type PMOS tubes, the embodiment of the invention provides a depletion type PMOS tube and enhancement type PMOS tube series branch, which is formed by connecting one enhancement type PMOS tube (M2) in series with a plurality of depletion type PMOS tubes (M1, M3, M4, M5, M6, M7, M8, M9, M10 and M11), and the grid source voltage Vgs of the PMOS tubes is overlapped, the proportionality coefficient is adjusted, and the zero temperature coefficient of the voltage can also be realized.
As shown in fig. 7, the compensation module includes a depletion PMOS and a plurality of enhancement PMOS, the drain of the PMOS MP5 is connected to the drain of the first enhancement PMOS in the compensation module, the source of the first enhancement PMOS is connected to the drain of the second depletion PMOS, and the source of the second depletion PMOS is connected to the drain of the third enhancement PMOS until being connected in series to the Y enhancement PMOS, where Y is a natural number greater than 0.
Specifically, under the process of only depletion type PMOS tubes, the depletion type PMOS tube and enhancement type PMOS tube series branch provided by the embodiment of the invention is formed by connecting one depletion type PMOS tube (M2) in series with a plurality of enhancement type PMOS tubes (M1, M3, M4, M5, M6, M7, M8, M9, M10 and M11), and the grid source voltage Vgs of the PMOS tubes is overlapped, so that the scaling factor is adjusted, and the zero temperature coefficient of the voltage can be realized.
Optionally, a fuse is connected in parallel to the serial branch of the enhancement MOS tube or the serial branch of the depletion MOS tube.
The embodiment of the invention also provides a simple fuse trimming mode, and the fuse can be easily blown by laser or a power-on mode by utilizing the dimension of the binary NMOS tube only to be designed on the serial branch of the depletion NMOS tube and the enhancement NMOS tube, so that the trimming of the reference voltage can be easily completed.
Optionally, the compensation module includes one depletion type NMOS transistor and one enhancement type NMOS transistor, or two depletion type NMOS transistors and one enhancement type NMOS transistor.
As shown in FIG. 3, the bandgap reference circuit of the embodiment of the invention has low power consumption and simple circuit, can be completed by only using one or two depletion type NMOS tubes and one enhancement type NMOS tube serial branch, and is widely applied to devices such as a lithium battery protection chip, an LED driving chip DC-DC converter, a digital-to-analog converter, an analog-to-digital converter and the like, and has strong practicability.
The embodiment of the invention also provides a control method based on the band gap reference circuit, which comprises the following steps:
acquiring a negative temperature voltage value of a grid source voltage of a depletion type MOS tube and the grid source voltage of an enhancement type MOS tube;
determining a positive temperature coefficient voltage according to the difference value of the negative temperature voltage value and the gate-source voltage;
Determining a positive temperature current according to the positive temperature coefficient voltage and the linear region resistance of the enhancement type MOS tube;
determining a positive temperature voltage according to the positive temperature current and the linear region resistance of the enhanced MOS tube;
And adjusting the proportionality coefficient according to the positive temperature voltage and the negative temperature voltage of the depletion type MOS tube gate source voltage so that the zero temperature coefficient of the voltage is smaller than a preset value.
Specifically, as shown in the circuit diagram of fig. 2, MP3 will also enter the cut-off region when the current on the branches of MN1, MN2, MP1, MP2, MP5 is low or 0, so that the gate voltage of MN6 will be reduced to 0V to cut off MN6, and the gate voltage of MN7 will be raised to enter the threshold region, so that the gate voltages of MP1 and MP2 can be pulled down to enter the threshold region. Once the gate voltages of MP1 and MP2 enter the threshold region, MP3 also enters the threshold region to prevent the start-up circuit from restarting, and the current-voltage characteristics of the constant current source circuit can be expressed as:
Wherein I 0 represents reverse saturation current, ζ represents non-ideal factor, greater than 1,
V GS denotes a MOS transistor gate-source voltage, VT denotes a thermal voltage, vt=kt/q, K is boltzmann constant, and q is an electron charge amount.
Two pairs of current mirror structures are defined by the keschiff voltage laws MN1, MN2, which can be listed as follows:
VGS1＝VGS2+ID2×R1.........(2)
Substituting the formula (2) from the uppermost formula (1) yields the following:
wherein I D1 is the base current through MN 1;
I D2 the base current through MN 2;
V T1 denotes the thermal voltage of MN 1;
v T2 a voltage representing heat;
Mu n, electron drift rate;
C OX, capacitance value of oxide layer;
boltzmann constant;
The ratio of the length to the width of the MOS tube,
Is arranged in the formula (3) to obtain
The (4) is square at two sides, the current irrelevant to VDD is obtained after the term shifting,
The temperature is still related, and the zero temperature coefficient of the voltage can be adjusted by adding the depletion type MOS tube and the enhancement type MOS tube in series branch circuit proportion. ,
The negative temperature characteristic of the grid source voltage of the depletion type MOS tube connected with the drain electrode and the grid electrode is utilized to generate positive temperature coefficient voltage by the difference value of the grid source voltage Vgs of the enhancement type NMOS tube, the positive temperature coefficient voltage is divided by the resistance of the NMOS tube in the linear region to obtain positive temperature current, the positive temperature current is multiplied by the resistance of the NMOS tube in the linear region to obtain positive temperature voltage, the negative temperature voltage Vgs of the grid source voltage of the depletion type NMOS tube is overlapped, the proportionality coefficient is adjusted, and the zero temperature coefficient of the voltage is realized.
The band gap reference circuit comprises a constant current power supply module and a compensation module, wherein the constant current power supply module at least comprises a starting unit and a current mirror unit, the compensation module comprises at least one enhancement type MOS tube and at least one depletion type MOS tube, the enhancement type MOS tube and the depletion type MOS tube are connected in series, the starting unit is connected with the current mirror unit, a source electrode of a PMOS tube MP5 in the current mirror unit is connected with a preset voltage, a drain electrode of the PMOS tube MP5 is connected with a drain electrode of a first enhancement type MOS tube in the compensation module, a source electrode of the first enhancement type MOS tube is connected with a drain electrode of a second depletion type MOS tube, or a drain electrode of the PMOS tube MP5 is connected with a drain electrode of the first depletion type MOS tube in the compensation module, the problems that the existing band gap reference circuit adopting the negative temperature characteristic of an emitter-base voltage of a BJT tube to construct zero temperature has large power consumption and complex circuit area are solved, and the effect of reducing the zero temperature of the voltage is achieved.
It should be noted that the foregoing detailed description is exemplary and is intended to provide further explanation of the application. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs.
It is noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of exemplary embodiments according to the present application. As used herein, the singular is intended to include the plural unless the context clearly indicates otherwise. Furthermore, it will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, steps, operations, devices, components, and/or groups thereof.
It should be noted that the terms "first," "second," and the like in the description and the claims of the present application and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the application described herein are capable of operation in sequences other than those illustrated or otherwise described herein.
Furthermore, the terms "comprise" and "have," as well as any variations thereof, are intended to cover a non-exclusive inclusion. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those elements but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
Spatially relative terms, such as "above," "upper" and "upper surface," "above" and the like, may be used herein for ease of description to describe one device or feature's spatial relationship to another device or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "above" or "over" other devices or structures would then be oriented "below" or "beneath" the other devices or structures. Thus, the process is carried out, the exemplary term "above" may be included. Upper and lower. Two orientations below. The device may also be positioned in other different ways, such as rotated 90 degrees or at other orientations, and the spatially relative descriptors used herein interpreted accordingly.
In the above detailed description, reference is made to the accompanying drawings, which form a part hereof. In the drawings, like numerals typically identify like components unless context indicates otherwise. The illustrated embodiments described in the detailed description, drawings, and claims are not meant to be limiting. Other embodiments may be utilized, and other changes may be made, without departing from the spirit or scope of the subject matter presented herein.
The above description is only of the preferred embodiments of the present invention and is not intended to limit the present invention, but various modifications and variations can be made to the present invention by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (9)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111462894.2A CN113985955B (en) | 2021-12-02 | 2021-12-02 | Bandgap reference circuit and control method |
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| CN104181971A (en) * | 2013-05-24 | 2014-12-03 | 比亚迪股份有限公司 | Reference voltage source |
| CN109901656A (en) * | 2019-04-10 | 2019-06-18 | 电子科技大学 | A low-power all-MOS transistor bandgap reference circuit and a converter based thereon |
| CN216486176U (en) * | 2021-12-02 | 2022-05-10 | 铠强科技(平潭)有限公司 | Band gap reference circuit |
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| US7116158B2 (en) * | 2004-10-05 | 2006-10-03 | Texas Instruments Incorporated | Bandgap reference circuit for ultra-low current applications |
| EP1846808A2 (en) * | 2004-12-07 | 2007-10-24 | Koninklijke Philips Electronics N.V. | Reference voltage generator providing a temperature-compensated output voltage |
| CN102279616B (en) * | 2011-03-29 | 2012-07-18 | 山东华芯半导体有限公司 | High-precision current reference source with pure MOS structure and method of manufacturing high-precision current reference source |
| CN102495661B (en) * | 2011-12-26 | 2014-02-12 | 电子科技大学 | A Bandgap Reference Circuit Based on Two Threshold Voltage MOS Devices |
| CN107066003A (en) * | 2016-12-30 | 2017-08-18 | 西南技术物理研究所 | Low-power-consumptioreference reference voltage source |
| US10749507B1 (en) * | 2019-06-19 | 2020-08-18 | Infineon Technologies Austria Ag | Current trimming system, method, and apparatus |
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| CN104181971A (en) * | 2013-05-24 | 2014-12-03 | 比亚迪股份有限公司 | Reference voltage source |
| CN109901656A (en) * | 2019-04-10 | 2019-06-18 | 电子科技大学 | A low-power all-MOS transistor bandgap reference circuit and a converter based thereon |
| CN216486176U (en) * | 2021-12-02 | 2022-05-10 | 铠强科技(平潭)有限公司 | Band gap reference circuit |
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