CN113675162A - System-in-package device and method - Google Patents
System-in-package device and method Download PDFInfo
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- CN113675162A CN113675162A CN202110738487.3A CN202110738487A CN113675162A CN 113675162 A CN113675162 A CN 113675162A CN 202110738487 A CN202110738487 A CN 202110738487A CN 113675162 A CN113675162 A CN 113675162A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/81986—Specific sequence of steps, e.g. repetition of manufacturing steps, time sequence
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Abstract
本申请公开了一种系统级封装器件及方法，包括：第一基板，包括相背设置的第一承载面和第一非承载面；至少一个第一功能器件，固定于所述第一承载面上，且与所述第一基板电连接；第二基板，与所述第一基板电连接，包括相背设置的第二承载面和第二非承载面，且所述第二非承载面与所述第一承载面相对并固定设置；其中，所述第二基板设置有贯穿所述第二承载面和所述第二非承载面的凹槽；所述至少一个第一功能器件从所述凹槽中露出；第二功能器件，跨接设置于所述至少一个第一功能器件的上方，且与所述至少一个第一功能器件周围的所述第二承载面固定设置，并与所述第二基板电连接。通过上述方式，能够有效提升系统级封装器件的良率。
The present application discloses a system-in-package device and method, comprising: a first substrate including a first bearing surface and a first non-bearing surface arranged opposite to each other; at least one first functional device fixed on the first bearing surface and electrically connected to the first substrate; the second substrate, electrically connected to the first substrate, includes a second bearing surface and a second non-bearing surface disposed opposite to each other, and the second non-bearing surface and The first bearing surface is opposite and fixedly arranged; wherein, the second substrate is provided with a groove penetrating the second bearing surface and the second non-bearing surface; the at least one first functional device is exposed in the groove; a second functional device is disposed across the at least one first functional device, and is fixedly disposed with the second bearing surface around the at least one first functional device, and is connected with the at least one first functional device. The second substrate is electrically connected. In the above manner, the yield of the system-in-package device can be effectively improved.
Description
Technical Field
The present application relates to the field of semiconductor packaging technologies, and in particular, to a system-in-package device and method.
Background
As moore's law develops to approach the limit, the integration of integrated circuits is higher and higher, and electronic products are developing toward miniaturization, intellectualization and high performance. The system-in-package technology is a mainstream technology capable of realizing system miniaturization at present, different chips can be packaged side by side or in an overlapping mode, and a plurality of active electronic devices or optional passive devices with different functions are assembled together, so that a certain specific function is realized.
The structure design of the system-in-package device in the prior art is often that the system-in-package device is stacked on a single substrate in the transverse or longitudinal direction. In order to further reduce the package size, an embedded package technology is commonly used, i.e., a capacitance-resistance device or a chip is directly embedded in a package substrate.
However, in the embedded package technique, a metal layer is usually covered on each of two side surfaces of the chip, and then a metal groove is formed on the metal layer by electroplating, so that the metal layer is easily separated from the chip by external impact during the production process, thereby causing abnormal product quality. The embedded packaging technology has extremely high requirements on process precision, and currently, the number of sustainable substrate manufacturers is small, and most of the technology can only embed small devices such as capacitance resistors and the like.
Disclosure of Invention
The technical problem mainly solved by the application is to provide a system-in-package device and a method, which can reasonably utilize the internal space of a package body and effectively improve the yield of the system-in-package device.
In order to solve the technical problem, the application adopts a technical scheme that: there is provided a system in package device comprising: the first substrate comprises a first bearing surface and a first non-bearing surface which are arranged oppositely; at least one first functional device fixed on the first bearing surface and electrically connected with the first substrate; the second substrate is electrically connected with the first substrate and comprises a second bearing surface and a second non-bearing surface which are arranged oppositely, and the second non-bearing surface is opposite to the first bearing surface and is fixedly arranged; the second substrate is provided with a groove which penetrates through the second bearing surface and the second non-bearing surface; the at least one first functional device is exposed from the groove; and the second functional device is arranged above the at least one first functional device in a bridging manner, is fixedly arranged with the second bearing surface around the at least one first functional device and is electrically connected with the second substrate.
A plurality of first bonding pads are arranged in the area, corresponding to the first functional device, of the first bearing surface, a plurality of second bonding pads on the functional surface of the first functional device face the first bonding pads, and the second bonding pads are in one-to-one correspondence with and electrically connected with the first bonding pads; and/or the first bearing surface is provided with a plurality of third bonding pads corresponding to the second non-bearing surface, the second non-bearing surface is provided with a plurality of fourth bonding pads, and the third bonding pads are in one-to-one correspondence with the fourth bonding pads and are electrically connected with the fourth bonding pads.
The plurality of second bonding pads are electrically connected with the plurality of first bonding pads through solder balls, and the plurality of third bonding pads are electrically connected with the plurality of fourth bonding pads through solder balls; and the first bearing surface is also provided with an annular dam, and the annular dam is exposed out of the groove and surrounds the periphery of the occupied area of all the first functional devices.
Wherein, in a direction from the first carrying surface to the first non-carrying surface, a maximum height value of all the first functional devices is less than or equal to a height value of the second substrate.
The second bearing surface is provided with a plurality of fifth bonding pads corresponding to the area of the second functional device, the second functional device is provided with a plurality of sixth bonding pads corresponding to the fifth bonding pads, and the fifth bonding pads are in one-to-one correspondence with the sixth bonding pads and are electrically connected with the sixth bonding pads.
Wherein the system-in-package device further comprises: underfill, which fills the area between the second functional device and the first substrate corresponding to the groove; and/or, a plastic package layer covering the top surface and the side surface of the first substrate, the second substrate and the second functional device.
Wherein the at least one first functional device comprises at least one of a chip and a passive component; the second functional device comprises a chip.
In order to solve the above technical problem, another technical solution adopted by the present application is: provided is a system-in-package method, including: providing a first substrate, wherein the first substrate comprises a first bearing surface and a first non-bearing surface which are arranged in a back-to-back manner; at least one first functional device is fixedly arranged on the first bearing surface and is electrically connected with the first substrate; electrically connecting a second substrate with the first substrate, wherein the second substrate comprises a second bearing surface and a second non-bearing surface which are arranged oppositely, and the second non-bearing surface is opposite to the first bearing surface and is fixedly arranged; the second substrate is provided with a groove penetrating through the second bearing surface and the second non-bearing surface, and the at least one first functional device is exposed out of the groove; and a second functional device is arranged above the at least one first functional device in a bridging manner, is fixedly arranged with the second bearing surface around the at least one first functional device and is electrically connected with the second substrate.
Wherein, the step of fixedly arranging at least one first functional device on the first bearing surface, and electrically connecting the at least one first functional device and the first substrate comprises: a plurality of first bonding pads arranged on the first bearing surface corresponding to the area of the first functional device correspond to a plurality of second bonding pads on the functional surface of the first functional device one by one; electrically connecting the plurality of second pads and the plurality of first pads through solder balls; and/or a plurality of third bonding pads arranged at the position of the first bearing surface corresponding to the second non-bearing surface are in one-to-one correspondence with a plurality of fourth bonding pads on the second non-bearing surface; and electrically connecting the plurality of third bonding pads and the plurality of fourth bonding pads through solder balls.
Wherein, before the step of electrically connecting the second substrate and the first substrate, the method further comprises: and an annular dam is formed around the periphery of the area occupied by all the first functional devices, is fixedly arranged on the first bearing surface and is exposed out of the groove.
Different from the prior art, the beneficial effects of the application are that: according to the system and the packaging device, the first substrate and the second substrate are stacked, so that a gap is reserved between the two substrates when the two substrates are connected, and the gap can effectively improve the heat dissipation effect inside the packaging device; on the other hand, the groove space in the second substrate is reasonably utilized through the design mode, at least one first functional device is accommodated, and meanwhile, functional devices of various types and sizes are compatible through the design of the adjusting substrate, so that the compatibility and the flexibility of the packaging device are improved; in addition, the design method can effectively solve the problem of abnormal product quality caused by the embedded packaging technology in the prior art, avoids the separation problem between the metal layer and the chip, simplifies the process and effectively improves the yield of the system-in-package chip.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts. Wherein:
FIG. 1 is a schematic flow chart diagram illustrating an embodiment of a system-in-package method according to the present application;
FIG. 2 is a schematic structural diagram of an embodiment corresponding to steps S101-S106 in FIG. 1;
FIG. 3 is a schematic flow chart illustrating an embodiment corresponding to step S102 in FIG. 1;
FIG. 4 is a top view of one embodiment of the second substrate of FIG. 2;
FIG. 5 is a schematic flow chart illustrating an embodiment corresponding to step S103 in FIG. 1;
FIG. 6 is a schematic structural diagram of an embodiment before step S103 in FIG. 2;
fig. 7 is a schematic structural diagram of an embodiment of the system-in-package device according to the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Referring to fig. 1 and fig. 2, fig. 1 is a schematic flow chart diagram of an embodiment of a system-in-package method of the present application, and fig. 2 is a schematic structural diagram of an embodiment corresponding to steps S101 to S106 in fig. 1, where the packaging method provided by the present application includes:
s101: a first substrate 10 is provided, wherein the first substrate 10 includes a first carrying surface 101 and a first non-carrying surface 102 disposed opposite to each other.
Specifically, referring to fig. 2(a), the first substrate 10 may be formed by stacking multiple layers of boards, wherein a plurality of first pads 103 are disposed on the carrying surface 101 for subsequent electrical connection with a chip to be packaged, and a plurality of solder balls 104 are disposed on a non-carrying surface 102 side of the first substrate, and the solder balls 104 may be in a Ball Grid Array (BGA) package form or a Land Grid Array (LGA) package form for subsequent electrical connection with other external devices to implement the function of a semiconductor package device. In one embodiment, to ensure the longitudinal dimension of the whole packaged device, the thickness dimension of the first substrate 10 needs to be designed in advance before the preparation; in yet another embodiment, a conventional substrate may be thinned in advance to form the first substrate 10 having a smaller thickness.
S102: at least one first functional device 20 is fixedly disposed on the first carrying surface 101, and the at least one first functional device 20 is electrically connected to the first substrate 10.
Specifically, referring to fig. 2(b), the first functional device 20 includes at least one of a chip 201 and a passive element 202, and the passive element 202 may be a capacitor, a resistor, or the like.
Referring to fig. 2(b) and fig. 3 together, fig. 3 is a schematic flow chart of an embodiment corresponding to step S102 in fig. 1, where the step S102 includes:
s201: the first pads 103 of the first carrying surface 101, which are arranged corresponding to the area of the first functional device 20, are in one-to-one correspondence with the second pads 204 of the functional surface 203 of the first functional device 20.
Specifically, referring to fig. 2(b), in the present embodiment, the plurality of first pads 103 are disposed at the center of the first carrying surface 101, the functional surface 203 of the first functional device 20 faces the first carrying surface 101 of the first substrate 10, and the plurality of first pads 103 correspond to the plurality of second pads 204 on the first functional device 20 one by one, so as to facilitate the implementation of the subsequent electrical connection step.
S202: the plurality of second pads 204 and the plurality of first pads 103 are electrically connected.
Specifically, the first pads 103 and the second pads 204 may be electrically connected by solder balls, but may also be electrically connected by a conductive material such as a conductive post or solder paste, and the present invention is not limited thereto.
With the above embodiment, the mounting of the first functional device 20 can be completed, and the electrical connection between the first functional device 20 and the first substrate 10 can be effectively achieved.
S103: electrically connecting the second substrate 30 with the first substrate 10, wherein the second substrate 30 includes a second carrying surface 301 and a second non-carrying surface 302 which are opposite to each other, and the second non-carrying surface 302 is opposite to and fixedly disposed on the first carrying surface 101; wherein, the second substrate 30 is provided with a groove 303 penetrating through the second carrying surface 301 and the second non-carrying surface 302, and at least one first functional device 20 is exposed from the groove 303.
Specifically, referring to fig. 2(c) and fig. 4, fig. 4 is a top view of an embodiment of the second substrate in fig. 2 (c). The second substrate 30 may be formed of a multi-layer board lamination arrangement in which the grooves 303 may be formed by controlling the shape of each layer board, i.e., the grooves 303 may be formed simultaneously when the multi-layer boards are laminated. Of course, after the multilayer board is stacked, a partial region may be removed by etching to form the groove 303. Preferably, the groove 303 is disposed at a central position of the second substrate 30, so that the first functional device 20 disposed on the first substrate 10 is exposed from the groove 303.
In this embodiment, please refer to fig. 2(c) and fig. 5 together, and fig. 5 is a flowchart illustrating step S103 in fig. 1 corresponding to an embodiment. The step S103 includes:
s301: the third pads 105 arranged at the positions of the first carrying surface 101 corresponding to the second non-carrying surface 302 are in one-to-one correspondence with the fourth pads 304 on the second non-carrying surface 302.
Specifically, referring to fig. 2(c), in the present embodiment, the third pads 105 are disposed at other positions of the first carrying surface 101 except the center position, the second non-carrying surface 302 of the second substrate 30 faces the first carrying surface 101 of the first substrate 10, and the positions of the third pads 105 and the fourth pads 304 on the second substrate 30 are in one-to-one correspondence, so as to facilitate the implementation of the subsequent electrical connection step.
S302: the plurality of third pads 105 and the plurality of fourth pads 304 are electrically connected.
Specifically, referring to fig. 2(c), the third pad 105 and the fourth pad 304 may be electrically connected by using a solder ball, or may be electrically connected by using a conductive post or a solder paste, which is not limited in this respect.
With the above embodiment, the mounting of the second substrate 30 can be completed, and the electrical connection between the second substrate 30 and the first substrate 10 can be effectively achieved.
In another embodiment, referring to fig. 6, fig. 6 is a schematic structural diagram of an embodiment before step S103 in fig. 2, where fig. 6(a) is a front view corresponding to the annular dam, and fig. 6(b) is a top view corresponding to the annular dam. Before the step S103, the method may further include: an annular dam 40 is formed around the periphery of the area occupied by all the first functional devices 20, and the annular dam 40 is fixedly arranged on the first bearing surface 101. Referring to fig. 6(b), the annular dam 40 is rectangular in the top view projection direction, but in other embodiments, the annular dam 40 may also be circular or in other irregular patterns in the top view projection direction, which is not particularly limited as long as the function of enclosure is achieved. The arrangement of the annular dam 40 can effectively control the overflow of the solder paste so as to avoid influencing subsequent mounting and reduce the probability of short circuit of a circuit structure.
S104: the second functional device 50 is disposed over the at least one first functional device 20, and is fixed to the second carrying surface 301 around the at least one first functional device 20 and electrically connected to the second substrate 30.
Specifically, referring to fig. 2(d), the second functional device 50 has a larger size, can bridge the second carrying surface 301 of the second substrate 30, and is electrically connected to the second substrate 30 through a solder ball, but may also be implemented by a conductive post or a solder paste, which has a conductive property, and is not limited in this respect.
S105: the position between the second functional device 50 and the first substrate 10 corresponding to the groove 303 is filled with the underfill 60.
Specifically, referring to fig. 2(e), the underfill 60 is added to avoid the problem of poor filling of the molding compound, thereby improving the product reliability of the packaged device.
S106: and forming a plastic packaging layer 70 on the side of the second functional device 50 far away from the second substrate 30, covering the top surfaces and the side surfaces of the first substrate 10, the second substrate 30 and the second functional device 50.
Specifically, referring to fig. 2(f), the material of the molding compound layer 70 may be epoxy resin, and the molding compound layer 70 protects the first substrate 10, the second substrate 30 and the second functional device 50 which are encapsulated inside.
Through the above embodiment, due to the stacked arrangement of the double substrates of the first substrate 10 and the second substrate 30, on one hand, a gap is left between the double substrates during connection, and the gap can effectively improve the heat dissipation effect inside the packaged device; on the other hand, the space of the groove 303 in the second substrate 30 is reasonably utilized through the design mode to accommodate at least one first functional device 20, and meanwhile, the design of the substrate is adjusted to be compatible with functional devices with various sizes, so that the compatibility and flexibility of the packaging device are improved; in addition, the design method can effectively solve the problem of abnormal product quality caused by the embedded packaging technology in the prior art, avoids the separation problem between the metal layer and the chip, simplifies the process and effectively improves the yield of the system-in-package chip.
The system-in-package device formed by the above system-in-package method is further described in the following structure. Referring to fig. 7, fig. 7 is a schematic structural diagram of an embodiment of a system-in-package device according to the present application. The system-in-package device 100 provided by the present application includes:
the first substrate 10 includes a first carrying surface 101 and a first non-carrying surface 102 disposed opposite to each other. In this embodiment, the first substrate 10 may be formed by stacking multiple layers of boards, a plurality of first pads 103 are disposed on the carrying surface 101 for electrically connecting with a chip to be packaged, and a plurality of solder balls 104 are disposed on a side of the non-carrying surface 102, where the solder balls 104 may be in a Ball Grid Array (BGA) package form or a Land Grid Array (LGA) package form, and are used for electrically connecting with other external devices to achieve a function of packaging the device. In one embodiment, to ensure the vertical dimension of the system-in-package device 100, the thickness dimension of the first substrate 10 needs to be designed in advance before being fabricated; in yet another embodiment, a conventional substrate may be thinned in advance to form the first substrate 10 having a smaller thickness.
At least one first functional device 20 is fixed on the first carrying surface 101 and electrically connected to the first substrate 10. In an implementation scenario, the at least one first functional device 20 comprises at least one of a chip 201 and a passive component 202. In this embodiment, the chip 201 may be disposed at a central position on the first supporting surface 101; the passive element 202, which may include a capacitor, a resistor, etc., is disposed at the periphery of the chip 201.
In this embodiment, with reference to fig. 7, a plurality of first pads 103 are disposed on the first carrying surface 101 corresponding to the area of the first functional device 20, a plurality of second pads 204 on the functional surface 203 of the first functional device 20 face the plurality of first pads 103, and the plurality of second pads 204 are in one-to-one correspondence with and electrically connected to the plurality of first pads 103. In one embodiment, the plurality of second pads 204 and the plurality of first pads 103 are electrically connected by solder balls, but in other embodiments, the electrical connection may be achieved by a material having conductive properties such as conductive posts or solder paste, and the present invention is not limited to this. With the above embodiment, the mounting of the first functional device 20 can be completed, and the electrical connection between the first functional device 20 and the first substrate 10 can be effectively achieved.
The second substrate 30, electrically connected to the first substrate 10, includes a second carrying surface 301 and a second non-carrying surface 302 disposed opposite to each other, and the second non-carrying surface 302 is opposite to and fixed to the first carrying surface 101; wherein, the second substrate 30 is provided with a groove 303 penetrating through the second carrying surface 301 and the second non-carrying surface 302; at least one first functional device 20 is exposed from the recess 303. In the present embodiment, the second substrate 30 may be formed of a multilayer board lamination arrangement, wherein the groove 303 may be formed by controlling the shape of each board, i.e., the groove 303 may be formed simultaneously when the multilayer boards are arranged in the lamination arrangement. Of course, in other embodiments, after the multi-layer board is stacked, a partial region may be removed by etching to form the groove 303. Preferably, the groove 303 is disposed at a central position of the second substrate 30, so that the first functional device 20 disposed at the central position of the first substrate 10 is exposed from the groove 303. In another embodiment, the groove 303 may be square, rectangular, circular, or other shapes in the projection direction of the top view, and the area size thereof may be designed according to the first functional device 20 to be accommodated, and is not limited herein.
In the present embodiment, in the direction from the first carrying surface 101 to the first non-carrying surface 102, the maximum height value of all the first functional devices 20 is less than or equal to the height value of the second substrate 30. According to the embodiment, the probability of short circuit of the circuit structure can be effectively reduced.
In another embodiment, a plurality of third pads 105 are disposed on the first carrying surface 101 at positions corresponding to the second non-carrying surface 302, a plurality of fourth pads 304 are disposed on the second non-carrying surface 302, and the plurality of third pads 105 and the plurality of fourth pads 304 are in one-to-one correspondence and electrically connected. In one embodiment, the plurality of third pads 105 and the plurality of fourth pads 304 are electrically connected by solder balls, but in other embodiments, the third pads and the fourth pads may be formed by a material having conductive properties, such as conductive columns or solder paste, and the present invention is not limited thereto.
The second functional device 50 is disposed over the at least one first functional device 20 in a bridging manner, is fixed to the second carrying surface 301 around the at least one first functional device 20, and is electrically connected to the second substrate 30. In the present embodiment, the second functional device 50 includes a chip. The second functional device 50 is large in size, and can be electrically connected to the second substrate 30 by a solder ball, but may also be implemented by a material having conductive properties such as a conductive post or solder paste, and is not particularly limited herein.
In this embodiment, a plurality of fifth pads (not shown) are disposed on the second carrying surface 301 in a region corresponding to the second functional device 50, a plurality of sixth pads (not shown) are disposed on the second functional device 50 in a position corresponding to the plurality of fifth pads, and the plurality of fifth pads and the plurality of sixth pads are in one-to-one correspondence and electrically connected.
With continued reference to fig. 7, the system-in-package device 100 provided by the present application further includes:
and the annular dam 40 is exposed out of the groove 303, and is arranged around the periphery of the area occupied by all the first functional devices 20. The annular dam 40 is rectangular in the top view projection direction, but in other embodiments, the top view projection direction of the annular dam 40 may also be circular or other irregular figures, which is not particularly limited as long as the function of enclosure is achieved. The arrangement of the annular dam 40 can effectively control the overflow of the solder paste so as to avoid influencing subsequent mounting and reduce the probability of short circuit of a circuit structure.
And the underfill 60 is used for filling the area between the second functional device 50 and the first substrate, which corresponds to the groove 303. The addition of the underfill 60 can avoid the problem of poor filling of the plastic package material, and improve the product reliability of the packaged device.
And a molding layer 70 covering the top and side surfaces of the first substrate 10, the second substrate 30, and the second functional device 50. Specifically, the molding layer 70 may be made of epoxy resin or the like, and can protect the first substrate 10, the second substrate 30 and the second functional device 50 which are sealed inside.
In summary, different from the situation of the prior art, the present application provides a system-in-package device and a method thereof, in which a first substrate and a second substrate are stacked, so that a gap is left between the two substrates when the two substrates are connected, and the gap can effectively improve the heat dissipation effect inside the package device; on the other hand, the groove space in the second substrate is reasonably utilized through the design mode, at least one first functional device is accommodated, and meanwhile, functional devices of various types and sizes are compatible through the design of the adjusting substrate, so that the compatibility and the flexibility of the packaging device are improved; in addition, the design method can effectively solve the problem of abnormal product quality caused by the embedded packaging technology in the prior art, avoids the separation problem between the metal layer and the chip, simplifies the process and effectively improves the yield of the system-in-package chip.
The above description is only for the purpose of illustrating embodiments of the present application and is not intended to limit the scope of the present application, and all modifications of equivalent structures and equivalent processes, which are made by the contents of the specification and the drawings of the present application or are directly or indirectly applied to other related technical fields, are also included in the scope of the present application.
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| CN111341673A (en) * | 2020-02-26 | 2020-06-26 | 通富微电子股份有限公司 | 2.5D packaging device |
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2021
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|---|---|---|---|---|
| US20050067688A1 (en) * | 2003-09-26 | 2005-03-31 | Tessera, Inc. | Structure and method of making capped chips including vertical interconnects having stud bumps engaged to surfaces of said caps |
| CN101656246A (en) * | 2008-08-19 | 2010-02-24 | 南茂科技股份有限公司 | Chip stacking packaging structure of substrate with opening and packaging method thereof |
| CN102738094A (en) * | 2012-05-25 | 2012-10-17 | 日月光半导体制造股份有限公司 | Semiconductor packaging structure for stacking and manufacturing method thereof |
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Application publication date: 20211119 |