CN113517863B - Low-noise amplifier circuit and RF front-end module - Google Patents
Low-noise amplifier circuit and RF front-end moduleInfo
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- CN113517863B CN113517863B CN202110352291.0A CN202110352291A CN113517863B CN 113517863 B CN113517863 B CN 113517863B CN 202110352291 A CN202110352291 A CN 202110352291A CN 113517863 B CN113517863 B CN 113517863B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/26—Modifications of amplifiers to reduce influence of noise generated by amplifying elements
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/56—Modifications of input or output impedances, not otherwise provided for
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/189—High-frequency amplifiers, e.g. radio frequency amplifiers
- H03F3/19—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
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Abstract
The invention discloses a low-noise amplifying circuit and a radio frequency front end module, wherein the signal input end, the signal output end, a first-stage amplifying circuit, a second-stage amplifying circuit, a first-stage output matching network and a second-stage output matching network of the low-noise amplifying circuit are serially connected between the signal input end and the signal output end, one end of the first-stage output matching network is connected with the output end of the first-stage amplifying circuit, the other end of the first-stage output matching network is connected with a first power supply end, one end of the second-stage output matching network is connected with the output end of the second-stage amplifying circuit, and the other end of the second-stage output matching network is connected with a second power supply end, and the output impedance of the low-noise amplifying circuit is related to the second-stage output matching network. According to the technical scheme, the output impedance of the low-noise amplifying circuit can be quickly subjected to impedance matching, and meanwhile, the gain of the low-noise amplifying circuit can be ensured.
Description
Technical Field
The present invention relates to the field of radio frequency integrated circuits, and in particular, to a low noise amplifying circuit and a radio frequency front end module.
Background
A receiver for transmitting or receiving radio frequency signals is typically included in a radio frequency integrated circuit. The receiver includes a low noise amplifier for amplifying the radio frequency signal. The low noise amplifier is used as the first stage of the receiver and is required to amplify the radio frequency signal transmitted or received by the radio frequency integrated circuit.
But is not limited to. In the current low-noise amplifying circuit, in the amplifying process of the radio frequency signal, the condition of matching the output impedance of the low-noise amplifying circuit can not be met while enough gain is provided.
Disclosure of Invention
The embodiment of the invention provides a low-noise amplifying circuit and a radio frequency front-end module, which are used for solving the problem that the existing low-noise amplifying circuit cannot meet the output impedance matching and gain of the low-noise amplifying circuit at the same time.
A low noise amplifying circuit comprises a signal input end, a signal output end, a first-stage amplifying circuit, a second-stage amplifying circuit, a first-stage output matching network and a second-stage output matching network;
the first-stage amplifying circuit and the second-stage amplifying circuit are connected in series between the signal input end and the signal output end;
The first stage output matching network connected between the output end of the second stage amplifying circuit and the first power supply end is configured to be associated with an imaginary part of the output impedance of the low noise amplifying circuit;
The second stage output matching network is connected between the output end of the second stage amplifying circuit and a second power supply end, is a resistor network and is configured to be associated with the real part of the output impedance of the low noise amplifying circuit.
Further, a gain of the low noise amplification circuit is associated with the second stage output matching network.
Further, the resistor network is an output matching resistor, wherein the output impedance of the low-noise amplifying circuit is in direct proportion to the resistance value of the output matching resistor.
Further, the resistor network is an adjustable resistor configured to adjust a real part of an output impedance of the low noise amplification circuit.
Further, the resistor network includes a plurality of impedance adjusting branches, each of which includes a matching switch and a matching resistor connected in series.
Further, the first stage output matching network includes a first capacitor and a first inductor connected in parallel.
Further, the first-stage amplifying circuit comprises a first blocking capacitor, a first amplifying transistor, a second amplifying transistor and a second blocking capacitor;
The first end of the first blocking capacitor is connected with the signal input end, and the second end of the first blocking capacitor is connected with the first end of the first amplifying transistor;
The second end of the first amplifying transistor is connected with the third end of the second amplifying transistor, and the third end of the first amplifying transistor is connected with the grounding end;
The first end of the second amplifying transistor is connected with the grounding end through the second blocking capacitor;
the second end of the second amplifying transistor is connected with the output end of the first-stage amplifying circuit and the input end of the second-stage amplifying circuit.
Further, the second-stage amplifying circuit comprises a third blocking capacitor, a fourth blocking capacitor, a third amplifying transistor and a fourth amplifying transistor;
The first end of the third blocking capacitor is used as the input end of the second-stage amplifying circuit to be connected with the output end of the first-stage amplifying circuit, and the second end of the third blocking capacitor is connected with the first end of the third amplifying transistor;
the second end of the third amplifying transistor is connected with the third end of the fourth amplifying transistor, and the third end of the third amplifying transistor is connected with the grounding end;
the first end of the fourth amplifying transistor is connected with the grounding end through the fourth blocking capacitor, and the second end of the fourth amplifying transistor is used as the output end of the second-stage amplifying circuit to be connected with the second-stage output matching network.
Further, the low noise amplifying circuit further comprises a first gain adjusting circuit and a second gain adjusting circuit;
the first gain adjusting circuit is connected with the first-stage amplifying circuit at one end and the ground terminal at the other end, and is configured to perform gain adjustment on the first-stage amplifying circuit;
And one end of the second gain adjusting circuit is connected with the second-stage amplifying circuit, the other end of the second gain adjusting circuit is connected with the grounding end, and the second gain adjusting circuit is configured for carrying out gain adjustment on the second-stage amplifying circuit.
The radio frequency front-end module comprises a substrate and a low-noise amplifying chip arranged on the substrate, wherein the low-noise amplifying chip is provided with the low-noise amplifying circuit.
The radio frequency front-end module further comprises a first gain adjusting circuit and a second gain adjusting circuit, wherein the first gain adjusting circuit comprises a first gain adjusting inductor arranged on the substrate, and the second gain adjusting circuit comprises a second gain adjusting inductor arranged on the substrate;
One end of the first gain adjusting inductor is connected with the first-stage amplifying circuit arranged on the low-noise amplifying chip, and the other end of the first gain adjusting inductor is connected with the grounding end;
and one end of the second gain adjusting inductor is connected with the second-stage amplifying circuit arranged on the low-noise amplifying chip, and the other end of the second gain adjusting inductor is connected with the grounding end.
The low-noise amplifying circuit and the radio frequency front end module are characterized in that a first-stage output matching network of the low-noise amplifying circuit is connected between an output end of the second-stage amplifying circuit and a first power supply end and is configured to be associated with an imaginary part of output impedance of the low-noise amplifying circuit, the second-stage output matching network is connected between the output end of the second-stage amplifying circuit and the second power supply end and is a resistor network and is configured to be associated with a real part of the output impedance of the low-noise amplifying circuit, the output end of the second-stage amplifying circuit is connected with the second-stage output matching network, and the output impedance and gain of the low-noise amplifying circuit can be adjusted through the second-stage output matching network, so that the impedance matching of the output end of the low-noise amplifying circuit can be guaranteed, and the gain of the low-noise amplifying circuit can be guaranteed within a wide frequency range.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the description of the embodiments of the present invention will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a low noise amplifier circuit according to an embodiment of the invention;
FIG. 2 is a schematic diagram of a low noise amplifier according to an embodiment of the invention;
FIG. 3 is a schematic diagram of a low noise amplifier according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of a low noise amplifier according to an embodiment of the invention;
FIG. 5 is a schematic diagram of a low noise amplifier circuit according to an embodiment of the invention;
Fig. 6 is another circuit diagram of the low noise amplifying circuit according to an embodiment of the present invention.
In the figure, 10 parts of a first-stage amplifying circuit, 20 parts of a second-stage amplifying circuit, 30 parts of a first-stage output matching network, 40 parts of a second-stage output matching network, 41 parts of an impedance adjusting branch circuit, 50 parts of a first gain adjusting circuit, and 60 parts of a second gain adjusting circuit.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are some, but not all embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
It should be understood that the present invention may be embodied in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the dimensions and relative dimensions of layers and regions may be exaggerated for the same elements throughout for clarity.
It will be understood that when an element or layer is referred to as being "on," "adjacent," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent, connected, or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.
Spatially relative terms, such as "under," "below," "beneath," "under," "above," "over," and the like, may be used herein for ease of description to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "under" or "beneath" other elements would then be oriented "on" the other elements or features. Thus, the exemplary terms "below" and "under" may include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatially relative descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
In the following description, for the purpose of providing a thorough understanding of the present invention, detailed structures and steps are presented in order to illustrate the technical solution presented by the present invention. Preferred embodiments of the present invention are described in detail below, however, the present invention may have other embodiments in addition to these detailed descriptions.
As shown in fig. 1, the present embodiment provides a low noise amplifying circuit including a signal input terminal Vin, a signal output terminal Vout, a first stage amplifying circuit 10, a second stage amplifying circuit 20, a first stage output matching network 30, and a second stage output matching network 40, the first stage amplifying circuit 10 and the second stage amplifying circuit 20 being connected in series between the signal input terminal Vin and the signal output terminal Vout, the first stage output matching network 30 connected between an output terminal of the second stage amplifying circuit 20 and a first power supply terminal being configured to be associated with an imaginary part of an output impedance of the low noise amplifying circuit, the second stage output matching network 40 connected between an output terminal of the second stage amplifying circuit 20 and the second power supply terminal being a resistive network configured to be associated with a real part of the output impedance of the low noise amplifying circuit.
The signal input terminal Vin is an input terminal for inputting a radio frequency input signal in the low noise amplifying circuit. The signal output end Vout is an output end for outputting the amplified radio frequency amplified signal in the low noise amplifying circuit. The rf amplified signal is an rf signal obtained by amplifying an rf input signal by the first stage amplifying circuit 10 and the second stage amplifying circuit 20.
As an example, the first stage amplification circuit 10 and the second stage amplification circuit 20 are connected in series between the signal input terminal Vin and the signal output terminal Vout, and configured to perform multi-stage amplification on the radio frequency input signal. It should be noted that the low noise amplifying circuit in this embodiment may include at least two stages of amplifying circuits, in which the second stage amplifying circuit 20 serves as the last stage amplifying circuit. For example, if the low noise amplifying circuit includes N stages of amplifying circuits, the first N-1 stages of amplifying circuits are all the first stage amplifying circuit 10, and the last stage of amplifying circuit is the second stage amplifying circuit 20. The rf input signal is amplified by the first N-1 first stage amplifying circuits 10 and then amplified by the second stage amplifying circuit 20 to output an rf amplified signal, so as to ensure the gain of the low noise amplifying circuit in a wide frequency range.
As another example, the first stage output matching network 30, one end of which is connected to the output terminal of the first stage amplifying circuit 10 and the other end of which is connected to the first power supply terminal, is configured to be associated with the imaginary part of the output impedance of the low noise amplifying circuit. It will be appreciated that if the low noise amplifying circuit includes a plurality of first stage amplifying circuits 10, an output terminal of each first stage amplifying circuit 10 is correspondingly connected to one first stage output matching network 30. In the present embodiment, the first-stage output matching network 30 is related to the imaginary part Im of the output impedance of the low-noise amplification circuit in addition to the load as the first-stage amplification circuit 10, that is, the imaginary value Im of the output impedance of the low-noise amplification circuit mainly depends on the first-stage output matching network 30. Wherein the first stage output matching network 30 preferably comprises a first capacitor and a first inductor connected in parallel. Further, the first capacitance and/or the first inductance may be arranged to be adjustable so as to adjust the imaginary part Im [ ] of the output impedance of the low noise amplifying circuit, achieving impedance matching.
As another example, the second stage output matching network 40 is connected at one end to the output of the second stage amplifying circuit 20 and at the other end to the second power supply terminal, and the second stage output matching network 40 is a resistive network configured to be associated with the real part of the output impedance of the low noise amplifying circuit, i.e. the second stage output matching network 40 in the present application affects only the real part of the output impedance of the low noise amplifying circuit, which depends on the first stage output matching network 30. In a specific embodiment, the output end of the low noise amplifying circuit is required to realize impedance matching of 50 ohms, and the implementation of impedance matching of 50 ohms is required to ensure that both the real part Re and the imaginary part Im of the output impedance meet the impedance matching requirement. However, when the low noise amplification circuit operates over a wide frequency band, the impedance matching of the output terminal of the low noise amplification circuit is mainly dependent on the real part impedance of the output impedance. The application is characterized in that the output end of the first-stage amplifying circuit 10 is connected with the first-stage output matching network 30 and is configured to be associated with the imaginary part of the output impedance of the low-noise amplifying circuit, the output end of the second-stage amplifying circuit 20 is connected with the second-stage output matching network 40, the second-stage output matching network 40 is a resistor network and is configured to be associated with the real part of the output impedance of the low-noise amplifying circuit, so that the output impedance of the output end of the low-noise amplifying circuit can be accurately regulated through the second-stage output matching network 40 in a wider frequency range, and the impedance matching is realized.
Further, the gain of the low noise amplification circuit in this embodiment is associated with the second stage output matching network. In one embodiment, the low noise amplifier circuit may be considered to achieve output impedance matching while ensuring a certain gain. As is known from the total gain G ain＝Gm1*Gm2*Rout of the low-noise amplifying circuit, in the case where the first-stage amplifying gain G m1 and the second-stage amplifying gain G m2 are determined, the total gain of the low-noise amplifying circuit is mainly determined by the magnitude of the output impedance R out. The second-stage output matching network is a resistor network, so that the output impedance R out of the low-noise amplifying circuit mainly depends on the resistance value R presented by the resistor network, and therefore, the impedance matching of the output end of the low-noise amplifying circuit in a wider frequency range can be realized and the gain of the low-noise amplifying circuit can be ensured by adjusting the second-stage output matching network. The gain of the first stage amplification gain G m1 is mainly related to the size of the amplifying transistor in the first stage amplification circuit. The gain magnitude of the second stage amplification gain G m2 is mainly related to the size of the amplification transistor in the second stage amplification circuit.
In one embodiment, referring to fig. 2 below, the output impedance R out of the low-noise amplifying circuit is related to the impedance of node B at the output of the second-stage amplifying circuit 20, i.e., the output impedance R out＝R//R0 at the output of the low-noise amplifying circuit, in addition to the total resistance R presented in the second-stage output matching network 40, where R out is the actual output impedance of the low-noise amplifying circuit. R is the total resistance exhibited by the second stage output matching network 40. R 0 is the impedance of the node B at the output of the second stage amplification circuit 20. It can be appreciated that, since the low noise amplifying circuit includes N stages of amplifying circuits, the first N-1 stage amplifying circuit is the first stage amplifying circuit 10, and the last stage amplifying circuit is the second stage amplifying circuit 20, so that the impedance R 0 of the node B at the output end of the second stage amplifying circuit 20 is far greater than the total resistance R presented in the second stage output matching network 40, and further, according to the output impedance R out＝R//R0 of the low noise amplifying circuit, the output impedance of the low noise amplifying circuit can be directly deduced to be mainly related to the second stage output matching network 40.
Further, the output impedance of the low noise amplifying circuit is in direct proportion to the total resistance value R corresponding to the second stage output matching network 40, that is, the larger the total resistance value R presented by the second stage output matching network 40, the larger the output impedance R out of the low noise amplifying circuit is, and under the condition that the first stage amplifying gain Gm1 and the second stage amplifying gain Gm2 are determined, the larger the total gain of the low noise amplifying circuit is. Conversely, the smaller the total resistance R presented by the second stage output matching network 40, the smaller the output impedance R out of the low noise amplification circuit, and the smaller the total gain G ain of the low noise amplification circuit. Therefore, through the second-stage output matching network 40, the output impedance and the gain of the low-noise amplifying circuit can be accurately adjusted, so that the impedance matching of the output end of the low-noise amplifying circuit and the gain of the low-noise amplifying circuit can be ensured within a wider range.
In this embodiment, the first stage output matching network 30 is connected between the output end of the second stage amplifying circuit 20 and the first power supply end and is configured to be associated with the imaginary part of the output impedance of the low noise amplifying circuit, the second stage output matching network 40 is connected between the output end of the second stage amplifying circuit 20 and the second power supply end, and the second stage output matching network 40 is a resistor network and is configured to be associated with the real part of the output impedance of the low noise amplifying circuit.
In an embodiment, the resistor network is an output matching resistor, wherein the output impedance of the low noise amplifying circuit is proportional to the resistance value of the output matching resistor.
The output matching resistor is a resistor with a fixed resistance value. In a specific embodiment, since the output impedance and the gain of the low noise amplifying circuit are both related to the second stage output matching network 40, when impedance matching of the output end of the low noise amplifying circuit needs to be considered, the resistance value of the output matching resistor connected to the output end of the second stage amplifying circuit can be determined directly according to the impedance matching value of the output end. When the total gain value of the low-noise amplifying circuit is needed to be considered, the resistance value of the output matching resistor connected to the output end of the second-stage amplifying circuit can be determined directly according to the total gain value of the low-noise amplifying circuit, so that the impedance matching of the output end of the low-noise amplifying circuit can be ensured, and the gain of the low-noise amplifying circuit can be ensured within a wider frequency range.
In one embodiment, as shown in fig. 2, the resistor network is an adjustable resistor R configured to adjust the real part of the output impedance of the low noise amplifier circuit.
In a specific embodiment, the resistor network is set to be an adjustable resistor R, so that the output impedance and the gain of the low-noise amplifying circuit can be adjusted in real time according to actual requirements. For example, the low noise amplifying circuit can set the adjustable resistor R to any resistance value meeting the requirement according to the received control command, so that the output impedance and gain of the output end of the low noise amplifying circuit can be adjusted through the second stage output matching network 40 within a wider frequency range.
In one embodiment, as shown in fig. 6, the second stage output matching network 40 includes a plurality of impedance adjusting branches 41, each impedance adjusting branch 41 includes a matching switch and a matching resistor connected in series, a first end of the plurality of impedance adjusting branches 41 is connected to the output terminal of the second stage amplifying circuit 20, and a second end of the plurality of impedance adjusting branches 41 is connected to the second power supply terminal.
As an example, the second stage output matching network 40 includes a plurality of impedance adjusting branches 41, each impedance adjusting branch 41 includes a matching switch and a matching resistor connected in series, where the resistance value of the matching resistor in each impedance adjusting branch 41 can be set in a customized manner according to the actual requirement, and is used for adjusting the output impedance and the gain of the low noise amplifying circuit.
In this embodiment, the second stage output matching network 40 includes a first impedance adjusting leg 41, a second impedance adjusting leg 41/. The nth impedance adjusting leg 41. The first impedance adjusting branch 41 comprises a first matching switch S1 and a first matching resistor R1, the second impedance adjusting branch 41 comprises a second matching switch S2 and a second matching resistor R2/. Sup./nth impedance adjusting branch 41 comprises an nth matching switch Sn and an nth matching resistor Rn. The first matching resistor R1 and the second matching resistor R2/nth matching resistor Rn connected to the low noise amplifying circuit can be controlled by the first matching switch S1 and the second matching switch S2/nth matching switch Sn, so that the output impedance and the gain of the low noise amplifying circuit can be adjusted, and the gain can be ensured while the impedance matching is satisfied. For example, when the first matching switch S1 is turned off and the second matching switch S2/. Once/N matching switch Sn is turned off, the first matching resistor R1 functions as a second stage output matching network, and the resistance value of the first matching resistor R1 is associated with the output impedance and gain of the low noise amplifying circuit. As another example, when the first matching switch S1 and the second matching switch S2 are turned off and the remaining matching switches are turned off, the first matching resistor R1 and the second matching resistor R2 function as a second-stage output matching network, and the parallel resistance value of the first matching resistor R1 and the second matching resistor R2 is associated with the output impedance and the gain of the noise amplifying circuit.
In an embodiment, as shown in fig. 3 to 5, the first stage output matching network 30 may be formed by at least two of the first resistor R31, the first capacitor C31, and the first inductor L31 connected in parallel.
In this embodiment, the first stage output matching network 30 includes a first resistor R31 and a first capacitor C31 connected in parallel. Or the first stage output matching network 30 includes a first capacitor C31 and a first inductor L31 in parallel. Or the first stage output matching network 30 includes a first resistor R31 and a first inductor L31 in parallel. Or the first stage output matching network 30 includes a first resistor R31, a first capacitor C31, and a first inductor L31 in parallel. It should be noted that, the parallel connection manner between the first resistor R31, the first capacitor C31, and the first inductor L31 and the parameter sizes corresponding to the first resistor R31, the first capacitor C31, and the first inductor L31 may be selected according to the actual requirement, so as to adjust the imaginary impedance in the output impedance of the low noise amplifying circuit.
It should be noted that, in a specific embodiment, when the first stage output matching network 30 includes the first resistor R31, the magnitude of the first resistor R31 affects the real part of the output impedance of the low noise amplifying circuit, but the present application has the second stage output matching network 40 connected to the output terminal of the second stage amplifying circuit 20, so that the real part of the output impedance of the low noise amplifying circuit is mainly determined by the second stage output matching network 40, and the first resistor R31 in the first stage output matching network 30 hardly affects the real part of the output impedance of the low noise amplifying circuit.
In an embodiment, as shown in fig. 2, the first stage output matching network 30 includes a first capacitor C31 and a first inductor L31 connected in parallel, where the first capacitor C31 is an adjustable capacitor.
In the present embodiment, the first stage output matching network 30 includes a first capacitor C31 and a first inductance L31 connected in parallel, configured to adjust an imaginary impedance in the output impedance of the low noise amplification circuit. Preferably, the first capacitor C31 is an adjustable capacitor, so as to facilitate adjustment of the imaginary impedance in the output impedance of the low noise amplifying circuit, so as to ensure that the adjustment of the imaginary impedance in the output impedance of the low noise amplifying circuit is implemented in a wider frequency band range.
In one embodiment, as shown in fig. 2, the first stage amplifying circuit 10 includes a first blocking capacitor C11, a first amplifying transistor M11, a second amplifying transistor M12 and a second blocking capacitor C12, where a first end of the first blocking capacitor C11 is connected to the signal input terminal Vin, a second end of the first blocking capacitor C11 is connected to the first end of the first amplifying transistor M11, a second end of the first amplifying transistor M11 is connected to a third end of the second amplifying transistor M12, a third end of the first amplifying transistor M11 is connected to a ground terminal, a first end of the second amplifying transistor M12 is connected to the ground terminal through the second blocking capacitor C12, and a second end of the second amplifying transistor M12 is connected to an input terminal of the second stage amplifying circuit 20 as an output terminal of the first stage amplifying circuit 10.
As an example, the first amplifying transistor M11 and the second amplifying transistor M12 may be transistors or field effect transistors. The second amplifying transistor M12 may also be a plurality of cascaded transistors or a plurality of cascaded field effect transistors. When the first-stage amplifying circuit 10 receives the radio frequency input signal input from the signal input terminal Vin, the first-stage amplifying transistor M11 and the second amplifying transistor M12 amplify the radio frequency input signal in multiple stages, and output a first-stage radio frequency amplified signal.
As another example, as shown in fig. 2 or 3, when the first and second amplifying transistors M11 and M12 are transistors, the first and second amplifying transistors M11 and M12 may be NPN transistors. The first end of the first blocking capacitor C11 is connected with the signal input end Vin, the second end of the first blocking capacitor C11 is connected with the first end of the first amplifying transistor M11, the second end of the first amplifying transistor M11 is connected with the third end of the second amplifying transistor M12, the third end of the first amplifying transistor M11 is connected with the grounding end and is configured to amplify the radio frequency input signal.
As another example, the first end of the second amplifying transistor M12 is connected to the ground end through the second blocking capacitor C12, and the second end of the second amplifying transistor M12 is connected to the input end of the second amplifying circuit 20 as the output end of the first amplifying circuit 10, and is configured to re-amplify the rf input signal amplified by the first amplifying transistor M11 and output the first-stage rf amplified signal. The second blocking capacitor C12 is configured to filter the harmonic or interference signal input to the first end of the second amplifying transistor M12.
In an embodiment, as shown in fig. 2, the second stage amplifying circuit 20 includes a third blocking capacitor C21, a fourth blocking capacitor C22, a third amplifying transistor M21 and a fourth amplifying transistor M22, where a first end of the third blocking capacitor C21 is used as an input end of the second stage amplifying circuit 20 and connected to an output end of the first stage amplifying circuit 10, a second end of the third blocking capacitor C21 is connected to a first end of the third amplifying transistor M21, a second end of the third amplifying transistor M21 is connected to a third end of the fourth amplifying transistor M22, a third end of the third amplifying transistor M21 is connected to a ground end, a first end of the fourth amplifying transistor M22 is connected to the ground end through the fourth blocking capacitor C22, and a second end of the fourth amplifying transistor M22 is used as an output end of the second stage amplifying circuit 20 and connected to the second stage output matching network 40.
As an example, the third amplifying transistor M21 and the fourth amplifying transistor M22 may be transistors or field effect transistors. The fourth amplifying transistor M22 may also be a plurality of cascaded transistors or a plurality of cascaded field effect transistors. When the first-stage amplifying circuit 10 receives the radio frequency input signal input from the signal input terminal Vin, the radio frequency input signal amplified by the first-stage amplifying circuit is subjected to second-stage amplifying processing by the third amplifying transistor M21 and the fourth amplifying transistor M22, and the second-stage radio frequency amplified signal is output.
As another example, when the third and fourth amplifying transistors M21 and M22 are transistors, the third and fourth amplifying transistors M21 and M22 may be NPN transistors. The first end of the third blocking capacitor C21 is used as an input end of the second-stage amplifying circuit 20 and connected with an output end of the first-stage amplifying circuit 10, the second end of the third blocking capacitor C21 is connected with the first end of the third amplifying transistor M21, the second end of the third amplifying transistor M21 is connected with the third end of the fourth amplifying transistor M22, the third end of the third amplifying transistor M21 is connected with a ground end, and the third end of the third amplifying transistor M21 is configured to amplify the first-stage radio frequency amplifying signal.
As another example, the first end of the fourth amplifying transistor M22 is connected to the ground end through the fourth blocking capacitor C22, and the second end of the fourth amplifying transistor M22 is connected to the second-stage output matching network 40 as the output end of the second-stage amplifying circuit 20, and is configured to amplify the first-stage rf amplified signal amplified by the third amplifying transistor M21 again and output the second-stage rf amplified signal. The second blocking capacitor C12 is configured to filter the harmonic or interference signal input to the first end of the fourth amplifying transistor M22.
In one embodiment, as shown in fig. 2, the low noise amplifying circuit further includes a first gain adjusting circuit 50 and a second gain adjusting circuit 60, wherein one end of the first gain adjusting circuit 50 is connected to the first stage amplifying circuit 10, the other end is connected to the ground terminal and is configured to perform gain adjustment on the first stage amplifying circuit 10, and one end of the second gain adjusting circuit 60 is connected to the second stage amplifying circuit 20, the other end is connected to the ground terminal and is configured to perform gain adjustment on the second stage amplifying circuit 20.
As an example, the first gain adjusting circuit 50 has one end connected to the first-stage amplifying circuit 10 and the other end connected to the ground, and is configured to perform gain adjustment on the first-stage amplifying circuit 10. Specifically, the first gain adjustment circuit 50 includes a first gain adjustment inductance L51, one end of the first gain adjustment inductance L51 is connected to the first-stage amplification circuit 10, and the other end is connected to the ground, and is configured to perform gain adjustment on the first-stage amplification circuit 10.
As another example, the second gain adjustment circuit 60 has one end connected to the second-stage amplification circuit 20 and the other end connected to the ground, and is configured to perform gain adjustment on the second-stage amplification circuit 20. Specifically, the second gain adjustment circuit 60 includes a second gain adjustment inductance L61, and one end of the second gain adjustment inductance L61 is connected to the first-stage amplification circuit 10, and the other end is connected to the ground terminal, and is configured to perform gain adjustment on the second-stage amplification circuit 20.
In this embodiment, the first gain adjusting circuit 50 has one end connected to the first stage amplifying circuit 10 and the other end connected to the ground terminal and is configured to perform gain adjustment on the first stage amplifying circuit 10, and the second gain adjusting circuit 60 has one end connected to the second stage amplifying circuit 20 and the other end connected to the ground terminal and is configured to perform gain adjustment on the second stage amplifying circuit 20 and to increase the gain of the low noise amplifying circuit.
The embodiment provides a radio frequency front-end module, which comprises a substrate and a low-noise amplifying chip arranged on the substrate, wherein the low-noise amplifying chip is provided with the low-noise amplifying circuit in the embodiment, and the low-noise amplifying circuit can realize impedance matching of an output end and simultaneously can ensure a certain gain.
In an embodiment, the radio frequency front end module further includes a first gain adjusting circuit 50 and a second gain adjusting circuit 60, the first gain adjusting circuit 50 includes a first gain adjusting inductor L51, the second gain adjusting circuit 60 includes a second gain adjusting inductor L61, one end of the first gain adjusting inductor L51 is connected to the first stage amplifying circuit 10 on the low noise amplifying chip, the other end of the first gain adjusting inductor L51 is connected to the ground, one end of the second gain adjusting inductor L61 is connected to the second stage amplifying circuit 20 on the low noise amplifying chip, the other end of the second gain adjusting inductor L61 is connected to the ground, and the first gain adjusting inductor L51 and the second gain adjusting inductor L61 are respectively disposed on the substrate.
In this embodiment, a first gain adjustment inductance L51 has one end connected to the first stage amplification circuit 10 on the low noise amplification chip and the other end connected to the ground terminal, and is configured to perform gain adjustment on the first stage amplification circuit 10, and a second gain adjustment inductance L61 has one end connected to the second stage amplification circuit 20 on the low noise amplification chip and the other end connected to the ground terminal, and is configured to perform gain adjustment on the second stage amplification circuit 20. Further, since the total occupied area of the first gain adjusting inductor L51 and the second gain adjusting inductor L61 is larger, the total occupied area of the low noise amplifying chip can be reduced, the mask number of the low noise amplifying chip can be reduced, and the cost of the low noise amplifying chip can be reduced.
The foregoing embodiments are merely illustrative of the technical solutions of the present invention, and not restrictive, and although the present invention has been described in detail with reference to the foregoing embodiments, it should be understood by those skilled in the art that modifications may still be made to the technical solutions described in the foregoing embodiments or equivalent substitutions of some technical features thereof, and that such modifications or substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention.
Claims (11)
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| CN114567271B (en) * | 2022-02-22 | 2023-09-19 | 锐石创芯(深圳)科技股份有限公司 | Low noise amplifying circuit and radio frequency front end module |
| CN114884470A (en) * | 2022-05-11 | 2022-08-09 | 锐石创芯(深圳)科技股份有限公司 | Low-noise amplifying circuit and low-noise amplifier structure |
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| US7489201B2 (en) * | 2006-05-10 | 2009-02-10 | Georgia Tech Research Corp. | Millimeter-wave cascode amplifier gain boosting technique |
| TWI344263B (en) * | 2008-01-25 | 2011-06-21 | Univ Nat Taiwan | Low-noise amplifier |
| US9929701B1 (en) * | 2016-09-21 | 2018-03-27 | Psemi Corporation | LNA with programmable linearity |
| CN109951163A (en) * | 2019-03-01 | 2019-06-28 | 西安电子科技大学 | A Multiple Feedback Broadband Low Noise Amplifier |
| CN211063579U (en) * | 2020-06-12 | 2020-07-21 | 成都锐新科技有限公司 | X-waveband low-noise amplifier |
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