CN113506781A

CN113506781A - Semiconductor structure and manufacturing method thereof

Info

Publication number: CN113506781A
Application number: CN202110636069.3A
Authority: CN
Inventors: 吕文隆
Original assignee: Advanced Semiconductor Engineering Inc
Current assignee: Advanced Semiconductor Engineering Inc
Priority date: 2021-06-08
Filing date: 2021-06-08
Publication date: 2021-10-15

Abstract

In the semiconductor structure and the manufacturing method thereof provided by the present disclosure, a calibration mold is designed to assist the positioning of electronic components, and at the same time, in order to avoid damage to the electronic components during the calibration process, corresponding chamfers are respectively made on the calibration mold and the electronic components, and the electronic components can be Motion correction along the chamfer to improve positioning accuracy.

Description

Semiconductor structure and manufacturing method thereof

Technical Field

The present disclosure relates to the field of semiconductor technology, and more particularly, to a semiconductor structure and a method for fabricating the same.

Background

Currently, when electronic components are embedded, a Pick-and-Place (Pick-and-Place) device is mostly needed to control the positioning accuracy of the electronic components, and if the electronic components are deviated, the yield of subsequent circuits or other processes is affected. The main technical means at present is to improve the pick-up precision of the pick-up device.

Disclosure of Invention

The present disclosure provides semiconductor structures and methods of fabricating the same.

In a first aspect, the present disclosure provides a semiconductor structure comprising: a first electronic component having opposing first and second surfaces, the second surface having a chamfer; the first circuit layer is arranged on the first surface and electrically connected with the first electronic component.

In some alternative embodiments, the chamfer extends from the second surface to a side between the second surface and the first surface.

In some alternative embodiments, the angle of the chamfer is between 30 and 85 degrees.

In some optional embodiments, the semiconductor structure further comprises: and the second electronic component is adjacent to the first electronic component, and the horizontal distance between the first electronic component and the second electronic component is greater than the length of a right-angle side projected to the horizontal direction by the chamfer.

In some optional embodiments, the semiconductor structure further comprises: and the mold sealing layer is used for coating the first electronic component and is provided with a third surface and a fourth surface which are opposite.

In some alternative embodiments, the molding compound exposes the chamfer of the first electronic component.

In some alternative embodiments, the mold seal covers the chamfer of the first electronic component.

In some optional embodiments, the semiconductor structure further comprises: the substrate is electrically connected with the first circuit layer.

In some alternative embodiments, the substrate has a through hole, the first electronic component is disposed in the through hole, and the mold sealing layer fills a gap between the first electronic component and the through hole.

In some alternative embodiments, the chamfer is a radiused chamfer.

In some optional embodiments, the semiconductor structure further comprises: the first circuit layer is exposed from the first opening to form a first conductive pad.

In some optional embodiments, the semiconductor structure further comprises: the second circuit layer is arranged on the fourth surface and is electrically connected with the substrate; and the second solder mask layer is arranged on the second circuit layer and provided with a plurality of second openings, and the second circuit layer exposed from the second openings forms a second conductive pad.

In a second aspect, the present disclosure provides a method of fabricating a semiconductor structure, the method comprising: providing a first carrier, the first carrier having an upper surface; arranging a first electronic component on the upper surface; and applying force to the first electronic component by using the correcting mould so as to correct the horizontal position of the first electronic component.

In some alternative embodiments, the first electronic component and the calibration mold each have a corresponding chamfer.

In some alternative embodiments, the upper surface is a vacuum table or tape.

In some optional embodiments, the method further comprises: providing a substrate; arranging a through hole on the substrate; the substrate is arranged on the upper surface, so that the first electronic assembly is arranged in the through hole.

In some optional embodiments, the method further comprises: and forming a mold sealing layer for coating the substrate and the first electronic component and filling the gap between the through hole and the first electronic component.

In some alternative embodiments, the chamfer of the first electronic component is formed by: arranging a wafer on the second carrier, wherein the wafer is provided with an active surface and a back surface; half-cutting the active surface by using a first cutter to disconnect the electrical connection; turning over to fix the wafer on a third carrier; and cutting the back surface by using a second cutter with cutter chamfering to separate the wafer and form a chamfer on the back surface to obtain a first electronic component with the chamfer.

In some alternative embodiments, the encapsulation layer has third and fourth opposing surfaces.

In some optional embodiments, the method further comprises: a first circuit layer is arranged on the third surface and is electrically connected with the first electronic component and the substrate respectively; arranging a first solder mask layer on the first circuit layer; a plurality of openings are arranged on the first solder mask layer, and the first circuit layer exposed from the openings forms a first conductive gasket.

In some optional embodiments, the method further comprises: a second circuit layer is arranged on the fourth surface and electrically connected with the substrate; arranging a second solder mask layer on the second circuit layer; a plurality of openings are formed in the second solder mask layer, and the second circuit layer exposed from the openings forms a second conductive pad.

In order to solve the technical problem that the yield of a subsequent circuit or other processes is affected due to the deviation of an electronic component, the semiconductor structure and the manufacturing method thereof provided by the disclosure assist the positioning of the electronic component by designing a correction die, and simultaneously, in order to avoid the electronic component from being damaged in the correction process, corresponding chamfers are respectively manufactured on the correction die and the electronic component, and the electronic component can be moved and corrected along the chamfers, so that the positioning precision is improved. In addition, the semiconductor structure and the manufacturing method thereof provided by the disclosure can be used for simultaneously correcting two or more electronic components.

Drawings

Other features, objects and advantages of the disclosure will become more apparent upon reading of the following detailed description of non-limiting embodiments thereof, made with reference to the accompanying drawings in which:

fig. 1-6 are first through sixth schematic structural views of a semiconductor structure according to the present disclosure;

fig. 7A to 7O are schematic structural views in the manufacturing process of a semiconductor structure according to the present disclosure.

Description of the symbols:

1-a first electronic component, 11-a chamfer, 12-a first surface, 13-a second surface, 121-a side, 2-a second electronic component, 21-a second chamfer, 3-a first circuit layer, 31-a first conductive pad, 4-a mold seal, 41-a mold seal, 42-a third surface, 43-a fourth surface, 5-a substrate, 51-a via, 52-a rewiring layer, 6-a second circuit layer, 61-a second conductive pad, 7-a first solder mask, 8-a second solder mask, 9-a calibration mold, 91-a mold chamfer, 10-an underfill, 141-a second carrier, 14-a third carrier, 15-a wafer, 16-a first cutter, 17-a second cutter, 171-a cutter chamfer, 18-first carrier, 181-upper surface, 19-punch die, 20-fourth carrier, theta-chamfer angle.

Detailed Description

The following description of the embodiments of the present disclosure will be provided in conjunction with the accompanying drawings and examples, and those skilled in the art can easily understand the technical problems and effects of the present disclosure. It is to be understood that the specific embodiments described herein are merely illustrative of the relevant invention and not restrictive of the invention. In addition, for convenience of description, only portions related to the related invention are shown in the drawings.

It should be noted that the structures, proportions, and dimensions shown in the drawings and described in the specification are for the understanding and reading of the present disclosure, and are not intended to limit the conditions under which the present disclosure can be implemented, so they are not technically significant, and any modifications of the structures, changes in the proportions and adjustments of the dimensions should be made without affecting the efficacy and attainment of the same. In the present specification, the terms "upper", "first", "second" and "first" are used for clarity of description only, and are not intended to limit the scope of the present disclosure, and changes or modifications in relative relationships thereof should be construed as being within the scope of the present disclosure without substantial technical changes.

In addition, the embodiments and features of the embodiments in the present disclosure may be combined with each other without conflict. Fig. 1-6 illustrate first through sixth schematic structural views of a semiconductor structure of the present disclosure. The present disclosure will be described in detail below with reference to fig. 1 to 6 in conjunction with an embodiment.

Fig. 1 shows a first structural schematic of a semiconductor structure of the present disclosure. The semiconductor structure shown in fig. 1 may include a first electronic component 1, a first circuit layer 3, a molding compound layer 4, a substrate 5, a second circuit layer 6, a first solder mask layer 7, and a second solder mask layer 8.

In this embodiment, the first electronic component 1 may have a first surface 12 and a second surface 13 opposite to each other. The first electronic component 1 may be, for example, a chip or the like having various functions.

The first circuit layer 3 may be disposed on the first surface 12 and electrically connected to the first electronic component 1. The first wiring layer 3 may include a conductive material such as gold (Au), silver (Ag), aluminum (Al), nickel (Ni), palladium (Pd), copper (Cu), or an alloy thereof.

The substrate 5 may be electrically connected to the first circuit layer 3. The substrate 5 may have a through hole 51, and the first electronic component 1 may be provided in the through hole 51. The substrate 5 may include a redistribution layer 52. The substrate 5 may include Polyimide (PI), ABF base material (ABF), molding compound (molding compound), pre-impregnated composite fibers (e.g., prepreg), borosilicate glass (BPSG), silicon oxide (silicon oxide), silicon nitride (silicon nitride), silicon oxynitride (silicon oxide), doped silicate glass (USG), combinations thereof, or the like. The substrate 5 may include a conductive material such as gold (Au), silver (Ag), aluminum (Al), nickel (Ni), palladium (Pd), copper (Cu), or an alloy thereof.

The molding layer 4 may encapsulate the first electronic component 1. The mold seal layer 4 may fill the gap between the first electronic component 1 and the via hole 51. The structure is not easy to deform and expand under the condition of temperature change, and can keep the original shape of an object under the condition of large temperature difference. The molding layer 4 may be made of a molding material such as Epoxy resin (Epoxy resin), Filler (Filler), Catalyst (Catalyst), Pigment (Pigment), Release Agent (Release Agent), Flame Retardant (Flame Retardant), Coupling Agent (Coupling Agent), Hardener (hardner), Low Stress absorbent (Low Stress Absorber), Adhesion Promoter (Adhesion Promoter), Ion trap (Ion Trapping Agent), or the like. The molding layer 4 may have third and fourth opposing

surfaces

42, 43.

The first solder resist layer 7 may be provided on the first wiring layer 3. The first solder resist layer 7 may have a plurality of first openings. The first wiring layer 3 exposed from the first opening may constitute a first conductive pad 31.

The second circuit layer 6 may be provided on the fourth surface 43. The second circuit layer 6 may be electrically connected to the substrate 5. The second solder resist layer 8 may be provided on the second wiring layer 6. The second solder resist layer 8 may have a plurality of second openings. The second wiring layer 6 exposed from the second opening may constitute a second conductive pad 61.

The second surface 13 of the first electronic component 1 may have a chamfer 11. The chamfer 11 may extend from the second surface 13 to a side 121 between the second surface 13 and the first surface 12. The chamfer angle θ may be between 30 degrees and 85 degrees. Providing the chamfer 11 may provide for greater alignment accuracy during processing.

Fig. 2 shows a second structural schematic of the semiconductor structure of the present disclosure. As shown in fig. 2, the semiconductor structure shown in fig. 1 is different in that the chamfer 11 shown in fig. 1 may be a bevel chamfer, and the chamfer 11 shown in fig. 2 may be a circular arc chamfer. That is, the shape of the chamfer may be various shapes, such as a chamfer, a circular arc chamfer, or may be different angles/radians, such as a 45 degree chamfer.

Fig. 3 illustrates a third structural schematic of the semiconductor structure of the present disclosure. As shown in fig. 3, the semiconductor structure is different from the semiconductor structure shown in fig. 1 in that the mold sealing layer 4 shown in fig. 1 may cover the first electronic component 1, and the mold sealing layer 4 shown in fig. 3 may expose the chamfer 11 of the first electronic component 1. I.e. the mould seal 4 may or may not completely cover the first electronic component 1.

Fig. 4 shows a fourth structural schematic of the semiconductor structure of the present disclosure. As shown in fig. 4, the difference with the semiconductor structure shown in fig. 1 is that the semiconductor structure shown in fig. 4 may further comprise a second electronic component 2.

In this embodiment, the second electronic component 2 may be adjacent to the first electronic component 1. The horizontal distance between the first electronic component 1 and the second electronic component 2 may be greater than the length of the cathetus of the chamfer 11 projected in the horizontal direction. The second component 2 may have a second chamfer 21.

Fig. 5 shows a fifth structural schematic of the semiconductor structure of the present disclosure. As shown in fig. 5, the semiconductor structure shown in fig. 1 is different in that the first electronic component 1 shown in fig. 1 is located closer to the center position, and the first electronic component 1 shown in fig. 5 is located closer to the edge position.

Fig. 6 shows a sixth structural schematic of the semiconductor structure of the present disclosure. As shown in fig. 6, the semiconductor structure shown in fig. 6 may further include an underfill material 10, which is different from the semiconductor structure shown in fig. 1.

In the present embodiment, the underfill material 10 may be used to protect the pins of the first electronic component 1 and fill the gaps between the pins of the first electronic component 1. The underfill material 10 may fill the voids for reinforcement purposes. The underfill material 10 may be, for example, Capillary Underfill (CUF), Molded Underfill (MUF), Non-conductive Paste (NCP), or the like.

The semiconductor structure provided by the present disclosure first sets a correction mold 9 (as shown in fig. 7I and 7J) for correcting the first electronic component 1, and then by providing a chamfer 11 corresponding to the mold chamfer 91 of the correction mold 9 on the first electronic component 1, and/or a second chamfer 21 corresponding to the mold chamfer 91 of the correction mold 9 on the second electronic component 2, the first electronic component 1 and/or the second electronic component 2 can realize movement correction along the mold chamfer 91 to improve positioning accuracy.

Fig. 7A to 7O show structural schematics in the fabrication of a semiconductor structure according to the present disclosure. The figures have been simplified for a better understanding of various aspects of the disclosure.

Referring to fig. 7A-7E, the chamfer 11 of the first electronic component 1 may be formed by: referring to fig. 7A, a wafer 15 is disposed on the second carrier 141. The wafer 15 may have an active side and a back side. Referring to fig. 7B, the active surface of the wafer 15 is half-cut by the first tool 16 to break the electrical connection. Referring to fig. 7C, the wafer 15 is mounted on the third carrier 14 by flipping and the second carrier 141 is removed. Referring to fig. 7D, the wafer 15 is separated and a chamfer 11 is formed on the back side by cutting the back side of the wafer 15 with a second tool 17 having a tool chamfer 171. Referring to fig. 7E, the first electronic component 1 with the chamfer 11 is obtained.

Referring to fig. 7F, a substrate 5 is provided.

Referring to fig. 7G and 7H, a through hole 51 is provided in the substrate 5 by a punch 19 (e.g., punch). The substrate 5 having the through-hole 51 is obtained.

Referring to fig. 7I, the calibration jig 9 shown in fig. 7I may be used to calibrate one electronic component (the first electronic component 1). First, a first carrier 18 is provided, the first carrier 18 having an upper surface 181. Then, the first electronic component 1 may be provided on the upper surface 181. Finally, the first electronic component 1 may be forced by means of the correction die 9 to correct the horizontal position of the first electronic component 1.

Referring to fig. 7J, the calibration jig 9 shown in fig. 7J can be used to calibrate two or more electronic components (the first electronic component 1 and the second electronic component 2) at the same time by first providing the first carrier 18, wherein the first carrier 18 has an upper surface 181. Then, the first electronic component 1 and the second electronic component 2 may be provided on the upper surface 181. Finally, the first electronic component 1 and the second electronic component 2 may be forced by the correction mold 9 to correct the horizontal positions of the first electronic component 1 and the second electronic component 2.

Specifically, the correction die 9 may be obtained by providing a die chamfer 91 on the ram (pressing head). The correcting mold 9 can be used not only to carry the first electronic component 1 and/or the second electronic component 2 onto the upper surface 181, but also to perform a correcting positioning of the first electronic component 1 and/or the second electronic component 2 by using the mold chamfer 91 of the correcting mold 9.

The upper surface 181 may be provided with a fixing stage, such as a vacuum suction stage, an electrostatic suction stage, or a tape (tape). This may be used to secure the first electronic component 1 and/or the second electronic component 2, providing a restraining force. The first electronic component 1 and/or the second electronic component 2 can thus be corrected for movement along the mould chamfer 91.

Referring to fig. 7K, the substrate 5 is disposed on the upper surface 181, such that the first electronic component 1 is disposed in the through hole 51.

Referring to fig. 7L and 7M, a mold sealing material 41 is disposed on the fourth carrier 20, and the substrate 5 and the first electronic component 1 are bonded to the mold sealing material 41 to form a mold sealing layer 4 covering the substrate 5 and the first electronic component 1 and filling a gap between the through hole 51 and the first electronic component 1. The molding layer 4 may have third and fourth opposing

surfaces

42, 43.

Referring to fig. 7N, a first circuit layer 3 is disposed on the third surface 42. The first circuit layer 3 may be electrically connected to the first electronic component 1 and the substrate 5, respectively. A second circuit layer 6 is provided on the fourth surface 43. The second circuit layer 6 may be electrically connected to the substrate 5.

Referring to fig. 7O, a first solder mask layer 7 is disposed on the first circuit layer 3. A plurality of first openings are provided on the first solder mask layer 7. The first wiring layer 3 exposed from the first opening may constitute a first conductive pad 31. A second solder mask layer 8 is provided on the second circuit layer 6. A plurality of second openings are provided on the second solder mask layer 8. The second wiring layer 6 exposed from the second opening may constitute a second conductive pad 61.

According to the method for manufacturing the semiconductor structure, the first electronic component 1 and/or the second electronic component 2 are/is assisted to be positioned by designing the correcting die 9, and meanwhile, in order to avoid the first electronic component 1 and/or the second electronic component 2 from being damaged in the correcting process, the die chamfer 91 is arranged on the correcting die 9, the corresponding chamfer 11 is manufactured on the first electronic component 1, and the corresponding second chamfer 21 is manufactured on the second electronic component 2. A fixed stage (e.g., a vacuum table, an electrostatic table, or a tape (tape)) on the upper surface 181 may assist in providing a restraining force so that the first electronic component 1 and/or the second electronic component 2 may be corrected for movement along the mold chamfer 91 to improve positioning accuracy.

The method for manufacturing the semiconductor structure provided by the present disclosure can achieve similar technical effects to the aforementioned semiconductor structure, and is not repeated here.

While the present disclosure has been described and illustrated with reference to particular embodiments thereof, such description and illustration are not intended to limit the present disclosure. It will be clearly understood by those skilled in the art that various changes may be made and equivalents may be substituted for elements thereof within the embodiments without departing from the true spirit and scope of the disclosure as defined by the appended claims. The illustrations may not be drawn to scale. There may be a difference between the technical reproduction and the actual implementation in the present disclosure due to variables in the manufacturing process, and the like. There may be other embodiments of the disclosure that are not specifically illustrated. The specification and drawings are to be regarded in an illustrative rather than a restrictive sense. Modifications may be made to adapt a particular situation, material, composition of matter, method, or process to the objective, spirit and scope of the present disclosure. All such modifications are intended to fall within the scope of the appended claims. Although the methods disclosed herein have been described with reference to particular operations performed in a particular order, it should be understood that these operations may be combined, sub-divided, or reordered to form equivalent methods without departing from the teachings of the present disclosure. Accordingly, unless specifically indicated herein, the order and grouping of the operations is not a limitation of the present disclosure.

Claims

1. A semiconductor structure comprising:

a first electronic component having opposing first and second surfaces, the second surface having a chamfer;

The first circuit layer is disposed on the first surface and is electrically connected to the first electronic component.

2. The semiconductor structure of claim 1, wherein the chamfer extends from the second surface to a side between the second surface and the first surface.

3. The semiconductor structure of claim 1, wherein the semiconductor structure further comprises:

The molding layer covers the first electronic component.

4. The semiconductor structure of claim 3, wherein the semiconductor structure further comprises:

a substrate electrically connected to the first circuit layer, the substrate has a through hole, the first electronic component is arranged in the through hole, and the molding layer fills the first electronic component and the through hole gap between.

5. A method of fabricating a semiconductor structure, comprising:

providing a first carrier having an upper surface;

disposing the first electronic component on the upper surface;

A force is applied to the first electronic component by a correcting mold to correct the horizontal position of the first electronic component.

6. The method of claim 5, wherein the first electronic component and the calibration mold respectively have corresponding chamfers.

7. The method of claim 5 or 6, wherein the upper surface is a vacuum table or tape.

8. The method of claim 5 or 6, wherein the method further comprises:

provide the substrate;

through holes are provided on the substrate;

A substrate is arranged on the upper surface, so that the first electronic component is placed in the through hole.

9. The method of claim 8, wherein the method further comprises:

A molding layer covering the substrate and the first electronic component and filling the gap between the through hole and the first electronic component is formed.

10. The method of claim 6, wherein the chamfer of the first electronic component is formed by:

Disposing a wafer on the second carrier, the wafer has an active surface and a back surface;

Half-cutting the active surface with a first cutter to disconnect the electrical connection;

turning over to fix the wafer on the third carrier;

The backside is cut with a second tool with a tool chamfer to separate the wafer and form a chamfer on the backside to obtain a first electronic component with a chamfer.