CN113241942B - A Bootstrap Drive Circuit Applied to Four-Switch Buck-Boost Converter - Google Patents
A Bootstrap Drive Circuit Applied to Four-Switch Buck-Boost Converter Download PDFInfo
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- CN113241942B CN113241942B CN202110600701.9A CN202110600701A CN113241942B CN 113241942 B CN113241942 B CN 113241942B CN 202110600701 A CN202110600701 A CN 202110600701A CN 113241942 B CN113241942 B CN 113241942B
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of DC power input into DC power output
- H02M3/02—Conversion of DC power input into DC power output without intermediate conversion into AC
- H02M3/04—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters
- H02M3/06—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using resistors or capacitors, e.g. potential divider
- H02M3/07—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
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Abstract
The embodiment of the invention provides a bootstrap drive circuit applied to a four-switch buck-boost converter, which comprises a first bridge arm and a second bridge arm which are connected through an inductor, wherein the first bridge arm and the second bridge arm are used for switching buck, buck-boost or boost working modes of the circuit, the circuit further comprises a control module, a drive module and a charging module, the control module controls 100% duty ratio output of an upper bridge arm of the first bridge arm through a PWM1 signal, the control module controls 100% duty ratio output of an upper bridge arm of the second bridge arm through a PWM4 signal, and the control module drives the charging module to charge through the drive module. The circuit solves the problem that the four-switch buck-boost converter cannot realize 100% duty cycle driving of an upper bridge arm.
Description
Technical Field
The invention relates to the technical field of power supplies, in particular to a bootstrap drive circuit applied to a four-switch buck-boost converter.
Background
In the four-switch buck-boost converter, the driving of the upper bridge arm switch tube needs to be realized through a bootstrap booster circuit.
As shown in fig. 1, in a conventional bootstrap boost circuit, NMOS transistors Q1 and Q2 constitute upper and lower switching transistors of the same bridge arm, and driving signals of the upper switching transistor Q1 and the lower switching transistor Q2 are in a complementary relationship. When Q2 is turned on, Q1 is turned off, the input voltage Vin charges a bootstrap capacitor C1 through a diode D1, and at the moment, the Vboot voltage, namely the voltage across the capacitor C1, is Vin-Vf (Vf is the forward conduction voltage drop of a diode D1); when Q2 is turned off, controller U1 sends a PWM signal to drive Q1 to turn on, Vboot provides a driving voltage to Q1, and as the turn-on voltage drop of Q1 continuously decreases, the source voltage of Q1 continuously increases, the Vboot voltage also continuously increases, and when Q1 is completely turned on, Vboot becomes 2 Vin-Vf, and the whole process is called a bootstrap boosting process.
In order to maintain the voltage across the bootstrap capacitor, the lower switch Q2 must be turned on for a sufficient time for Vin to charge the bootstrap capacitor C1 through the diode D1. Therefore, under the condition that the four-switch buck-boost converter works in a pure buck mode or a pure boost mode, the upper bridge arm cannot be driven to have 100% duty ratio, and therefore the efficiency of the system is affected.
Disclosure of Invention
The embodiment of the invention provides a bootstrap drive circuit applied to a four-switch buck-boost converter, and solves the problem that the four-switch buck-boost converter cannot realize 100% duty cycle drive of an upper bridge arm.
The embodiment of the invention discloses the following technical scheme:
the invention provides a bootstrap drive circuit applied to a four-switch buck-boost converter, which comprises a first bridge arm and a second bridge arm which are connected through an inductor, wherein the first bridge arm and the second bridge arm are used for switching buck, buck-boost or boost working modes of the circuit, the circuit further comprises a control module, a drive module and a charging module, the control module controls 100% duty ratio output of an upper bridge arm of the first bridge arm through a PWM1 signal, the control module controls 100% duty ratio output of an upper bridge arm of the second bridge arm through a PWM4 signal, and the control module drives the charging module to charge through the drive module.
Further, the driving module comprises a first driving switch, a second driving switch and a third driving switch, when the PWM5 signal is at a high level, the first driving switch controls the second driving switch to be turned off and controls the third driving switch to be turned on, the input voltage Vin is charged once through the charging module, when the PWM5 signal is at a low level, the first driving switch controls the second driving switch to be turned on and controls the third driving switch to be turned off, and the input voltage Vin is charged twice through the charging module.
Further, the first driving switch is an NMOS transistor Q7, the second driving switch is an NMOS transistor Q6, the third driving switch is a PNP triode Q5, the gate of the NMOS transistor Q7 is connected to one end of a resistor R1, the other end of the resistor R1 is connected to the PWM5 signal of the control module, the drain of the NMOS transistor Q7 is connected to the gate of the NMOS transistor Q6, the source of the NMOS transistor Q7 is grounded, the drain of the NMOS transistor Q6 is connected to the gate of the NMOS transistor Q6 through a resistor R3, the gate of the NMOS transistor Q6 is connected to the base of the PNP triode Q5 through a resistor R4, the source of the NMOS transistor Q6 is connected to the emitter of the PNP triode Q5, and the collector of the PNP triode Q5 is grounded;
when the circuit works in a buck mode or a buck-boost mode, the PWM5 signal is at a low level, and the driving module does not control the charging module;
the circuit works in a boost mode, when a PWM5 signal is at a high level, an NMOS tube Q7 is conducted, an NMOS tube Q6 is closed, a PNP type triode Q5 is conducted, an input voltage Vin is charged for one time through a charging module, when the PWM5 signal is at a low level, an NMOS tube Q7 is closed, a PNP type triode Q5 is closed, an NMOS tube Q6 is conducted, and the input voltage Vin is charged for the second time through the charging module.
Further, the charging module includes a first bootstrap capacitor C1 and a second bootstrap capacitor C2, the input voltage Vin is connected to one end of the second bootstrap capacitor C2 and the anode of the diode D1 through a diode D2, the other end of the second bootstrap capacitor C2 is connected to the emitter of the PNP transistor Q5, the cathode of the diode D1 is connected to one end of the first bootstrap capacitor C1, the other end of the first bootstrap capacitor C1 is connected to the first bridge arm, and one end of the first bootstrap capacitor C1 is used as a Vboot voltage to provide the operating voltage to the control module;
when the circuit works in buck mode or buck-boost mode, the PWM5 signal is at low level, and the input voltage Vin charges the first bootstrap capacitor C1 through the diode D2 and the diode D1;
the circuit works in a boost mode, when a PWM5 signal is in a high level, an input voltage Vin forms a loop through a diode D2, a second bootstrap capacitor C2, a PN junction of an emitter and a base of a PNP triode Q5 and a resistor R4, base current of the PNP triode Q5 is amplified and then charges a second bootstrap capacitor C2, when the PWM5 signal is in a low level, an NMOS tube Q6 is conducted, reference voltage of a second bootstrap capacitor C2 is increased, and the second bootstrap capacitor C2 charges a first bootstrap capacitor C1.
Further, the first bridge arm comprises an NMOS transistor Q1 and an NMOS transistor Q2, the NMOS transistor Q1 serves as an upper bridge arm of the first bridge arm, a drain of the NMOS transistor Q1 is connected with the input voltage Vin, a gate of the NMOS transistor Q1 is connected with a PWM1 signal of the control module, a source of the NMOS transistor Q1 is connected with a drain of the NMOS transistor Q2, a gate of the NMOS transistor Q2 is connected with a PWM2 signal of the control module, and a source of the NMOS transistor Q2 is grounded;
when the circuit works in the buck mode or the buck-boost mode, the NMOS tube Q1 and the NMOS tube Q2 are alternately switched on, the NMOS tube Q4 is switched on for a long time, the NMOS tube Q3 is switched off for a long time, and the NMOS tube Q4 serving as an upper bridge arm of the second bridge arm outputs at a duty ratio of 100%.
Further, the second bridge arm comprises an NMOS transistor Q3 and an NMOS transistor Q4, the NMOS transistor Q4 serves as an upper bridge arm of the second bridge arm, a drain of the NMOS transistor Q4 is connected to the output voltage Vout, a gate of the NMOS transistor Q4 is connected to a PWM4 signal of the control module, a source of the NMOS transistor Q4 is connected to a drain of the NMOS transistor Q3, a gate of the NMOS transistor Q3 is connected to a PWM3 signal of the control module, a source of the NMOS transistor Q3 is grounded, a source of the NMOS transistor Q1 is connected to the other end of the first bootstrap capacitor C1, and a source of the NMOS transistor Q1 is connected to a source of the NMOS transistor Q4 through an inductor L1;
when the circuit works in a boost mode, the NMOS tube Q3 and the NMOS tube Q4 are alternately conducted, the NMOS tube Q1 is in long conduction, the NMOS tube Q2 is in long disconnection, and the NMOS tube Q1 serving as an upper bridge arm of the first bridge arm outputs at a duty ratio of 100%.
Further, the control module comprises a controller and a switch control unit, wherein PWM' 1-5 signals of the controller sequentially generate PWM1-5 signals through the switch control unit, and PWM1-5 signals are sequentially connected with the gates of NMOS transistors Q1, Q2, Q3, Q4 and Q7 in a one-to-one mode;
when the circuit works in a buck mode or a buck-boost mode, the controller controls the duty ratio of PWM1-4 through the switch control unit, so that the NMOS tube Q1 and the NMOS tube Q2 are alternately switched on, the NMOS tube Q4 is switched on for a long time, and the NMOS tube Q3 is switched off for a long time;
when the circuit works in a boost mode, the controller controls the duty ratio of PWM1-4 through the switch control unit, so that the NMOS tube Q3 and the NMOS tube Q4 are alternately switched on, the NMOS tube Q1 is switched on for a long time, and the NMOS tube Q2 is switched off for a long time.
Further, the voltage Vboot provides an operating voltage for the switch control unit.
Furthermore, the model of the NMOS tube Q1-Q4 is BSC050N03LS, the model of the NMOS tube Q6 and the model of the NMOS tube Q7 are 2N7002, and the model of the PNP triode Q5 is LMBT3906LT 1G.
Further, the model of the switch control unit is UCC 27282.
The effect provided in the summary of the invention is only the effect of the embodiment, not all the effects of the invention, and one of the above technical solutions has the following advantages or beneficial effects:
according to the bootstrap drive circuit applied to the four-switch buck-boost converter, the controller controls the duty ratio of the PWM1-4 signal through the switch control unit, the on-off time of the NMOS tubes Q1-Q4 is adjusted, and the controller drives the charging module to charge through the PWM5 signal drive module. The circuit provided by the invention realizes that when the circuit works in buck mode or buck-boost mode, the controller controls the upper bridge arm of the second bridge arm to output at 100% duty ratio, and when the circuit works in boost mode, the controller controls the upper bridge arm of the first bridge arm to output at 100% duty ratio, thereby effectively improving the conversion efficiency of the converter.
Drawings
In order to more clearly illustrate the embodiments or technical solutions in the prior art of the present invention, the drawings used in the description of the embodiments or prior art will be briefly described below, and it is obvious for those skilled in the art that other drawings can be obtained based on these drawings without creative efforts.
FIG. 1 is a schematic diagram of a conventional bootstrap boost circuit in accordance with the present invention;
FIG. 2 is a block diagram of the circuit of the present invention;
FIG. 3 is a block diagram of a control module according to the present invention;
FIG. 4 is a schematic diagram of a circuit according to an embodiment of the present invention;
FIG. 5 is a flow chart of the method of the present invention.
Detailed Description
In order to clearly explain the technical features of the present invention, the following detailed description of the present invention is provided with reference to the accompanying drawings. The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. To simplify the disclosure of the present invention, the components and arrangements of specific examples are described below. Furthermore, the present invention may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. It should be noted that the components illustrated in the figures are not necessarily drawn to scale. Descriptions of well-known components and processing techniques and procedures are omitted so as to not unnecessarily limit the invention.
A Boost converter: the single-tube non-isolated direct current converter is also called a boost converter, and is a single-tube non-isolated direct current converter with output voltage higher than input voltage. Buck/Boost converter: the buck-boost converter is a single-tube non-isolated direct current converter with output voltage lower or higher than input voltage, but the polarity of the output voltage is opposite to that of the input voltage. The Buck/Boost converter can be regarded as a Buck converter and a Boost converter which are connected in series and combined with a switching tube.
As shown in fig. 2, a structural block diagram of the circuit of the present invention includes a first bridge arm and a second bridge arm connected through an inductor, where the first bridge arm and the second bridge arm are used to switch buck, buck-boost or boost operating modes of the circuit, the circuit further includes a control module, a driving module, and a charging module, the control module controls 100% duty cycle output of an upper bridge arm of the first bridge arm through a PWM1 signal, the control module controls 100% duty cycle output of an upper bridge arm of the second bridge arm through a PWM4 signal, and the control module drives the charging module to charge through the driving module.
As shown IN fig. 4, which is a schematic diagram of a circuit according to an embodiment of the present invention, IN the circuit, the model of the diode D1 and the model of the diode D2 are IN4147, the model of the NMOS transistors Q1 to Q4 are BSC050N03LS, the model of the NMOS transistors Q6 and Q7 are 2N7002, and the model of the PNP triode Q5 is LMBT3906LT 1G.
The driving module comprises a first driving switch, a second driving switch and a third driving switch, when the PWM5 signal is at a high level, the first driving switch controls the second driving switch to be closed and controls the third driving switch to be opened, the input voltage Vin is charged once through the charging module, when the PWM5 signal is at a low level, the first driving switch controls the second driving switch to be opened and controls the third driving switch to be closed, and the input voltage Vin is charged twice through the charging module.
The first driving switch is an NMOS tube Q7, the second driving switch is an NMOS tube Q6, the third driving switch is a PNP type triode Q5, the grid electrode of the NMOS tube Q7 is connected with one end of a resistor R1, the other end of the resistor R1 is connected with a PWM5 signal of the control module, the drain electrode of the NMOS tube Q7 is connected with the grid electrode of the NMOS tube Q6, the source electrode of the NMOS tube Q7 is grounded, the drain electrode of the NMOS tube Q6 is connected with the grid electrode of the NMOS tube Q6 through a resistor R3, the grid electrode of the NMOS tube Q6 is connected with the base electrode of the PNP type triode Q5 through a resistor R4, the source electrode of the NMOS tube Q6 is connected with the emitter electrode of the PNP type triode Q5, and the collector electrode of the PNP type triode Q5 is grounded.
When the circuit works in the buck mode or the buck-boost mode, the PWM5 signal is at a low level, and the driving module does not control the charging module; the circuit works in a boost mode, when a PWM5 signal is at a high level, an NMOS tube Q7 is conducted, an NMOS tube Q6 is closed, a PNP type triode Q5 is conducted, an input voltage Vin is charged for one time through a charging module, when a PWM5 signal is at a low level, an NMOS tube Q7 is closed, a PNP type triode Q5 is closed, an NMOS tube Q6 is conducted, and the input voltage Vin is charged for the second time through the charging module.
The charging module comprises a first bootstrap capacitor C1 and a second bootstrap capacitor C2, an input voltage Vin is connected with one end of the second bootstrap capacitor C2 and the anode of a diode D1 through a diode D2, the other end of the second bootstrap capacitor C2 is connected with the emitter of a PNP type triode Q5, the cathode of the diode D1 is connected with one end of the first bootstrap capacitor C1, the other end of the first bootstrap capacitor C1 is connected with a first bridge arm, and one end of the first bootstrap capacitor C1 is used as a Vboost voltage to provide working voltage for the control module.
When the circuit works in buck mode or buck-boost mode, the PWM5 signal is at low level, and the input voltage Vin charges the first bootstrap capacitor C1 through the diode D2 and the diode D1; when the PWM5 signal is at high level, the input voltage Vin forms a loop through the diode D2, the second bootstrap capacitor C2, the PN junction of the emitter and the base of the PNP triode Q5, and the resistor R4, the base current of the PNP triode Q5 is amplified and then charges the second bootstrap capacitor C2, when the PWM5 signal is at low level, the NMOS tube Q6 is turned on, the reference voltage of the second bootstrap capacitor C2 is increased, and the second bootstrap capacitor C2 charges the first bootstrap capacitor C1.
The first bridge arm comprises an NMOS tube Q1 and an NMOS tube Q2, the NMOS tube Q1 is used as an upper bridge arm of the first bridge arm, the drain electrode of the NMOS tube Q1 is connected with an input voltage Vin, the grid electrode of the NMOS tube Q1 is connected with a PWM1 signal of the control module, the source electrode of the NMOS tube Q1 is connected with the drain electrode of the NMOS tube Q2, the grid electrode of the NMOS tube Q2 is connected with a PWM2 signal of the control module, and the source electrode of the NMOS tube Q2 is grounded.
The second bridge arm comprises an NMOS tube Q3 and an NMOS tube Q4, the NMOS tube Q4 is used as an upper bridge arm of the second bridge arm, the drain electrode of the NMOS tube Q4 is connected with the output voltage Vout, the grid electrode of the NMOS tube Q4 is connected with the PWM4 signal of the control module, the source electrode of the NMOS tube Q4 is connected with the drain electrode of the NMOS tube Q3, the grid electrode of the NMOS tube Q3 is connected with the PWM3 signal of the control module, the source electrode of the NMOS tube Q3 is grounded, the source electrode of the NMOS tube Q1 is connected with the other end of the first bootstrap capacitor C1, and the source electrode of the NMOS tube Q1 is connected with the source electrode of the NMOS tube Q4 through an inductor L1.
When the circuit works in a buck mode or a buck-boost mode, the NMOS tube Q1 and the NMOS tube Q2 are alternately switched on, the NMOS tube Q4 is switched on for a long time, the NMOS tube Q3 is switched off for a long time, and the NMOS tube Q4 serving as an upper bridge arm of the second bridge arm outputs at a duty ratio of 100%; when the circuit works in a boost mode, the NMOS tube Q3 and the NMOS tube Q4 are alternately conducted, the NMOS tube Q1 is in long conduction, the NMOS tube Q2 is in long disconnection, and the NMOS tube Q1 serving as an upper bridge arm of the first bridge arm outputs at a duty ratio of 100%.
As shown in fig. 3, the control module of the present invention includes a controller and a switch control unit, wherein the PWM' 1-5 signal of the controller sequentially generates the PWM1-5 signal through the switch control unit, the PWM1-5 signal is sequentially connected with the gates of NMOS transistors Q1, Q2, Q3, Q4, and Q7 in a one-to-one manner, and the Vboot voltage provides the operating voltage for the switch control unit.
The model of the switch control unit is UCC27282, and UCC27282 is a strong N-channel MOSFET driver, and the maximum switch node (HS) voltage is 100V. It allows the control of two N-channel MOSFETs in a half-bridge or synchronous architecture configuration based topology. Its 3.5A peak sink current and 2.5A peak source current have low pull-up and pull-down resistances, enabling UCC27282 to drive a high power MOSFET with minimal switching losses during MOSFET miller platform switching. Since the input is independent of the supply voltage, the UCC27282 can be used with analog and digital controllers.
The input pin and HS pin of UCC27282 can withstand an ultra-large negative voltage, thereby improving the robustness of the system. Input interlocks further improve robustness and system reliability in high noise applications. The enable and disable functions respond to failure events in the system by reducing the power consumption of the driver, which increases the flexibility of the system. The 5V UVLO allows the system to operate at lower bias voltages, which is necessary in many high frequency applications and improves system efficiency in certain modes of operation. The smaller propagation delay and delay matching performance can minimize the requirement for dead time and further improve efficiency.
The UCC27282 provides an under-voltage lockout (UVLO) function for the high-side and low-side drivers, forcing the output low if the VDD voltage is below a specified threshold. The integrated bootstrap diode eliminates the need for an external discrete diode in many applications, saves circuit board space, and reduces system cost. The UCC27282 is in a small package, which enables high density design.
When the circuit works in the buck mode or the buck-boost mode, the controller controls the duty ratio of the PWM1-4 through the switch control unit, so that the NMOS transistor Q1 and the NMOS transistor Q2 are alternately switched on, the NMOS transistor Q4 is switched on for a long time, and the NMOS transistor Q3 is switched off for a long time. When the NMOS transistor Q2 is turned on, the input voltage Vin charges the first bootstrap capacitor C1 through the diode D2 and the diode D1, at this time, the Vboot voltage is Vin-2 × Vf (Vf is a forward conduction voltage drop of the diodes D1 and D2), when the NMOS transistor Q2 is turned off, the controller sends a PWM1 signal to drive the NMOS transistor Q1 to be turned on, Vboot provides a driving voltage to the switch control unit, the source voltage Vcom of the NMOS transistor Q1 is continuously increased along with the continuous decrease of the conduction voltage drop of the NMOS transistor Q1, the Vboot voltage is also continuously increased, when the NMOS transistor Q1 is completely turned on, the Vboot voltage is 2 Vin-2 Vf, and the first bootstrap capacitor C1 completes a bootstrap boosting process, so that the duty cycle driving of the NMOS transistor Q4100% is realized.
When the circuit works in buck or buck-boost mode, the NMOS tube Q1 and the NMOS tube Q2 are alternately conducted, the first bootstrap capacitor C1 automatically realizes bootstrap boosting through the on and off of the NMOS tube Q2, and therefore the controller can realize the duty ratio driving of the NMOS tube Q4100% without sending a PWM5 signal.
When the circuit works in the boost mode, the controller controls the duty ratio of the PWM1-4 through the switch control unit, so that the NMOS transistor Q3 and the NMOS transistor Q4 are alternately switched on, the NMOS transistor Q1 is switched on for a long time, and the NMOS transistor Q2 is switched off for a long time. The controller controls a PWM5 signal through the switch control unit, when the PWM5 signal is at a high level, the NMOS tube Q7 is conducted, the NMOS tube Q6 is closed, the PNP type triode Q5 is conducted, an input voltage Vin forms a loop through a diode D2, a second bootstrap capacitor C2, a PN junction of an emitter and a base of the PNP type triode Q5 and a resistor R4, a base current of the PNP type triode Q5 is amplified and then charges the second bootstrap capacitor C2, conduction voltage drop of the PNP type triode Q5 is ignored, and at the moment, voltage at two ends of the second bootstrap capacitor C2 is Vin-Vf. When the PWM5 signal is at a low level, the NMOS transistor Q7 is turned off, the gate voltage of the NMOS transistor Q6 is raised, so that the PNP transistor Q5 is forced to be turned off, and at the same time, the NMOS transistor Q6 is turned on, so that the reference voltage of the second bootstrap capacitor C2 is raised to Vcom, the second bootstrap capacitor C2 charges the first bootstrap capacitor C1, the Vboot voltage is charged to Vcom + Vin-2 Vf at the highest level, and the Vboot voltage is used as the driving voltage of the switch control unit, so that the bootstrap boosting process can be realized without turning on the NMOS transistor Q2, and the NMOS transistor Q1100% duty cycle driving is realized.
When the circuit works in a boost mode, the NMOS tube Q1 is continuously conducted, the drive of the NMOS tube Q1 depends on Vboost voltage, the Vboost voltage depends on the first bootstrap capacitor C1, the circuits of the NMOS tube Q7, the NMOS tube Q6 and the like and the PWM1-5 signal are conditions for realizing C1 bootstrap charging, and therefore the continuous conduction of the NMOS tube Q1 is required to be maintained, the traditional circuit cannot be achieved, and the method is adopted.
The voltage Vboot at the junction of the first bootstrap capacitor C1 and the cathode of the diode provides the operating voltage for the switch control unit.
As shown in fig. 5, a flowchart of the operation of the circuit of the present invention includes:
the first bridge arm receives an input voltage Vin, and the second bridge arm provides an output voltage Vout;
the controller switches the buck, buck-boost or boost working mode of the circuit through the first bridge arm and the second bridge arm;
when the circuit works in a buck mode or a buck-boost mode, the input voltage Vin charges the first bootstrap capacitor C1, and the controller controls the upper bridge arm of the second bridge arm to output at a 100% duty ratio;
when the circuit works in a boost mode, the controller drives the input voltage Vin to charge the first bootstrap capacitor C1 through the driving module, and the controller controls the upper bridge arm of the first bridge arm to output at a 100% duty ratio.
The controller switches the buck, buck-boost or boost working mode of the circuit through the first bridge arm and the second bridge arm, and specifically comprises the following steps:
the controller controls the duty ratio of PWM1-4 through the switch control unit, so that the NMOS tube Q1 and the NMOS tube Q2 are alternately switched on, the NMOS tube Q4 is switched on for a long time, the NMOS tube Q3 is switched off for a long time, and the circuit works in a buck mode or a buck-boost mode;
the controller controls the duty ratio of the PWM1-4 through the switch control unit, so that the NMOS tube Q3 and the NMOS tube Q4 are alternately switched on, the NMOS tube Q1 is switched on for a long time, the NMOS tube Q2 is switched off for a long time, and the circuit works in a boost mode.
When the circuit works in a buck mode or a buck-boost mode, the input voltage Vin charges the first bootstrap capacitor C1, and the controller controls the upper bridge arm of the second bridge arm to output at a 100% duty ratio, which specifically comprises:
when the NMOS transistor Q1 is turned off and the NMOS transistor Q2 is turned on, the input voltage Vin charges the first bootstrap capacitor C1 through the diode D2 and the diode D1;
when the NMOS transistor Q1 is turned on and the NMOS transistor Q2 is turned off, the reference voltage of the first bootstrap capacitor C1 connected with the source electrode of the NMOS transistor Q1 rises;
when the circuit is in the buck mode or the buck-boost mode, the NMOS transistor Q4 is in long conduction, the NMOS transistor Q3 is in long disconnection, and the output of the NMOS transistor Q4100% duty ratio is achieved.
When the circuit works in a boost mode, the controller drives the input voltage Vin to charge the first bootstrap capacitor C1 through the driving module, and the controller controls the upper bridge arm of the first bridge arm to output at a 100% duty ratio, which specifically comprises the following steps:
the controller controls the PWM1-5 signal through the switch control unit;
when the PWM5 signal is at a high level, the NMOS transistor Q7 and the PNP transistor Q5 are turned on, the NMOS transistor Q6 is turned off, the input voltage Vin forms a loop to the ground through the diode D2, the second bootstrap capacitor C2, the PN junction of the emitter and the base of the PNP transistor Q5, and the resistor R4, and the base current of the PNP transistor Q5 is amplified to charge the second bootstrap capacitor C2;
when the PWM5 signal is at a low level, the NMOS transistor Q7 and the PNP transistor Q5 are turned off, the NMOS transistor Q6 is turned on, the reference voltage of the second bootstrap capacitor C2 is raised, and the second bootstrap capacitor C2 charges the first bootstrap capacitor C1;
in a boost mode, the NMOS transistor Q3 and the NMOS transistor Q4 are alternately switched on, the NMOS transistor Q1 is switched on for a long time, and the NMOS transistor Q2 is switched off for a long time, so that the output of the NMOS transistor Q1100% duty ratio is realized.
The foregoing is only a preferred embodiment of the present invention, and it will be apparent to those skilled in the art that various modifications and improvements can be made without departing from the principle of the invention, and such modifications and improvements are also considered to be within the scope of the invention.
Claims (8)
1. A bootstrap drive circuit applied to a four-switch buck-boost converter comprises a first bridge arm and a second bridge arm which are connected through an inductor, wherein two ends of the inductor are respectively connected with a midpoint of the first bridge arm and a midpoint of the second bridge arm, the first bridge arm and the second bridge arm are used for switching buck, buck-boost or boost working modes of the circuit, the bootstrap drive circuit is characterized by further comprising a control module, a drive module and a charging module, the control module controls output of an upper bridge arm of the first bridge arm through a PWM1 signal, the control module controls output of an upper bridge arm of the second bridge arm through a PWM4 signal, the control module drives the charging module through the drive module, and the charging module is used for charging the circuit;
the driving module comprises a first driving switch, a second driving switch and a third driving switch, the first driving switch is an NMOS (N-channel metal oxide semiconductor) transistor Q7, when a PWM (pulse-width modulation) 5 signal is at a high level, the first driving switch receives the PWM5 signal, the second driving switch is controlled to be turned off, the third driving switch is controlled to be turned on, the input voltage Vin is charged once through the charging module, when the PWM5 signal is at a low level, the first driving switch receives the PWM5 signal, the second driving switch is controlled to be turned on, the third driving switch is controlled to be turned off, and the input voltage Vin is charged for the second time through the charging module.
2. The bootstrap drive applied to four-switch buck-boost converter as claimed in claim 1
The circuit is characterized in that the second drive switch is an NMOS transistor Q6, the third drive switch is a PNP type triode Q5, the gate of the NMOS transistor Q7 is connected with one end of a resistor R1, the other end of the resistor R1 is connected with a PWM5 signal of the control module, the drain of the NMOS transistor Q7 is connected with the gate of the NMOS transistor Q6, the source of the NMOS transistor Q7 is grounded, the drain of the NMOS transistor Q6 is connected with the gate of the NMOS transistor Q6 through the resistor R3, the gate of the NMOS transistor Q6 is connected with the base of the PNP type triode Q5 through the resistor R4, the source of the NMOS transistor Q6 is connected with the emitter of the PNP type triode Q5, and the collector of the PNP type triode Q5 is grounded.
3. The bootstrap driving circuit for four-switch buck-boost converter as claimed in claim 2, wherein said charging module includes a first bootstrap capacitor C1 and a second bootstrap capacitor C2, the input voltage Vin is connected to one end of the second bootstrap capacitor C2 and the anode of the diode D1 through the diode D2,
the other end of the second bootstrap capacitor C2 is connected to an emitter of the PNP transistor Q5, a cathode of the diode D1 is connected to one end of the first bootstrap capacitor C1, the other end of the first bootstrap capacitor C1 is connected to a midpoint of the first bridge arm, and one end of the first bootstrap capacitor C1 is used as a Vboot voltage to provide a working voltage for the control module.
4. The bootstrap drive circuit applied to four-switch buck-boost converter according to claim 1, characterized in that, the first bridge arm includes NMOS transistor Q1 and NMOS transistor Q2, NMOS transistor Q1 is used as the upper bridge arm of the first bridge arm, the drain of NMOS transistor Q1 is connected to the input voltage Vin, the gate of NMOS transistor Q1 is connected to the PWM1 signal of the control module, the source of NMOS transistor Q1 is connected to the drain of NMOS transistor Q2, the connection point is the midpoint of the first bridge arm, the gate of NMOS transistor Q2 is connected to the PWM2 signal of the control module, and the source of NMOS transistor Q2 is grounded.
5. The bootstrap drive circuit applied to four-switch buck-boost converter as claimed in claim 4, wherein said second bridge arm includes NMOS transistor Q3 and NMOS transistor Q4, NMOS transistor Q4 is used as upper bridge arm of the second bridge arm, drain of NMOS transistor Q4 is connected to output voltage Vout, and NMOS transistor Q4
The gate of the transistor Q4 is connected to the PWM4 signal of the control module, the source of the NMOS transistor Q4 is connected to the drain of the NMOS transistor Q3, the connection point is the midpoint of the second arm, the gate of the NMOS transistor Q3 is connected to the PWM3 signal of the control module, the source of the NMOS transistor Q3 is grounded, the source of the NMOS transistor Q1 is connected to the other end of the first bootstrap capacitor C1, and the source of the NMOS transistor Q1 is connected to the source of the NMOS transistor Q4 through the inductor L1.
6. Bootstrap drive applied to four-switch buck-boost converter according to claim 5
The circuit is characterized in that the control module comprises a controller and a switch control unit, PWM' 1-5 signals of the controller sequentially generate PWM1-5 signals through the switch control unit, and PWM1-5 signals are sequentially connected with the grids of NMOS transistors Q1, Q2, Q3, Q4 and Q7 in a one-to-one mode.
7. The bootstrap drive circuit applied to four-switch buck-boost converter as claimed in claim 6, wherein said NMOS transistor Q1-Q4 is model BSC050N03LS, NMOS transistor Q6 and NMOS transistor Q7 are model 2N7002, PNP triode Q5 is model LMBT3906LT 1G.
8. The bootstrap drive applied to four-switch buck-boost converter as claimed in claim 7
The circuit is characterized in that the model of the switch control unit is UCC 27282.
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| CN114157177A (en) * | 2021-11-29 | 2022-03-08 | 苏州伟创电气科技股份有限公司 | Motor drive inverter device and bootstrap charging method, device and storage medium |
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| US5627460A (en) * | 1994-12-28 | 1997-05-06 | Unitrode Corporation | DC/DC converter having a bootstrapped high side driver |
| US7848125B2 (en) * | 2008-10-21 | 2010-12-07 | Texas Instruments Incorporated | Keep-alive for power stage with multiple switch nodes |
| US8174248B2 (en) * | 2009-05-16 | 2012-05-08 | Texas Instruments Incorporated | Systems and methods of bit stuffing pulse width modulation |
| US8502511B1 (en) * | 2013-01-03 | 2013-08-06 | Richtek Technology Corporation | Buck switching regulator |
| TWM472362U (en) * | 2013-08-07 | 2014-02-11 | Richtek Technology Corp | Buck switching regulator |
| CN103715886B (en) * | 2013-12-11 | 2017-01-11 | 矽力杰半导体技术(杭州)有限公司 | Four-switch buck/boost mode converter control method and control circuit |
| CN108616210B (en) * | 2018-04-20 | 2020-08-25 | 成都芯源系统有限公司 | Drive circuit, control circuit and bootstrap voltage refreshing method of switching converter |
| CN110460233B (en) * | 2019-07-30 | 2024-08-20 | 杭州士兰微电子股份有限公司 | Boost-buck converter and control method thereof |
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