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CN113223959B - Method for manufacturing compression joint type diode core - Google Patents

Method for manufacturing compression joint type diode core Download PDF

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CN113223959B
CN113223959B CN202110389795.XA CN202110389795A CN113223959B CN 113223959 B CN113223959 B CN 113223959B CN 202110389795 A CN202110389795 A CN 202110389795A CN 113223959 B CN113223959 B CN 113223959B
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aluminum
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tube core
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王民安
王日新
汪杏娟
郑春鸣
黄永辉
王志亮
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Huangshan Core Microelectronics Co ltd
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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D8/00Diodes
    • H10D8/01Manufacture or treatment
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/113Isolations within a component, i.e. internal isolations
    • H10D62/115Dielectric isolations, e.g. air gaps
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D8/00Diodes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838Bonding techniques
    • H01L2224/8384Sintering

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Abstract

The invention discloses a compression joint type diode core and a manufacturing method thereof, comprising the following steps: 1) preparing a diode diffusion sheet, 2) corroding a voltage tank, 3) depositing a polycrystalline silicon film or a silicon nitride film by the voltage tank, 4) passivating voltage tank glass, 5) etching to remove a passivation film of most of cathode surface and anode surface areas which do not need protection of the polycrystalline silicon film or the silicon nitride, 6) welding a chip and a molybdenum sheet, 7) evaporating aluminum on a cathode surface, 8) selectively corroding an aluminum layer on the cathode surface, and 9) microalloy on an aluminum layer. Further 10) single-side multilayer metallization of the molybdenum sheet on the anode surface of the tube core, and 11) coating of a third protective layer on the voltage slot. The chip is tested before welding, unqualified chips are removed, waste of molybdenum sheets and the like is avoided, and the unqualified chips are reused after being processed. The voltage slot adopts three-layer protection, so that the leakage current of the tube core tested under high-temperature dynamic conditions is reduced; the molybdenum sheet is protected by titanium-nickel-silver multilayer metal to prevent oxidation, so that the thermal resistance and the resistance are reduced, and the power consumption is reduced.

Description

一种压接式二极管管芯制作方法A method of manufacturing a crimped diode die

技术领域technical field

本发明涉及二极管管芯及制作方法,尤其是涉及一种压接式二极管管芯制作方法。属于半导体器件技术领域。The invention relates to a diode die and a manufacturing method, in particular to a method for manufacturing a crimping diode die. It belongs to the technical field of semiconductor devices.

背景技术Background technique

目前,现有技术是:压接式二层结构二极管管扩散片的制备:1)根据电参数的要求,选择N型硅片的电阻率及片厚,对硅单晶片双面扩N+,保留一面作阴极,然后去除另一面N+层,再扩P层形成阳极。2)再通过铝箔与钼片焊接。3)阴极经过蒸铝、铝微合金。4)磨正斜角、腐蚀正斜角,涂胶硅橡胶或聚酰亚胺等保护台面。现有工艺、流程存在有四点不足之处:1.报废的管芯钼片不能再利用。测试中电参数不合格管芯属于废品。而钼片因和芯片通过铝箔焊在一起的,经过磨正斜角、腐蚀正斜角后钼片的边沿已变形,几何尺寸与原钼片不相符,钼片跟随一起报废,造成生产成本升高。2.磨角工艺效率低。芯片和钼片焊接形成管芯后,需要逐片磨正斜角,生产效率低,磨正斜角占用芯片阴极面面积较大,引起通态压降大。3.管芯台面不能用低压化学气相淀积工艺(CVD)来淀积半绝缘多晶硅膜或氮化硅膜。管芯焊接后磨正负斜角腐蚀清洗后,不能在700-800℃高温下做低压化学气相淀积工艺(CVD)来做半绝缘多晶硅膜或氮化硅膜对正斜角进行钝化保护,原因是硅铝合金温度的熔点为577℃,芯片与钼片硬焊的温度是650℃左右,而后道制膜钝化正斜角的温度需要在700-800℃下进行,膜钝化温度高于焊接的温度,会造成阴极铝层、阳极P层的合金层在此高温下烧的过深,引起反向耐压降低报废。所以正斜角只能做一般的钝化膜保护,如聚酰亚胺、硅橡胶。此类绝缘保护材料难以阻挡多数离子杂质对正负斜角台面的沾污、侵蚀。因此在高温测试下,反向漏电流偏大,高温反偏特性不稳定,合格率低。4.管芯阳极面的钼片易氧化。管芯阳极面的钼片由于没有抗氧化的金属层,长时间存放,钼片表面会形成一层氧化层,该氧化层具有一定的热阻和电阻,增加功耗。At present, the existing technology is: the preparation of the pressure-connected two-layer structure diode tube diffusion sheet: 1) according to the requirements of the electrical parameters, select the resistivity and the sheet thickness of the N-type silicon wafer, and expand N+ on both sides of the silicon single wafer, and keep One side is used as the cathode, and then the N+ layer on the other side is removed, and then the P layer is expanded to form the anode. 2) Then weld the aluminum foil and the molybdenum sheet. 3) The cathode is steamed aluminum and aluminum microalloy. 4) Grinding the positive bevel, corroding the positive bevel, coating silicone rubber or polyimide to protect the table. There are four deficiencies in the existing technology and flow process: 1. The discarded tube core molybdenum sheets cannot be reused. Die cores with unqualified electrical parameters in the test are waste products. However, because the molybdenum sheet and the chip are welded together through aluminum foil, the edge of the molybdenum sheet has been deformed after grinding and corroding the positive bevel angle, and the geometric size does not match the original molybdenum sheet. The molybdenum sheet is scrapped together, resulting in an increase in production costs. high. 2. The efficiency of the angle grinding process is low. After the chip and the molybdenum sheet are welded to form a tube core, the bevel needs to be ground one by one, and the production efficiency is low. The bevel grinding occupies a large area of the cathode surface of the chip, causing a large on-state voltage drop. 3. Low pressure chemical vapor deposition (CVD) cannot be used to deposit semi-insulating polysilicon film or silicon nitride film on the mesa of the die. After the core is welded, the positive and negative bevels are corroded and cleaned, and the low-pressure chemical vapor deposition process (CVD) cannot be used at a high temperature of 700-800°C to make a semi-insulating polysilicon film or a silicon nitride film to passivate the positive bevel. The reason is that the melting point of silicon-aluminum alloy is 577°C, the brazing temperature of the chip and the molybdenum sheet is about 650°C, and the temperature of the passivation positive angle of the subsequent film formation needs to be carried out at 700-800°C, and the film passivation temperature If the temperature is higher than the welding temperature, the cathode aluminum layer and the alloy layer of the anode P layer will burn too deeply at this high temperature, causing the reverse withstand voltage to decrease and be scrapped. Therefore, the positive bevel can only be used for general passivation film protection, such as polyimide and silicone rubber. This type of insulating protection material is difficult to prevent most ionic impurities from staining and eroding the positive and negative beveled mesa. Therefore, under the high temperature test, the reverse leakage current is too large, the high temperature reverse bias characteristic is unstable, and the qualified rate is low. 4. The molybdenum sheet on the anode side of the tube core is easy to oxidize. Since the molybdenum sheet on the anode surface of the tube core has no anti-oxidation metal layer, an oxide layer will form on the surface of the molybdenum sheet after long-term storage. This oxide layer has a certain thermal resistance and electrical resistance, which increases power consumption.

中国专利申请201710649775.5公开了一种整流二极管芯片结构及其制备方法该整流二极管芯片结构包括长基区N,设置在长基区N上表面的N+层,设置在长基区N下表面的P和P+层,所述N+层向下延伸至P层设有电压槽,所述电压槽位于芯片的周边,为单边槽结构;在P层平面上设置有P型凸台,所述P型凸台位于电压槽的下方;所述P型凸台的宽度大于电压槽底部的宽度。所述电压槽斜边的长度大于N型基区的厚度,以利于耗尽层的展宽。由于阴极、阳极镀镍金。该芯片只能用于软焊接(400度℃以下),不能用于压接式器件中。因为压接式管芯是在600-700℃加入铝箔与钼片焊接,电极镍金层将会渗透入N+阴极和P层内部,导致芯片性能严重下降甚至损坏。Chinese patent application 201710649775.5 discloses a rectifier diode chip structure and its preparation method. The rectifier diode chip structure includes a long base region N, an N+ layer disposed on the upper surface of the long base region N, P and a layer disposed on the lower surface of the long base region N. The P+ layer, the N+ layer extends downwards to the P layer with a voltage groove, the voltage groove is located on the periphery of the chip, and is a single-sided groove structure; a P-type boss is arranged on the P-layer plane, and the P-type boss The platform is located below the voltage groove; the width of the P-type boss is greater than the width of the bottom of the voltage groove. The length of the hypotenuse of the voltage groove is greater than the thickness of the N-type base region, so as to facilitate the widening of the depletion layer. Because the cathode and anode are nickel-plated with gold. This chip can only be used for soft soldering (below 400°C), and cannot be used for press-fit devices. Because the crimp-type die is welded with aluminum foil and molybdenum sheet at 600-700°C, the nickel-gold electrode layer will penetrate into the N+ cathode and P layer, resulting in a serious decline in chip performance or even damage.

发明内容Contents of the invention

本发明的目的是针对以上现有技术不足之处,提供一种压接式二极管管芯及制作方法,提高产品电参数、降低生产成本、提高产品的合格率。The object of the present invention is to provide a crimped diode die and a manufacturing method to improve the electrical parameters of the product, reduce the production cost, and improve the qualified rate of the product, aiming at the above shortcomings of the prior art.

本发明为达到上述目的采用的技术方案是:一种压接式二极管管芯制作方法,先制成具有P型凸台、可承受反向耐压且表面未进行金属化的芯片,然后通过铝箔与钼片硬焊接;包括以下步骤:The technical solution adopted by the present invention to achieve the above purpose is: a method for manufacturing a crimped diode die, firstly making a chip with a P-shaped boss, capable of withstanding reverse pressure and without metallization on the surface, and then passing the aluminum foil Brazing with molybdenum sheet; includes the following steps:

1)制备二层结构二极管扩散片:根据电参数的要求,选择N型硅片的电阻率及片厚,双面扩N+;其中一面设置为阴极,阴极面预留电压槽区域;然后去除另一面N+,在其电压槽下方用激光打盲孔,然后扩P层阳极和P型凸台;去除硼、磷硅玻璃;清洗待用。1) Prepare a two-layer structure diode diffusion sheet: According to the requirements of electrical parameters, select the resistivity and thickness of the N-type silicon wafer, and expand N+ on both sides; one side is set as the cathode, and the voltage groove area is reserved on the cathode side; then remove the other On one side of N+, use a laser to drill a blind hole under the voltage groove, and then expand the P layer anode and P-type boss; remove boron and phosphosilicate glass; clean and set aside.

2)在阴极面涂光刻胶、按电压槽图案曝光、显影、腐蚀电压槽,腐蚀后冲洗去除光刻胶、烘干待用。2) Apply photoresist on the cathode surface, expose according to the voltage groove pattern, develop, corrode the voltage groove, rinse and remove the photoresist after etching, and dry for later use.

3)电压槽淀积半绝缘多晶硅膜或氮化硅膜,将腐蚀好的有电压槽结构的片子放在化学气相淀积设备中,淀积半绝缘多晶硅膜或氮化硅膜,按常规的制膜工艺操作,膜厚

Figure BDA0003016376830000031
3) The semi-insulating polysilicon film or silicon nitride film is deposited on the voltage tank, and the etched sheet with the voltage tank structure is placed in the chemical vapor deposition equipment, and the semi-insulating polysilicon film or silicon nitride film is deposited, according to the conventional Film making process operation, film thickness
Figure BDA0003016376830000031

4)电压槽玻璃钝化:将阴极面上电压槽已完成半绝缘多晶硅或氮化硅钝化膜区域再涂玻璃粉并进行钝化,形成玻璃钝化膜,钝化温度690-750℃,钝化时间30-60min;4) Glass passivation of the voltage tank: the semi-insulating polysilicon or silicon nitride passivation film area of the voltage tank on the cathode surface is coated with glass powder and then passivated to form a glass passivation film. The passivation temperature is 690-750°C. Passivation time 30-60min;

5)刻蚀去除不需要半绝缘多晶硅膜或氮化硅保护的大部分阴极面和阳极面区域的钝化膜:对电压槽进行玻璃钝化后,再涂覆光刻胶,按照阴极面的设计图案进行曝光显影,保留电压槽上的光刻胶;显影后用稀氢氟酸去除阴极面上残留的玻璃粉;再用混合酸腐蚀液刻蚀不需要的半绝缘多晶硅膜、或用等离子设备刻蚀去除氮化硅膜保护的大部分阴极面和阳极面整个区域的钝化膜,然后放置在硫酸中去除电压槽上的光刻胶。5) Etching and removing the passivation film on most of the cathode and anode areas that do not need semi-insulating polysilicon film or silicon nitride protection: after passivating the voltage tank, apply photoresist, according to the cathode surface Design the pattern for exposure and development, and keep the photoresist on the voltage slot; after development, use dilute hydrofluoric acid to remove the residual glass powder on the cathode surface; then use mixed acid etching solution to etch the unnecessary semi-insulating polysilicon film, or use plasma The equipment is etched to remove most of the cathode surface protected by the silicon nitride film and the passivation film on the entire area of the anode surface, and then placed in sulfuric acid to remove the photoresist on the voltage slot.

6)芯片与钼片的焊接:芯片与钼片焊接前,对芯片做测试,剔除不合格芯片。将芯片、铝箔、钼片重叠在一起在高真空烧结炉中在620-700℃、恒温10-20分钟下焊接,降温出炉。6) Welding of chip and molybdenum sheet: before welding the chip and molybdenum sheet, test the chip and reject unqualified chips. Stack chips, aluminum foil, and molybdenum sheets together and weld them in a high vacuum sintering furnace at 620-700°C and constant temperature for 10-20 minutes, then cool down and leave the furnace.

7)阴极面蒸铝:将焊接好的管芯放置在高真空镀膜或磁控溅射设备中,对阴极面进行蒸铝,铝层厚度不少于

Figure BDA0003016376830000032
7) Aluminum steaming on the cathode surface: place the welded tube core in a high-vacuum coating or magnetron sputtering equipment, and steam the cathode surface, and the thickness of the aluminum layer is not less than
Figure BDA0003016376830000032

8)阴极面铝层选择腐蚀:在阴极已有铝层的面上涂光刻胶、曝光显影去除电压槽上的光刻胶,然后用铝腐蚀液进行铝刻蚀,去除阴极面上的光刻胶保留阴极面上的铝层;8) Selective corrosion of the aluminum layer on the cathode surface: apply photoresist on the surface of the cathode with an existing aluminum layer, expose and develop to remove the photoresist on the voltage groove, and then perform aluminum etching with an aluminum corrosion solution to remove the photoresist on the cathode surface. The resist retains the aluminum layer on the cathode side;

9)铝层微合金:把阴极面铝层选择性腐蚀好的管芯放置在有氮气保护的合金炉中进行铝微合金,温度500-550℃,合金时间10-50min。9) Micro-alloying of the aluminum layer: Place the tube core that has been selectively corroded on the aluminum layer on the cathode surface in an alloy furnace protected by nitrogen gas for aluminum micro-alloying at a temperature of 500-550°C and an alloying time of 10-50 minutes.

进一步,还包括步骤10)管芯阳极面钼片单面多层金属化:将管芯阳极面钼片朝上放置在真空磁控溅射设备中或真空镀膜机中进行钛镍银多层金属化的溅射,厚度分别为钛

Figure BDA0003016376830000033
镍/>
Figure BDA0003016376830000034
银/>
Figure BDA0003016376830000035
并在温度400-450℃、时间为20-60min的下进行微合金。因为银层不易氧化,起到抗氧化作用。Further, it also includes step 10) single-sided multilayer metallization of the molybdenum sheet on the anode side of the tube core: placing the molybdenum sheet on the anode side of the tube core upwards in a vacuum magnetron sputtering device or in a vacuum coating machine for titanium-nickel-silver multilayer metallization oxidized sputtering, thicknesses were Ti
Figure BDA0003016376830000033
Nickel />
Figure BDA0003016376830000034
Silver />
Figure BDA0003016376830000035
And carry out microalloying at a temperature of 400-450° C. and a time of 20-60 minutes. Because the silver layer is not easy to oxidize, it acts as an anti-oxidant.

更进一步,还包括步骤11)电压槽进行涂覆第三保护层:对电压槽涂聚酰亚胺或涂硅橡胶进一步的钝化保护,防止碰撞造成损伤。Further, it also includes step 11) coating the voltage groove with a third protective layer: coating the voltage groove with polyimide or silicone rubber for further passivation protection to prevent damage caused by collision.

本发明的积极效果是:(1)采用先在硅单晶片上先形成二层结构并具有P型凸台二极管扩散片,然后制成可以承受反向耐压的芯片,在焊接前可以对芯片逐片测试(现有技术在焊接前,芯片不具备测试条件),先剔除掉不能承受反向耐压的芯片,对可以承受反向耐压的芯片再与钼片进行焊接,避免了钼片、化学试剂、人工的浪费,大大降低生产成本。(2)二极管芯片用腐蚀电压槽的工艺替代磨角工艺,在酸腐蚀机中一次芯片腐蚀数量达到100-300片(Φ30-60mm),比传统的逐片磨角工艺效率提高了几十倍,极大的提高了生产效率。(3)由于芯片和钼片通过焊接形成管芯,最终经过各项电参数测试少数不合格的管芯因未经过磨角、焊接后的腐蚀工序,钼片的几何尺寸未有改变,经过处理后完全可以再次利用,进一步降低了生产成本。(4)芯片电压槽由于采用了低压化学气相淀积(CVD)工艺对敏感的电压槽区域进行了第一次半绝缘多晶硅膜或氮化硅膜钝化和玻璃钝化膜的二次保护,有效的防止了多数离子杂质的污染、侵蚀,再采用聚酰亚胺和具有弹性的硅橡胶进行第三次保护,防止碰撞,显著降低了管芯在高温、动态下测试的漏电流,提高了在高温反偏下测试的稳定性和合格率。(5)二极管管芯阳极面的钼片采用了溅射或蒸发钛镍银多层金属保护,防止氧化,降低了热阻和电阻,减少了功耗。The positive effect of the present invention is: (1) adopt earlier to form two-layer structure and have P-type boss diode diffuser sheet on the silicon single chip, then make the chip that can bear reverse withstand voltage, before welding, chip can be Test piece by piece (in the prior art, the chip does not have the test conditions before welding), first remove the chip that cannot withstand the reverse withstand voltage, and then weld the chip that can withstand the reverse withstand voltage with the molybdenum sheet to avoid the molybdenum sheet , chemical reagents, artificial waste, greatly reducing production costs. (2) Diode chips use the process of corroding the voltage groove instead of the grinding process. In the acid etching machine, the number of chips etched at one time reaches 100-300 pieces (Φ30-60mm), which is dozens of times more efficient than the traditional piece-by-piece grinding process. , greatly improving production efficiency. (3) Since the chip and the molybdenum sheet are welded to form a tube core, a small number of unqualified tube cores after various electrical parameter tests have not undergone grinding and corrosion after welding, and the geometric dimensions of the molybdenum sheet have not changed. After that, it can be reused completely, which further reduces the production cost. (4) The chip voltage tank is protected by the first semi-insulating polysilicon film or silicon nitride film passivation and the second protection of the glass passivation film on the sensitive voltage tank area by using a low-pressure chemical vapor deposition (CVD) process. It effectively prevents the pollution and erosion of most ionic impurities, and then uses polyimide and elastic silicone rubber for the third protection to prevent collisions, significantly reducing the leakage current of the die under high temperature and dynamic testing, and improving the The stability and pass rate of the test under high temperature reverse bias. (5) The molybdenum sheet on the anode surface of the diode core is protected by sputtering or evaporating titanium-nickel-silver multi-layer metal to prevent oxidation, reduce thermal resistance and electrical resistance, and reduce power consumption.

以下将结合附图和实施例,对本发明进行较为详细的说明。The present invention will be described in detail below with reference to the accompanying drawings and embodiments.

附图说明Description of drawings

图1为本发明压接式管芯剖视构造示意图。FIG. 1 is a schematic diagram of a cross-sectional structure of a crimping die according to the present invention.

图中:1.阳极、2.N型基区、3.阴极、4.铝层、5.电压槽、6.半绝缘多晶硅膜、7.玻璃钝化膜、8.硅橡胶、9.P型凸台、10.激光盲孔、11.钼片、12.多金属化层、13.铝箔。In the figure: 1. Anode, 2. N-type base area, 3. Cathode, 4. Aluminum layer, 5. Voltage tank, 6. Semi-insulating polysilicon film, 7. Glass passivation film, 8. Silicone rubber, 9. P Type boss, 10. Laser blind hole, 11. Molybdenum sheet, 12. Multi-metallization layer, 13. Aluminum foil.

具体实施方式Detailed ways

实施例1.如图1所示,一种压接式二极管管芯制作方法,先制成具有P型凸台(9)、可承受反向耐压且表面未进行金属化的芯片,然后通过铝箔(13)与钼片(11)硬焊接;包括以下步骤:Embodiment 1. As shown in Figure 1, a kind of method of making crimping type diode tube core, first make the chip that has P-type boss (9), can bear reverse withstand voltage and the surface is not carried out metallization, then pass Hard welding of aluminum foil (13) and molybdenum sheet (11); comprises the following steps:

1)制备二层结构二极管扩散片:根据电参数的要求,选择N型硅片的电阻率及片厚,双面扩N+扩散层;其中一面设置为阴极(3),阴极面预留电压槽区域;然后去除另一面N+,在其电压槽下方用激光打盲孔(10),然后扩P层阳极(1)和P型凸台(9);去除硼、磷硅玻璃;清洗待用。1) Prepare a two-layer structure diode diffusion sheet: According to the requirements of electrical parameters, select the resistivity and thickness of the N-type silicon wafer, and expand the N+ diffusion layer on both sides; one side is set as the cathode (3), and the cathode side is reserved for voltage slots area; then remove the N+ on the other side, drill a blind hole (10) with a laser below the voltage groove, and then expand the P layer anode (1) and P-type boss (9); remove boron and phosphosilicate glass; clean and set aside.

2)在阴极面涂光刻胶、按电压槽图案曝光、显影、腐蚀电压槽(5),腐蚀后冲洗去除光刻胶、烘干待用。具体是将二极管二层结构的扩散片进行涂光刻胶、曝光、显影出电压槽(5)所需腐蚀的区域,然后放置在混合酸腐蚀液中腐蚀,酸液温度为-10℃~12℃,时间5-20min,所述的混合酸腐蚀液,混合酸体积比为氢氟酸5份、冰乙酸4份、发烟硝酸2份、硝酸1份。2) Coating photoresist on the cathode surface, exposing according to the voltage groove pattern, developing, and corroding the voltage groove (5), rinsing and removing the photoresist after etching, and drying for later use. Specifically, the diffusion sheet with a two-layer structure of the diode is coated with photoresist, exposed, and developed to obtain the corroded area of the voltage groove (5), and then placed in a mixed acid etching solution for etching. The temperature of the acid solution is -10°C to 12°C. ℃, time 5-20min, the mixed acid etching solution, the mixed acid volume ratio is 5 parts of hydrofluoric acid, 4 parts of glacial acetic acid, 2 parts of fuming nitric acid, and 1 part of nitric acid.

3)电压槽淀积半绝缘多晶硅膜(6)或氮化硅膜,将腐蚀好的有电压槽结构的片子放在化学气相淀积设备中,淀积半绝缘多晶硅膜或氮化硅膜,按常规的制膜工艺操作,膜厚

Figure BDA0003016376830000051
半绝缘多晶硅膜制作工艺参数:气体为硅烷、一氧化二氮、氯化氢;氯化氢清洁工艺参数:温度炉口575℃、炉中575℃、炉尾575℃,清洁时间40min,清洁压力200-300毫托,清洁流量100-200ml/min;SIPOS沉积工艺参数:温度炉口640-660℃、炉中640-660℃、炉尾640-660℃;SIPOS先通硅烷淀积40S后,再SIPOS沉积30-45min;SIPOS沉积压力:300毫托,气体流量:N2O为50-80ml/min,SiH4为260-320m l/min;MTO温度为炉口600-670℃、炉中600-670℃、炉尾600-670℃;时间20-30min;致密化炉口700-800℃、炉中700-800℃、炉尾700-800℃,时间20-30min。3) Deposit a semi-insulating polysilicon film (6) or a silicon nitride film on the voltage tank, place the corroded sheet with a voltage tank structure in a chemical vapor deposition device, and deposit a semi-insulating polysilicon film or a silicon nitride film, According to the conventional film making process, the film thickness
Figure BDA0003016376830000051
Semi-insulating polysilicon film production process parameters: gas is silane, nitrous oxide, hydrogen chloride; hydrogen chloride cleaning process parameters: temperature furnace mouth 575 ℃, furnace 575 ℃, furnace tail 575 ℃, cleaning time 40min, cleaning pressure 200-300 mm Torr, cleaning flow rate 100-200ml/min; SIPOS deposition process parameters: temperature furnace mouth 640-660°C, furnace temperature 640-660°C, furnace tail 640-660°C; -45min; SIPOS deposition pressure: 300mTorr, gas flow: 50-80ml/min for N2O, 260-320ml/min for SiH4; MTO temperature is 600-670℃ at the furnace mouth, 600-670℃ in the furnace, 600-670°C; time 20-30min; densification furnace mouth 700-800°C, furnace 700-800°C, furnace tail 700-800°C, time 20-30min.

4)电压槽玻璃钝化:将阴极面上电压槽已完成半绝缘多晶硅或氮化硅钝化膜区域再涂玻璃粉并进行钝化,形成玻璃钝化膜(7),钝化温度690-750℃,钝化时间30-60min;4) Glass passivation of the voltage tank: the semi-insulating polysilicon or silicon nitride passivation film area of the voltage tank on the cathode surface is then coated with glass powder and passivated to form a glass passivation film (7). The passivation temperature is 690- 750℃, passivation time 30-60min;

5)刻蚀去除不需要半绝缘多晶硅膜或氮化硅保护的大部分阴极面和阳极面区域的钝化膜:对电压槽进行玻璃钝化后,再涂覆光刻胶,按照阴极面的设计图案进行曝光显影,保留电压槽上的光刻胶;显影后用稀氢氟酸去除阴极面上残留的玻璃粉;再用混合酸腐蚀液刻蚀不需要的半绝缘多晶硅膜、或用等离子设备刻蚀去除氮化硅膜保护的大部分阴极面和阳极面整个区域的钝化膜,然后放置在硫酸中去除电压槽上的光刻胶;所述的混合酸腐蚀液体积比为氢氟酸5份、冰乙酸4份、发烟硝酸2份、硝酸1份。5) Etching and removing the passivation film on most of the cathode and anode areas that do not need semi-insulating polysilicon film or silicon nitride protection: after passivating the voltage tank, apply photoresist, according to the cathode surface Design the pattern for exposure and development, and keep the photoresist on the voltage slot; after development, use dilute hydrofluoric acid to remove the residual glass powder on the cathode surface; then use mixed acid etching solution to etch the unnecessary semi-insulating polysilicon film, or use plasma The device etches to remove most of the passivation film on the cathode surface and the entire area of the anode surface protected by the silicon nitride film, and then places it in sulfuric acid to remove the photoresist on the voltage slot; the volume ratio of the mixed acid etching solution is hydrogen fluorine 5 parts of acid, 4 parts of glacial acetic acid, 2 parts of fuming nitric acid, and 1 part of nitric acid.

6)芯片与钼片的焊接:芯片与钼片焊接前,对芯片做测试,剔除不合格芯片。将芯片、铝箔、钼片重叠在一起在高真空烧结炉中在620-700℃、恒温10-20分钟下焊接,降温出炉。6) Welding of chip and molybdenum sheet: before welding the chip and molybdenum sheet, test the chip and reject unqualified chips. Stack chips, aluminum foil, and molybdenum sheets together and weld them in a high vacuum sintering furnace at 620-700°C and constant temperature for 10-20 minutes, then cool down and leave the furnace.

7)阴极面蒸铝:将焊接好的管芯放置在高真空镀膜或磁控溅射设备中,对阴极面进行蒸铝,铝层(4)厚度不少于

Figure BDA0003016376830000061
7) Aluminum steaming on the cathode surface: place the welded tube core in a high-vacuum coating or magnetron sputtering equipment, and steam aluminum on the cathode surface. The thickness of the aluminum layer (4) is not less than
Figure BDA0003016376830000061

8)阴极面铝层选择腐蚀:在阴极已有铝层的面上涂光刻胶、曝光显影去除电压槽上的光刻胶,然后用铝腐蚀液进行铝刻蚀,去除阴极面上的光刻胶保留阴极面上的铝层;所述的铝腐蚀液体积比,磷酸:冰乙酸:硝酸:水=76.58%:14.64%:3.94%:4.84%;温度60-70℃,腐蚀9-20min。8) Selective corrosion of the aluminum layer on the cathode surface: apply photoresist on the surface of the cathode with an existing aluminum layer, expose and develop to remove the photoresist on the voltage groove, and then perform aluminum etching with an aluminum corrosion solution to remove the photoresist on the cathode surface. The resist retains the aluminum layer on the cathode surface; the aluminum corrosion solution volume ratio, phosphoric acid: glacial acetic acid: nitric acid: water = 76.58%: 14.64%: 3.94%: 4.84%; temperature 60-70 ℃, corrosion 9-20min .

9)铝层微合金:把阴极面铝层选择性腐蚀好的管芯放置在有氮气保护的合金炉中进行铝微合金,温度500-550℃,合金时间10-50min。9) Micro-alloying of the aluminum layer: Place the tube core that has been selectively corroded on the aluminum layer on the cathode surface in an alloy furnace protected by nitrogen gas for aluminum micro-alloying at a temperature of 500-550°C and an alloying time of 10-50 minutes.

进一步,还包括步骤10)管芯阳极面钼片单面多层金属化:将管芯阳极面钼片朝上放置在真空磁控溅射设备中或真空镀膜机中进行钛镍银多层金属化的溅射,厚度分别为钛

Figure BDA0003016376830000062
镍/>
Figure BDA0003016376830000063
银/>
Figure BDA0003016376830000064
并在温度400-450℃、时间为20-60min的下进行微合金,形成多金属化层(12)。Further, it also includes step 10) single-sided multilayer metallization of the molybdenum sheet on the anode side of the tube core: placing the molybdenum sheet on the anode side of the tube core upwards in a vacuum magnetron sputtering device or in a vacuum coating machine for titanium-nickel-silver multilayer metallization oxidized sputtering, thicknesses were Ti
Figure BDA0003016376830000062
Nickel />
Figure BDA0003016376830000063
Silver />
Figure BDA0003016376830000064
And carry out microalloying at a temperature of 400-450° C. for 20-60 minutes to form a multi-metallization layer (12).

更进一步,还包括步骤11)电压槽进行涂覆第三保护层:对电压槽涂聚酰亚胺或涂硅橡胶(8)。Further, it also includes step 11) coating the voltage groove with a third protective layer: coating the voltage groove with polyimide or silicone rubber (8).

12)管芯测试入库。12) Die test storage.

本具体实施方案中具体的操作细节,是业内人士所知悉的工艺,不再赘述。但不影响实施方案的主体内容。The specific operation details in this specific embodiment are processes known to those in the industry and will not be repeated here. But it does not affect the main content of the implementation plan.

Claims (9)

1.一种压接式二极管管芯制作方法,先制成具有P型凸台(9)、可承受反向耐压且表面未进行金属化的芯片,然后通过铝箔(13)与钼片(11)硬焊接;包括以下步骤:1. A method for making a press-fit diode tube core, first making a chip with a P-type boss (9), which can withstand reverse voltage resistance and without metallization on the surface, and then pass aluminum foil (13) and molybdenum sheet ( 11) Brazing; including the following steps: 1)制备二层结构二极管扩散片:根据电参数的要求,选择N型硅片的电阻率及片厚,双面扩N+扩散层;其中一面设置为阴极(3),阴极面预留电压槽区域;然后去除另一面N+,在其电压槽下方用激光打盲孔(10),然后扩P层阳极(1)和P型凸台(9);去除硼、磷硅玻璃;清洗待用;1) Prepare a two-layer structure diode diffusion sheet: According to the requirements of electrical parameters, select the resistivity and thickness of the N-type silicon wafer, and expand the N+ diffusion layer on both sides; one side is set as the cathode (3), and the cathode side is reserved for voltage slots area; then remove the N+ on the other side, drill a blind hole (10) with a laser below the voltage groove, and then expand the P layer anode (1) and P-type boss (9); remove boron and phosphosilicate glass; clean and set aside; 2)在阴极面涂光刻胶、按电压槽图案曝光、显影、腐蚀电压槽(5),腐蚀后冲洗去除光刻胶、烘干待用;2) Coating photoresist on the cathode surface, exposing according to the voltage groove pattern, developing, and corroding the voltage groove (5), rinsing and removing the photoresist after etching, and drying for later use; 3)电压槽淀积半绝缘多晶硅膜(6)或氮化硅膜,将腐蚀好的有电压槽结构的片子放在化学气相淀积设备中,淀积半绝缘多晶硅膜或氮化硅膜,按常规的制膜工艺操作,膜厚
Figure FDA0003016376820000011
3) Deposit a semi-insulating polysilicon film (6) or a silicon nitride film on the voltage tank, place the corroded sheet with a voltage tank structure in a chemical vapor deposition device, and deposit a semi-insulating polysilicon film or a silicon nitride film, According to the conventional film making process, the film thickness
Figure FDA0003016376820000011
4)电压槽玻璃钝化:将阴极面上电压槽已完成半绝缘多晶硅或氮化硅钝化膜区域再涂玻璃粉并进行钝化,形成玻璃钝化膜(7),钝化温度690-750℃,钝化时间30-60min;4) Glass passivation of the voltage tank: the semi-insulating polysilicon or silicon nitride passivation film area of the voltage tank on the cathode surface is then coated with glass powder and passivated to form a glass passivation film (7). The passivation temperature is 690- 750℃, passivation time 30-60min; 5)刻蚀去除不需要半绝缘多晶硅膜或氮化硅保护的大部分阴极面和阳极面区域的钝化膜:对电压槽进行玻璃钝化后,再涂覆光刻胶,按照阴极面的设计图案进行曝光显影,保留电压槽上的光刻胶;显影后用稀氢氟酸去除阴极面上残留的玻璃粉;再用混合酸腐蚀液刻蚀不需要的半绝缘多晶硅膜、或用等离子设备刻蚀去除氮化硅膜保护的大部分阴极面和阳极面整个区域的钝化膜,然后放置在硫酸中去除电压槽上的光刻胶;5) Etching and removing the passivation film on most of the cathode and anode areas that do not need semi-insulating polysilicon film or silicon nitride protection: after passivating the voltage tank, apply photoresist, according to the cathode surface Design the pattern for exposure and development, and keep the photoresist on the voltage slot; after development, use dilute hydrofluoric acid to remove the residual glass powder on the cathode surface; then use mixed acid etching solution to etch the unnecessary semi-insulating polysilicon film, or use plasma The equipment is etched to remove most of the passivation film on the cathode side and the entire area of the anode side protected by the silicon nitride film, and then placed in sulfuric acid to remove the photoresist on the voltage slot; 6)芯片与钼片的焊接:将芯片、铝箔、钼片重叠在一起在高真空烧结炉中在620-700℃、恒温10-20分钟下焊接,降温出炉;6) Welding of chip and molybdenum sheet: stack the chip, aluminum foil, and molybdenum sheet together in a high-vacuum sintering furnace at 620-700°C and constant temperature for 10-20 minutes for welding, then cool down and leave the furnace; 7)阴极面蒸铝:将焊接好的管芯放置在高真空镀膜或磁控溅射设备中,对阴极面进行蒸铝,铝层(4)厚度不少于
Figure FDA0003016376820000012
7) Aluminum steaming on the cathode surface: place the welded tube core in a high-vacuum coating or magnetron sputtering equipment, and steam aluminum on the cathode surface. The thickness of the aluminum layer (4) is not less than
Figure FDA0003016376820000012
8)阴极面铝层选择腐蚀:在阴极已有铝层的面上涂光刻胶、曝光显影去除电压槽上的光刻胶,然后用铝腐蚀液进行铝刻蚀,去除阴极面上的光刻胶保留阴极面上的铝层;8) Selective corrosion of the aluminum layer on the cathode surface: apply photoresist on the surface of the cathode with an existing aluminum layer, expose and develop to remove the photoresist on the voltage groove, and then perform aluminum etching with an aluminum corrosion solution to remove the photoresist on the cathode surface. The resist retains the aluminum layer on the cathode side; 9)铝层微合金:把阴极面铝层选择性腐蚀好的管芯放置在有氮气保护的合金炉中进行铝微合金,温度500-550℃,合金时间10-50min。9) Micro-alloying of the aluminum layer: Place the tube core that has been selectively corroded on the aluminum layer on the cathode surface in an alloy furnace protected by nitrogen gas for aluminum micro-alloying at a temperature of 500-550°C and an alloying time of 10-50 minutes.
2.如权利要求1所述的压接式二极管管芯制作方法,其特征在于:还包括步骤10)管芯阳极面钼片设置多金属化层(12):将管芯阳极面钼片朝上放置在真空磁控溅射设备中或真空镀膜机中进行钛镍银多层金属化的溅射,厚度分别为钛
Figure FDA0003016376820000021
Figure FDA0003016376820000022
银/>
Figure FDA0003016376820000023
并在温度400-450℃、时间为20-60min的下进行微合金。
2. The manufacturing method of crimping type diode tube core as claimed in claim 1, it is characterized in that: also comprise step 10) tube core anode surface molybdenum sheet is provided with multi-metallization layer (12): the tube core anode surface molybdenum sheet faces Put it in the vacuum magnetron sputtering equipment or in the vacuum coating machine for sputtering of titanium-nickel-silver multi-layer metallization, the thickness is respectively titanium
Figure FDA0003016376820000021
nickel
Figure FDA0003016376820000022
Silver />
Figure FDA0003016376820000023
And carry out microalloying at a temperature of 400-450° C. and a time of 20-60 minutes.
3.如权利要求1或2所述的压接式二极管管芯制作方法,其特征在于:还包括步骤11)电压槽进行涂覆第三保护层:对电压槽涂聚酰亚胺或涂硅橡胶(8)。3. The manufacturing method of the crimping type diode tube core as claimed in claim 1 or 2, characterized in that: it also includes step 11) the voltage groove is coated with a third protective layer: the voltage groove is coated with polyimide or coated with silicon Rubber (8). 4.如权利要求1或2所述的压接式二极管管芯制作方法,其特征在于:所述的步骤2)是将二极管二层结构的扩散片进行涂光刻胶、曝光、显影出电压槽(5)所需腐蚀的区域,然后放置在混合酸腐蚀液中腐蚀,酸液温度为-10℃-10℃,时间5-20min,所述的混合酸腐蚀液,混合酸体积比为氢氟酸5份、冰乙酸4份、发烟硝酸2份、硝酸1份。4. The method for manufacturing a pressure-bonded diode die as claimed in claim 1 or 2, wherein in step 2) the diffusion sheet of the two-layer structure of the diode is coated with photoresist, exposed, and developed to produce a voltage The area to be corroded in the tank (5) is then placed in a mixed acid etching solution for corrosion, the temperature of the acid solution is -10°C-10°C, and the time is 5-20min. In the mixed acid etching solution, the volume ratio of the mixed acid is hydrogen 5 parts of hydrofluoric acid, 4 parts of glacial acetic acid, 2 parts of fuming nitric acid, and 1 part of nitric acid. 5.如权利要求1或2所述的压接式二极管管芯制作方法,其特征在于:所述的步骤3),半绝缘多晶硅膜制作工艺参数:气体为硅烷、一氧化二氮、氯化氢;氯化氢清洁工艺参数:温度炉口575℃、炉中575℃、炉尾575℃,清洁时间40min,清洁压力200-300毫托,清洁流量100-200ml/min;SIPOS沉积工艺参数:温度炉口640-660℃、炉中640-660℃、炉尾640-660℃;SIPOS先通硅烷淀积40S后,再SIPOS沉积30-45min;SIPOS沉积压力:300毫托,气体流量:N2O为50-80ml/min,SiH4为260-320ml/min;MTO温度为炉口600-670℃、炉中600-670℃、炉尾600-670℃;时间20-30min;致密化炉口700-800℃、炉中700-800℃、炉尾700-800℃,时间20-30min。5. as claimed in claim 1 or 2 described method for making crimping type diode tube core, it is characterized in that: described step 3), semi-insulating polysilicon film manufacturing process parameter: gas is silane, nitrous oxide, hydrogen chloride; Hydrogen chloride cleaning process parameters: temperature furnace mouth 575°C, furnace 575°C, furnace tail 575°C, cleaning time 40min, cleaning pressure 200-300 millitorr, cleaning flow rate 100-200ml/min; SIPOS deposition process parameters: temperature furnace mouth 640 -660°C, 640-660°C in the furnace, 640-660°C at the end of the furnace; SIPOS is first passed through silane deposition for 40S, and then SIPOS is deposited for 30-45min; SIPOS deposition pressure: 300 millitorr, gas flow: N2O is 50-80ml /min, SiH4 is 260-320ml/min; MTO temperature is furnace mouth 600-670℃, furnace 600-670℃, furnace tail 600-670℃; time 20-30min; densification furnace mouth 700-800℃, furnace Middle 700-800°C, furnace tail 700-800°C, time 20-30min. 6.如权利要求1或2所述的压接式二极管管芯制作方法,其特征在于:所述的步骤5)中所述的混合酸腐蚀液体积比为氢氟酸5份、冰乙酸4份、发烟硝酸2份、硝酸1份。6. The method for making a crimping diode tube core as claimed in claim 1 or 2, characterized in that: the volume ratio of the mixed acid etching solution described in the step 5) is 5 parts of hydrofluoric acid, 4 parts of glacial acetic acid 1 part, 2 parts of fuming nitric acid, 1 part of nitric acid. 7.如权利要求1或2所述的压接式二极管管芯制作方法,其特征在于:所述的步骤8)中,所述的铝腐蚀液体积比,磷酸:冰乙酸:硝酸:水=76.58%:14.64%:3.94%:4.84%;温度60-70℃,腐蚀9-20min。7. The manufacturing method of press-fit diode tube core as claimed in claim 1 or 2, characterized in that: in the described step 8), the volume ratio of the aluminum corrosion solution is phosphoric acid: glacial acetic acid: nitric acid: water = 76.58%: 14.64%: 3.94%: 4.84%; temperature 60-70 ℃, corrosion 9-20min. 8.如权利要求1或2所述的压接式二极管管芯制作方法,其特征在于:所述的步骤6)中,所述的芯片与钼片焊接前,对芯片做测试,剔除不合格芯片。8. The manufacturing method of press-fit diode tube core as claimed in claim 1 or 2, characterized in that: in the described step 6), before the described chip is welded with the molybdenum sheet, the chip is tested to remove unqualified chip. 9.如权利要求1所述的压接式二极管管芯,其特征在于:采用如权利要求1-8任一所述的压接式二极管管芯制备方法而成。9 . The crimping diode die according to claim 1 , characterized in that it is formed by the method for preparing the crimping diode die according to any one of claims 1-8. 10 .
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0541514A (en) * 1990-09-20 1993-02-19 Toshiba Corp Pressure-contact type semiconductor device
US6433370B1 (en) * 2000-02-10 2002-08-13 Vram Technologies, Llc Method and apparatus for cylindrical semiconductor diodes
JP2004288680A (en) * 2003-03-19 2004-10-14 Mitsubishi Electric Corp Pressure welding type semiconductor device
CN204011439U (en) * 2014-06-30 2014-12-10 常州佳盟电子科技有限公司 Point-contact diode
JP2016082105A (en) * 2014-10-17 2016-05-16 株式会社東芝 Semiconductor device

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100499172C (en) * 2004-11-30 2009-06-10 安徽省祁门县黄山电器有限责任公司 Rectifier diode, chip special for producing rectifier diode and producing method
JP5074093B2 (en) * 2007-05-11 2012-11-14 オンセミコンダクター・トレーディング・リミテッド Semiconductor device and manufacturing method thereof
CN101752248A (en) * 2009-12-18 2010-06-23 浙江四方电子有限公司 Thyristor core manufacturing process
CN103730430B (en) * 2013-12-16 2016-06-15 启东吉莱电子有限公司 A kind of table top large power semiconductor device multilayer complex films passivating structure and preparation technology thereof
JP2015177142A (en) * 2014-03-18 2015-10-05 株式会社日立製作所 Semiconductor device and power conversion device using the same
CN110890416A (en) * 2018-09-08 2020-03-17 安徽微半半导体科技有限公司 A composite inner passivation layer double trench structure high-power rectifier device application chip
CN109638083B (en) * 2018-12-29 2024-04-05 捷捷半导体有限公司 Fast recovery diode and preparation method thereof
CN209150121U (en) * 2018-12-29 2019-07-23 捷捷半导体有限公司 A kind of fast recovery diode

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0541514A (en) * 1990-09-20 1993-02-19 Toshiba Corp Pressure-contact type semiconductor device
US6433370B1 (en) * 2000-02-10 2002-08-13 Vram Technologies, Llc Method and apparatus for cylindrical semiconductor diodes
JP2004288680A (en) * 2003-03-19 2004-10-14 Mitsubishi Electric Corp Pressure welding type semiconductor device
CN204011439U (en) * 2014-06-30 2014-12-10 常州佳盟电子科技有限公司 Point-contact diode
JP2016082105A (en) * 2014-10-17 2016-05-16 株式会社東芝 Semiconductor device

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