CN113099236A - Encoding circuit, bit plane encoder, encoding method, encoding device, and medium - Google Patents
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Abstract
The embodiment of the application provides an encoding circuit, a bit plane encoder, an encoding method, encoding equipment and a medium. In some embodiments of the present application, after extracting data of multiple bit planes from data of an original image, bit plane coding is performed on the data of each bit plane in parallel by using multiple bit plane encoders, so as to obtain coded data corresponding to each bit plane; and finally, generating compressed image data of the original image according to the generated compressed code stream corresponding to each bit plane.
Description
Cross-referencing
This application is incorporated by reference into the present application, china patent application No. 201911337773.8 entitled "encoding circuit, bit plane encoder, encoding method, apparatus and medium", filed 2019, 12 and 23.
Technical Field
The present application relates to the field of image processing technologies, and in particular, to an encoding circuit, a bit plane encoder, an encoding method, an encoding device, and a medium.
Background
With the development of multimedia, image compression technology has gradually become a hot spot of research for more effectively storing various pictures. The JPEG2000 standard has a wide application prospect in various fields because it shows excellent performances such as a high compression ratio and high flexibility, and thus has been paid more and more attention by people and has become a hot spot for research and study.
Currently, the coding algorithm adopted by JPEG2000 is complex. EBCOT is the core part of JPEG2000 coding algorithm, which generates compressed code stream after entropy coding and code stream organization of quantized wavelet coefficient, and is the key of image compression; although the EBCOT as a core coding algorithm improves the compression performance, it is counted that when implemented in software, this part consumes more than 60% of the operation time of the whole coding algorithm. Therefore, the coding efficiency of the conventional JPEG2000 coding algorithm is low, and the image compression efficiency is affected.
Disclosure of Invention
Aspects of the present application provide an encoding circuit, a bit plane encoder, an encoding method, an apparatus, and a medium, the encoding circuit having a simple and compact structure and high encoding efficiency.
An embodiment of the present application provides an encoding circuit, including: the device comprises a bit plane data separation module, a plurality of bit plane encoders and a plurality of entropy encoders;
the bit plane data separation module is used for extracting data of a plurality of bit planes from data of an original image;
the bit plane encoders are connected with a bit plane data separation module and used for performing bit plane encoding on the data of the bit planes to obtain encoded data corresponding to the bit planes;
the plurality of entropy encoders are respectively connected with the plurality of bit plane encoders and are used for entropy encoding the encoded data corresponding to the plurality of bit planes respectively to obtain compressed code streams corresponding to the plurality of bit planes so as to generate compressed image data of the original image.
An embodiment of the present application further provides a bit plane encoder, including: the encoding mode prediction module and at least one encoding module;
the encoding mode prediction module is used for receiving data of a bit plane to be processed, predicting a target encoding mode which can be adopted by the data of the bit plane to be processed, and outputting an enable signal to the encoding module providing the target encoding mode;
and the at least one coding module is connected with the coding mode prediction module and is used for carrying out coding operation on the data of the bit plane to be processed when an enabling signal is received so as to generate the coded data corresponding to the bit plane to be processed.
The embodiment of the present application further provides an encoding method, which is applicable to an encoding circuit, and the method includes:
extracting data of a plurality of bit planes from data of an original image by using a bit plane data separation module in an encoding circuit;
carrying out bit plane coding on the data of the bit planes by utilizing a plurality of bit plane encoders in a coding circuit to obtain coded data corresponding to the bit planes respectively;
and entropy coding the coded data corresponding to the bit planes by utilizing a plurality of entropy coders connected with a plurality of bit plane coders in a coding circuit to obtain compressed code streams corresponding to the bit planes so as to generate compressed image data of the original image.
An embodiment of the present application further provides an encoding device, including: a memory and a processor;
the memory to store one or more computer instructions;
the processor to execute the one or more computer instructions to:
extracting data of a plurality of bit planes from data of an original image by using a bit plane data separation module in an encoding circuit;
carrying out bit plane coding on the data of the bit planes by utilizing a plurality of bit plane encoders in a coding circuit to obtain coded data corresponding to the bit planes respectively;
and entropy coding the coded data corresponding to the bit planes by utilizing a plurality of entropy coders connected with a plurality of bit plane coders in a coding circuit to obtain compressed code streams corresponding to the bit planes so as to generate compressed image data of the original image.
Embodiments of the present application also provide a computer-readable storage medium storing a computer program that, when executed by one or more processors, causes the one or more processors to perform actions comprising:
extracting data of a plurality of bit planes from the data of the original image by using a bit plane data separation module in the coding circuit;
carrying out bit plane coding on the data of the bit planes by utilizing a plurality of bit plane encoders in a coding circuit to obtain coded data corresponding to the bit planes respectively;
and entropy coding the coded data corresponding to the bit planes by utilizing a plurality of entropy coders connected with a plurality of bit plane coders in a coding circuit to obtain compressed code streams corresponding to the bit planes so as to generate compressed image data of the original image.
In some embodiments of the present application, after extracting data of multiple bit planes from data of an original image, bit plane coding is performed on the data of each bit plane in parallel by using multiple bit plane encoders, so as to obtain coded data corresponding to each bit plane; and finally, generating compressed image data of the original image according to the generated compressed code stream corresponding to each bit plane.
Drawings
The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the application and together with the description serve to explain the application and not to limit the application. In the drawings:
fig. 1 is a schematic structural diagram of an encoding circuit according to an exemplary embodiment of the present application;
fig. 2 is a schematic structural diagram of a bit plane data separation module according to an exemplary embodiment of the present disclosure;
FIG. 3 is a schematic diagram illustrating an overall structure of a bit-plane encoder according to an exemplary embodiment of the present application;
FIG. 4 is a circuit diagram of zero-coding modules LL, LH and HL sub-bands in accordance with an exemplary embodiment of the present application;
FIG. 5 is a circuit diagram of a zero coding module HH sub-band in accordance with an exemplary embodiment of the present application;
FIG. 6 is a circuit diagram of an amplitude refinement coding module provided in an exemplary embodiment of the present application;
FIG. 7 is a circuit diagram of a symbol encoding module provided in an exemplary embodiment of the present application;
fig. 8 is a circuit diagram of a run-length encoding module according to an exemplary embodiment of the present application;
FIG. 9 is a schematic diagram of a bit-plane encoder according to an exemplary embodiment of the present application;
fig. 10 is a flowchart illustrating an encoding method according to an exemplary embodiment of the present application;
fig. 11 is a schematic structural diagram of an encoding apparatus according to an exemplary embodiment of the present application.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the technical solutions of the present application will be described in detail and completely with reference to the following specific embodiments of the present application and the accompanying drawings. It should be apparent that the described embodiments are only some of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
At present, the JPEG2000 coding algorithm has low coding efficiency and influences the image compression efficiency. For the technical problem existing at present, in some embodiments of the present application, after data of multiple bit planes are extracted from data of an original image, bit plane coding is performed on the data of each bit plane in parallel by using multiple bit plane encoders, so as to obtain coded data corresponding to each bit plane; and finally, generating compressed image data of the original image according to the generated compressed code stream corresponding to each bit plane.
Currently, the EBCOT algorithm is divided into two parts: t1 part and T2 part. The T1 part encodes the data of the original image to generate a compressed code stream corresponding to each bit plane, and the T2 part completes the control and organization of the compressed code stream rate. The coding circuit provided by the embodiment of the application is mainly improved aiming at the T1 part.
The technical solutions provided by the embodiments of the present application are described in detail below with reference to the accompanying drawings.
Fig. 1 is a schematic structural diagram of an encoding circuit according to an exemplary embodiment of the present application. As shown in fig. 1, the encoding circuit includes a bit plane data separation module 11, a plurality of bit plane encoders 12, and a plurality of entropy encoders 13. A bit plane data bit plane separation module 111 for extracting data of a plurality of bit planes from data of an original image; the bit plane encoders 12 are connected to the bit plane data separation module 11, and configured to perform bit plane encoding on data of a plurality of bit planes to obtain encoded data corresponding to the plurality of bit planes; an entropy encoder 13 is connected to a bit plane encoder 12, and is configured to perform entropy encoding on encoded data corresponding to each of the plurality of bit planes to obtain compressed code streams corresponding to the plurality of bit planes, so as to generate compressed image data of the original image. The circuit structure of the coding circuit is simple and compact, the coding efficiency is high, and the image compression efficiency can be improved.
In this embodiment, a plurality of bit plane encoders 12 are connected in parallel to the output end of the bit plane data separation module 11, and perform bit plane encoding on the data of a plurality of bit planes to obtain encoded data corresponding to each of the plurality of bit planes; an entropy encoder 13 is connected in series behind each bit plane encoder 12, the entropy encoder 13 performs entropy encoding on the encoded data corresponding to each of the plurality of bit planes respectively to obtain compressed code streams corresponding to the plurality of bit planes, and the bit plane encoder 12 and the entropy encoder 13 which are connected in series are used for encoding a single bit plane respectively to improve the encoding efficiency of the graphic data.
In the above embodiment, the encoding circuit may further include the selector 14 and the compression processing module 15. The selector 14 is connected to the plurality of entropy encoders 13, and is configured to sort the compressed code streams corresponding to the plurality of bit planes and output the sorted compressed code streams; the compression processing module 15 is connected to the selector 14, and the compression processing module 15 layers the ordered compressed code streams according to the contribution to the quality of the restored image to generate compressed image data of the original image.
In the present embodiment, the data of the original image is wavelet-transformed data. The data of the original image may also be discrete cosine transformed data. The image data after the wavelet transform is stored in ram, and provides data support for the bit plane data separation module 11. For a 16-bit image, 16 bit planes can be used for representation, wherein the most significant bit plane stores the sign bits of the remaining bit planes, and therefore, for a 16-bit image, the data of 15 bit planes needs to be encoded.
In the present embodiment, the data of each bit plane includes: the sign bit of the bit plane, the magnitude of the bit plane, and the effective state variables of the bit plane.
Fig. 2 is a schematic structural diagram of a bit plane data separation module 11 according to an exemplary embodiment of the present application. As shown in fig. 2, the bit plane data bit plane separation module 111 includes: a bit plane separation module 111 and a valid state variable prediction module 112; the bit plane separation module 111 obtains the image data after the wavelet transform of the original image, and separates the sign bit of each bit plane and the amplitude of each bit plane from the image data after the wavelet transform; the effective state variable prediction module 112 is connected to the bit plane separation module 111, and is configured to obtain an effective state variable of each bit plane according to the amplitude of each bit plane.
In the above embodiment, the valid state variable prediction module 112 obtains the valid state variable of each bit plane according to the amplitude of each bit plane, and one achievable way is to perform or operation on the amplitudes of all the bit planes above the target bit plane and the corresponding positions of the designated positions to obtain the importance state variable of the designated position of the target bit plane; and the amplitude refinement state variable of the specified position of the target bit plane is the importance state variable of the corresponding position of the bit plane on the target bit plane. For example: the significance state variable σ for a given position [ m, n ] in the p-th layer bit plane is the or operation of the magnitudes of the corresponding positions of all bit planes above the p-th layer bit plane and the significance state variable of the highest layer bit plane is 0. The amplitude refinement state variable for a given position [ m, n ] in the bit plane of the p-th layer is the significance state variable for the corresponding position in the p + 1-th layer.
The significance state variable of the p-th layer bit plane is formulated as:
the amplitude refinement state variable formula of the p-th layer bit plane is as follows: e.g. of the typep＝σp+1。
Where σ denotes an effective state variable, e denotes an amplitude refinement state variable, p denotes the current layer number, v denotes the amplitude, and m, n denotes position information in the code block.
It can be seen from the above that the relationships between the bit planes are linked by the valid state variables, and the valid state variables of each coding point in each bit plane are pre-obtained, so that the data of each bit plane can be coded in a parallel manner.
Fig. 3 is a schematic diagram of an overall structure of a bit plane encoder 12 according to an exemplary embodiment of the present application. A plurality of bit plane encoders 12 are connected in parallel to the output end of the bit plane data bit plane separation module 111, as shown in fig. 3, the bit plane encoders 12 include an encoding mode prediction module and at least one encoding module; the coding mode prediction module is connected with the bit plane data separation module 11 and is used for predicting a target coding mode which can be adopted by data of each bit plane and outputting an enable signal to a coding module corresponding to the provided target coding mode; at least one coding module is respectively connected to the bit plane data separation module 11, and is configured to perform a coding operation on data of a target bit plane sent to the bit plane coder 12 to which the coding module belongs when receiving an enable signal, so as to generate coded data corresponding to the target bit plane. According to the embodiment of the application, the target coding mode which can be adopted by the data of each bit plane is predicted, and the four coding modes are coded simultaneously, so that the coding speed is improved.
The working principle of the encoding mode prediction module according to the embodiment of the present application is described with reference to fig. 3. As shown in fig. 3, the important encoding module includes a run-length encoding module, a zero encoding module, a sign encoding module, and an amplitude refinement encoding module. The neighborhood data of the current data to be coded comprises the previous data of the current data to be coded and the next data of the current data to be coded. For example, when the width of the coding slice is four, the current four data to be coded and the importance state variables of the domain data of the four data to be coded are input into the coding mode prediction module to predict the coding mode. The coding mode prediction module performs coding mode prediction as follows: if the importance state variables of the current data to be coded and the neighborhood data of the current data to be coded are both 0, determining the run coding mode as a target coding mode; if the importance states of the current data to be coded are all 0 and at least one of the importance state variables of the neighborhood data of the current data to be coded is not 0, determining a zero coding mode as a target coding mode; if the amplitude of the current data to be coded is 1, determining a symbol coding mode as a target coding mode; if the importance state variables of the current data to be coded are all 1, determining an amplitude refinement coding mode as a target coding mode; the current data to be encoded is part of the data to be encoded in the data of the target bit plane. And after the prediction of the primary coding mode is finished, setting all the enabling signals to be invalid. In the process of coding mode prediction, whether the coding mode prediction module works or not is determined by a control signal of the main control module, and after the main control module reads the next row of coded data, an enabling signal of the coding mode prediction module is set to be effective. It is obvious that the above coding mode prediction module can be implemented by using logic circuit or software.
The formula for the coding mode prediction by the coding mode prediction module is as follows:
mi＝σneigh
zc_eni＝(！vi)&mi
sc_eni＝vi&zc_eni
mrc_eni＝(！zc_eni)&σi
rlc_en＝！(m1+m2+m3+m4)
wherein m isiRepresenting a state variable of importance, v representing a magnitude, zc _ eniIndicating zero coding is active, sc _ eniIndicating that the symbol encoding is valid, mrc _ eniThe amplitude refinement coding is effective; rlc en indicates that run length coding is valid.
With reference to fig. 3, the following describes the encoding process of the run-length encoding module, the zero encoding module, the sign encoding module and the amplitude refinement encoding respectively:
FIG. 4 is a circuit diagram of zero-coding modules LL, LH and HL sub-bands in accordance with an exemplary embodiment of the present application; FIG. 5 is a circuit diagram of a zero coding module HH sub-band in accordance with an exemplary embodiment of the present application. Zero-coding operations are only possible when the data to be coded is not important per se. As shown in fig. 4 and 5, the zero encoding module includes a first summing circuit 201, a first context generator 203 and a first output circuit 202; the first summing circuit 201 is connected to the bit plane data separation module 11, and is configured to sum the state variables of importance of neighborhood data of each to-be-encoded data in the target bit plane data, to obtain a summing result corresponding to each to-be-encoded data; the first context generator 203 is connected to the first summation circuit 201, and is configured to obtain a context corresponding to a summation result of each to-be-encoded data from a mapping relationship between a pre-stored summation result and context information, so as to generate a context corresponding to a target bit plane; the first output circuit 202 is connected to the first context generator 203 and the encoding mode prediction module, and is configured to control the first output circuit 202 to output the encoded data corresponding to the target bit plane when receiving the enable signal sent by the encoding mode prediction module.
In the above embodiment of the present application, as shown in fig. 4, in the zero-coded LL, LH, and HL subbands, the first summing circuit 201 sums the importance state variables of the horizontal neighborhood, the vertical neighborhood, and the diagonal neighborhood of 8-bit neighborhood data to obtain a summation result; the first context generator 203 acquires a context corresponding to the summation result from a mapping relationship between the pre-stored summation result and the context information according to the summation result. A selection circuit is also included between the first summing circuit 201 and the first context generator 203 for operations that require interchanging the sum of the significance state variables of V and H during the encoding of the HL subband. When receiving the enable signal sent by the encoding method prediction module, the first output circuit 202 controls the first output circuit 202 to output the encoded data corresponding to the target bit plane.
In the above-described embodiment of the present application, as shown in fig. 5, in the zero-coded HH sub-band, the first summing circuit 201 sums the significance state variables of the horizontal neighborhood and the vertical neighborhood of the 8-bit neighborhood data to obtain a summation result; the first context generator 203 acquires a context corresponding to the summation result from a mapping relationship between the pre-stored summation result and the context information according to the summation result. When receiving the enable signal sent by the encoding method prediction module, the first output circuit 202 controls the first output circuit 202 to output the encoded data corresponding to the target bit plane.
In the above embodiment, the mapping relationship between the summation result and the context information is shown in the following table:
where H denotes the sum of the sample horizontal neighborhood significance state variables, V denotes the sum of the sample vertical neighborhood significance state variables, D denotes the sum of the four diagonal significance state variables of the sample, and X denotes disregard.
Fig. 6 is a circuit diagram of an amplitude refinement coding module according to an exemplary embodiment of the present application. As shown in fig. 6, the amplitude refinement encoding module includes a second context generator 301 and a second output circuit 302; the second context generator 301 is connected to the bit plane data separation module 11, and configured to perform a nor operation on a sum of importance state variables of neighborhood data of each to-be-encoded data in the target bit plane data, and combine the sum with a signal indicating whether to perform amplitude refinement encoding for the first time to obtain a context corresponding to each to-be-encoded data, so as to generate a context corresponding to the target bit plane; the second output circuit 302 is connected to the second context generator 301 and the encoding mode prediction module, and is configured to control the second output circuit 302 to output the encoded data corresponding to the target bit plane when receiving the enable signal sent by the encoding mode prediction module.
In the above embodiment of the present application, the sum of the significance state variables of the 8-bit neighborhood data is calculated by a nor gate, and then combined with whether to enter the signal at the sta _ s _ new end of the amplitude refinement coding for the first time to generate the context. The output of the overall coding is controlled by an enable signal, and the coding result is valid and output only when the MRC _ en terminal is valid. The mapping relationship between each to-be-coded data and the context is shown in the following table:
fig. 7 is a circuit diagram of a symbol encoding module according to an exemplary embodiment of the present application. The symbol encoding module comprises a signal acquisition circuit 401, a third context generator 402 and a third output circuit 403; the signal obtaining circuit 401 is connected to the bit plane data separation circuit, and is configured to generate all vertical contributions and all horizontal contributions corresponding to each to-be-encoded data according to the state variable of importance and the sign bit of the neighborhood data of each to-be-encoded data in the data of the target bit plane; the third context generator 402 is connected to the signal obtaining circuit 401, and configured to obtain a context corresponding to each to-be-encoded data from a mapping relationship between the vertical contribution and the encoded data and the horizontal contribution, so as to generate encoded data corresponding to a target bit plane; the third output circuit 403 is connected to the third context generator 402, and controls the third output circuit 403 to output the encoded data corresponding to the target bit plane when receiving the enable signal from the encoding scheme prediction module.
In the above-described embodiment of the present application, as shown in fig. 7, the signal acquisition circuit 401 generates all the vertical contributions and the horizontal contributions from the significance state variables and the sign bits of the horizontal domain and the vertical domain of the data to be encoded; a third context generator 402, for obtaining corresponding encoded data according to the mapping relationship between the vertical contribution and the horizontal contribution and the encoded data; the third output circuit 403 outputs correct encoded data when the symbol encoding is valid only when the SC _ en trigger is valid. Symbol encoding is entered immediately after zero encoding of data is performed when the data to be encoded becomes valid for the first time as the highest non-zero data. The states of the coefficients are represented by "1" for positive significance, "-1" for negative significance and "0" for non-significance, e.g. the magnitude at position H1 is 0, then the position contribution is 0 whether the sign of the position is positive or negative, and when the magnitude of this position is 1, the contribution is positive significance (1) when the sign is positive and negative significance (-1) when the sign is negative. The context indexes of symbol encoding are shown in tables 2-5. Xorabit denotes the inversion factor where H denotes the sign sum of the horizontal neighborhood coefficients and V denotes the vertical direction. If the H neighborhood coefficient is the sum of the sign coefficients of the valid neighborhoods, it is 0 if it is invalid. The mapping relationship between the vertical contribution and the horizontal contribution and the encoded data is shown as the following table:
fig. 8 is a circuit diagram of a run-length encoding module according to an exemplary embodiment of the present application. As shown in fig. 8, the run-length encoding module is configured to obtain encoded data corresponding to each to-be-encoded data from a mapping relationship between each to-be-encoded data and the encoded data, so as to generate and output encoded data corresponding to a target bit plane. If the four data to be encoded are not valid in this bit plane either, a decision of 0 for the output context 17 is made, and then the next set of data is encoded. If there is at least one data among the four data to be encoded that is valid in this bit plane, the context 17 and decision 1 are output first, and then the context 18 and the position information (00,01,10, and 11) of the first valid data are output as decisions together with the context 18, followed by sign encoding of the significant coefficients.
In order to improve the speed of the run length coding and facilitate the design of a hardware structure, the run length coding is simplified into a data table look-up process in the design, because the run length coding has 16 conditions in total, compared with the calculation, the complexity of a circuit can be simplified and the coding speed can be improved. Specific encoding methods are shown in tables 2-4, wherein x0, x1, x2 and x3 respectively represent sign bits corresponding to Data. The mapping relationship between the data to be encoded (input data) and the encoded data (output data) is shown in the following table:
in the embodiment of the encoding circuit of the present application, after extracting data of a plurality of bit planes from data of an original image, bit plane encoding is performed on the data of each bit plane in parallel by using a plurality of bit plane encoders 12, and encoded data corresponding to each bit plane is obtained; and entropy encoding the encoded data corresponding to each bit plane in parallel by using a plurality of entropy encoders 13 to obtain a compressed code stream corresponding to each bit plane, and finally generating compressed image data of the original image according to the generated compressed code stream corresponding to each bit plane.
Fig. 9 is a schematic structural diagram of a bit plane encoder 12 according to an exemplary embodiment of the present application. As shown in fig. 9, the bit plane encoder 12 according to the embodiment of the present application includes an encoding mode prediction module and at least one encoding module. The encoding mode prediction module is used for receiving the data of the bit plane to be processed, predicting a target encoding mode which can be adopted by the data of the bit plane to be processed and outputting an enabling signal to the encoding module providing the target encoding mode; and the at least one coding module is connected with the coding mode prediction module and is used for carrying out coding operation on the data of the bit plane to be processed when the enabling signal is received so as to generate the coded data corresponding to the bit plane to be processed.
In this embodiment, for the embodiment portion of the bit plane encoder 12, reference may be made to the description of the embodiment portion of the bit plane encoder 12, and details are not repeated here.
In the embodiment of the bit plane encoder 12, after extracting data of a plurality of bit planes from data of an original image, the bit plane encoder 12 is used to perform bit plane encoding on the data of each bit plane in parallel, so as to obtain encoded data corresponding to each bit plane; and entropy encoding the encoded data corresponding to each bit plane in parallel by using a plurality of entropy encoders 13 to obtain a compressed code stream corresponding to each bit plane, and finally generating compressed image data of the original image according to the generated compressed code stream corresponding to each bit plane.
Based on the above embodiments of the encoding circuit, some embodiments of the present application further provide an encoding method, and the encoding method provided by the embodiments of the present application is a method for encoding by the above encoding circuit.
Fig. 10 is a flowchart illustrating an encoding method according to an exemplary embodiment of the present application. As shown in fig. 10, the method includes:
s101: extracting data of a plurality of bit planes from the data of the original image by using a bit plane data separation module 11 in the coding circuit;
s102: bit-plane coding is carried out on data of a plurality of bit planes by using a plurality of bit-plane coders 12 in a coding circuit to obtain coded data corresponding to the plurality of bit planes respectively;
s103: entropy coding is performed on coded data corresponding to each of the plurality of bit planes by using an entropy coder 13 connected to a bit plane coder 12 in the coding circuit, so as to obtain compressed code streams corresponding to the plurality of bit planes, so as to generate compressed image data of the original image.
In the embodiment of the present application, an execution main body of the encoding method in the embodiment of the present application may be a computer device or a handheld device, and the implementation form of the execution main body may be various, for example, a smart phone, a personal computer, a wearable device, a tablet computer, and the like.
In this embodiment, the bit plane data separation module 11 obtains image data of an original image after wavelet transformation, and separates a sign bit of each bit plane and an amplitude of each bit plane from the image data after wavelet transformation; the effective state variable prediction module 112 is connected to the bit plane separation module 111, and is configured to obtain an effective state variable of each bit plane according to the amplitude of each bit plane.
In the above embodiment, the valid state variable prediction module 112 obtains the valid state variable of each bit plane according to the amplitude of each bit plane, and one achievable way is to perform or operation on the amplitudes of all the bit planes above the target bit plane and the corresponding positions of the designated positions to obtain the importance state variable of the designated position of the target bit plane; and the amplitude refinement state variable of the specified position of the target bit plane is the importance state variable of the corresponding position of the bit plane on the target bit plane. For example: the significance state variable σ for a given position [ m, n ] in the p-th layer bit plane is the or operation of the magnitudes of the corresponding positions of all bit planes above the p-th layer bit plane and the significance state variable of the highest layer bit plane is 0. The amplitude refinement state variable for a given position [ m, n ] in the bit plane of the p-th layer is the significance state variable for the corresponding position in the p + 1-th layer.
The significance state variable of the p-th layer bit plane is formulated as:
the amplitude refinement state variable formula of the p-th layer bit plane is as follows: e.g. of the typep＝σp+1。
Where σ denotes an effective state variable, e denotes an amplitude refinement state variable, p denotes the current layer number, v denotes the amplitude, and m, n denotes position information in the code block.
It can be seen from the above that the relationships between the bit planes are linked by the valid state variables, and the valid state variables of each coding point in each bit plane are pre-obtained, so that the data of each bit plane can be coded in a parallel manner.
The coding mode prediction module is connected to the bit plane data bit plane separation module 111, and is configured to predict a target coding mode that can be adopted by data of each bit plane, and output an enable signal to a coding module that provides a target coding mode; at least one encoding module is respectively connected to the bit plane data bit plane separation module 111, and is configured to perform an encoding operation on data of a target bit plane sent to the bit plane encoder 12 to which the encoding module belongs when receiving an enable signal, so as to generate encoded data corresponding to the target bit plane. According to the embodiment of the application, the target coding mode which can be adopted by the data of each bit plane is predicted, and the four coding modes are coded simultaneously, so that the coding speed is improved.
In the above embodiments of the present application, the neighborhood data of the current data to be encoded includes previous data of the current data to be encoded and next data of the current data to be encoded. For example, when the width of the coding slice is four, the current four data to be coded and the importance state variables of the domain data of the four data to be coded are input into the coding mode prediction module to predict the coding mode. The coding mode prediction module performs coding mode prediction as follows: if the importance state variables of the current data to be coded and the neighborhood data of the current data to be coded are both 0, determining the run coding mode as a target coding mode; if the importance states of the current data to be coded are all 0 and at least one of the importance state variables of the neighborhood data of the current data to be coded is not 0, determining a zero coding mode as a target coding mode; if the amplitude of the current data to be coded is 1, determining a symbol coding mode as a target coding mode; if the importance state variables of the current data to be coded are all 1, determining an amplitude refinement coding mode as a target coding mode; the current data to be encoded is part of the data to be encoded in the data of the target bit plane. And after the prediction of the primary coding mode is finished, setting all the enabling signals to be invalid. In the process of coding mode prediction, whether the coding mode prediction module works or not is determined by a control signal of the main control module, and after the main control module reads the next row of coded data, an enabling signal of the coding mode prediction module is set to be effective. It is obvious that the above coding mode prediction module can be implemented by using logic circuit or software.
For specific encoding modes in the run-length encoding module, the zero encoding module, the symbol encoding module and the amplitude refinement encoding module, reference may be made to the description of relevant portions of the foregoing embodiments, which is not described herein again.
In the embodiment of the encoding method of the present application, after extracting data of a plurality of bit planes from data of an original image, bit plane encoding is performed on the data of each bit plane in parallel by using a plurality of bit plane encoders 12, and then encoded data corresponding to each bit plane is obtained; and entropy encoding the encoded data corresponding to each bit plane in parallel by using a plurality of entropy encoders 13 to obtain a compressed code stream corresponding to each bit plane, and finally generating compressed image data of the original image according to the generated compressed code stream corresponding to each bit plane.
Fig. 11 is a schematic structural diagram of an encoding apparatus according to an exemplary embodiment of the present application. As shown in fig. 11, the encoding apparatus includes: a memory 1101 and a processor 1102. In addition, the data processing device also comprises necessary components like a communication component 1103 and a power component 1104.
A memory 1101 for storing computer programs and may be configured to store other various data to support operations on the data processing apparatus. Examples of such data include instructions for any application or method operating on a data processing device.
The memory 1101 may be implemented by any type or combination of volatile or non-volatile memory devices such as Static Random Access Memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic or optical disks.
A communication component 1103 configured to perform data transmission with other devices.
The processor 1102, which may execute computer instructions stored in the memory 1101, is configured to: extracting data of a plurality of bit planes from the data of the original image by using a bit plane data separation module in the coding circuit; carrying out bit plane coding on data of a plurality of bit planes by utilizing a plurality of bit plane encoders in a coding circuit to obtain coded data corresponding to the plurality of bit planes respectively; and entropy coding the coded data corresponding to the bit planes by using a plurality of entropy coders connected with a plurality of bit plane coders in the coding circuit to obtain compressed code streams corresponding to the bit planes so as to generate compressed image data of the original image.
Optionally, after obtaining the compressed code streams corresponding to the multiple bit planes, the processor 1102 may further be configured to: sequencing the compressed code streams corresponding to the bit planes by using a selector in the coding circuit and outputting the sequenced compressed code streams; and layering the sequenced compressed code streams by using a compression processing module in the coding circuit according to the quality contribution to the recovered image to generate compressed image data of the original image.
Optionally, the data of each bit plane comprises a sign bit of the bit plane, a magnitude of the bit plane, and a valid state variable of the bit plane; the processor 1102 extracts data of a plurality of bit planes from the data of the original image, and is specifically configured to: carrying out bit plane separation on data of an original image by using a bit plane separation module in a bit plane data separation module to obtain the amplitude of each bit plane and the sign bit of each bit plane; and acquiring the effective state variable of each bit plane according to the amplitude of each bit plane by using an effective state variable prediction module in the bit plane data separation module.
Optionally, the valid state variables include an importance state variable and an amplitude refinement state variable, and the processor 1102 obtains the valid state variable of the designated position of the target bit plane according to the amplitude of each bit plane, and is specifically configured to: performing OR operation on the amplitudes of all bit planes above the target bit plane and corresponding positions of the designated positions, wherein the importance state variable of the highest layer bit plane and the highest layer bit plane is 0, and obtaining the importance state variable of the designated positions of the target bit plane; and the amplitude refinement state variable of the specified position of the target bit plane is the importance state variable of the corresponding position of the bit plane on the target bit plane.
Optionally, the processor 1102 performs bit-plane coding on the data of the multiple bit planes to obtain coded data corresponding to each of the multiple bit planes, and is specifically configured to: predicting a target coding mode which can be adopted by data of each bit plane by using a coding mode prediction module in a bit plane encoder, and outputting an enable signal to a coding module in the bit plane encoder corresponding to the target coding mode; when receiving the enabling signal, the encoding module performs encoding operation on data of a target bit plane of the bit plane encoder to which the encoding module belongs to generate encoded data corresponding to the target bit plane.
Optionally, the target encoding manner that the processor 1102 can adopt in predicting the data of each bit plane is specifically used for: if the importance state variables of the current data to be coded and the neighborhood data of the current data to be coded are both 0, determining the run coding mode as a target coding mode; if the importance states of the current data to be coded are all 0 and at least one of the importance state variables of the neighborhood data of the current data to be coded is not 0, determining a zero coding mode as a target coding mode; if the amplitude of the current data to be coded is 1, determining a symbol coding mode as a target coding mode; if the importance state variables of the current data to be coded are all 1, determining an amplitude refinement coding mode as a target coding mode; the current data to be encoded is part of the data to be encoded in the data of the target bit plane.
Optionally, the encoding module comprises at least one of: the device comprises a run length coding module, a zero coding module, a symbol coding module and an amplitude refinement coding module.
The communications component of fig. 11 described above is configured to facilitate communications between the device in which the communications component is located and other devices in a wired or wireless manner. The device in which the communication component is located may access a wireless network based on a communication standard, such as WiFi, 2G or 3G, or a combination thereof. In an exemplary embodiment, the communication component receives a broadcast signal or broadcast related information from an external broadcast management system via a broadcast channel. In an exemplary embodiment, the communication component further includes Near Field Communication (NFC) technology, Radio Frequency Identification (RFID) technology, infrared data association (IrDA) technology, Ultra Wideband (UWB) technology, Bluetooth (BT) technology, and the like to facilitate short-range communications.
The power supply assembly of fig. 11 provides power to the various components of the device in which the power supply assembly is located. The power components may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power for the device in which the power component is located.
In the embodiment of the encoding device of the present application, after extracting data of a plurality of bit planes from data of an original image, bit plane encoding is performed on the data of each bit plane in parallel by using a plurality of bit plane encoders, and encoded data corresponding to each bit plane is obtained; and finally, generating compressed image data of the original image according to the generated compressed code stream corresponding to each bit plane.
Correspondingly, the embodiment of the application also provides a computer readable storage medium storing the computer program. The computer-readable storage medium stores a computer program, and the computer program, when executed by one or more processors, causes the one or more processors to perform the steps in the method embodiment shown in fig. 10.
As will be appreciated by one skilled in the art, embodiments of the present invention may be provided as a method, system, or computer program product. Accordingly, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present invention may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The present invention is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
In a typical configuration, a computing device includes one or more processors (CPUs), input/output interfaces, network interfaces, and memory.
The memory may include forms of volatile memory in a computer readable medium, Random Access Memory (RAM) and/or non-volatile memory, such as Read Only Memory (ROM) or flash memory (flash RAM). Memory is an example of a computer-readable medium.
Computer-readable media, including both non-transitory and non-transitory, removable and non-removable media, may implement information storage by any method or technology. The information may be computer readable instructions, data structures, modules of a program, or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), other types of Random Access Memory (RAM), Read Only Memory (ROM), Electrically Erasable Programmable Read Only Memory (EEPROM), flash memory or other memory technology, compact disc read only memory (CD-ROM), Digital Versatile Discs (DVD) or other optical storage, magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage devices, or any other non-transmission medium that can be used to store information that can be accessed by a computing device. As defined herein, a computer readable medium does not include a transitory computer readable medium such as a modulated data signal and a carrier wave.
It should also be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
The above description is only an example of the present application and is not intended to limit the present application. Various modifications and changes may occur to those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the scope of the claims of the present application.
Claims (14)
1. An encoding circuit, comprising: the device comprises a bit plane data separation module, a plurality of bit plane encoders and a plurality of entropy encoders;
the bit plane data separation module is used for extracting data of a plurality of bit planes from data of an original image;
the bit plane encoders are connected with a bit plane data separation module and used for performing bit plane encoding on the data of the bit planes to obtain encoded data corresponding to the bit planes;
the entropy encoder is respectively connected with the bit plane encoder and is used for entropy encoding the encoded data corresponding to each bit plane to obtain compressed code streams corresponding to the bit planes so as to generate compressed image data of the original image.
2. The circuit of claim 1, further comprising: and the selector is connected with the plurality of entropy encoders and is used for sequencing the compressed code streams corresponding to the plurality of bit planes and outputting the sequenced compressed code streams so as to generate compressed image data of the original image.
3. The circuit of claim 1 or 2, wherein the data for each bit plane comprises: sign bit of the bit plane, amplitude of the bit plane and effective state variable of the bit plane;
the bit-plane data separation module includes: the device comprises a bit plane separation module and an effective state variable prediction module;
the bit plane separation module acquires data of an original image, and separates the data of the original image to obtain sign bits of each bit plane and amplitude values of each bit plane;
and the effective state variable prediction module is connected with the bit plane separation module and is used for acquiring the effective state variable of each bit plane according to the amplitude of each bit plane.
4. The circuit of claim 1 or 2, wherein each bit plane encoder comprises a coding mode prediction module and at least one coding module;
the coding mode prediction module is connected with the bit plane data separation module and used for predicting a target coding mode which can be adopted by data of each bit plane and outputting an enable signal to a coding module corresponding to the target coding mode;
and the at least one coding module is respectively connected with the bit plane data separation module and is used for carrying out coding operation on the data of the target bit plane sent into the bit plane coder to which the coding module belongs when an enabling signal is received so as to generate the coded data corresponding to the target bit plane.
5. The circuit of claim 4, wherein the valid state variables comprise significance state variables, and wherein the encoding mode prediction module is specifically configured to:
if the importance state variables of the current data to be coded and the neighborhood data of the current data to be coded are both 0, determining a run coding mode as the target coding mode;
if the importance states of the current data to be coded are all 0 and at least one of the importance state variables of the neighborhood data of the current data to be coded is not 0, determining a zero coding mode as the target coding mode;
if the amplitude of the current data to be coded is 1, determining a symbol coding mode as the target coding mode;
if the importance state variables of the current data to be coded are all 1, determining an amplitude refinement coding mode as the target coding mode;
and the current data to be coded is partial data to be coded in the data of the target bit plane.
6. A bit plane encoder, comprising: the encoding mode prediction module and at least one encoding module;
the encoding mode prediction module is used for receiving data of a bit plane to be processed, predicting a target encoding mode which can be adopted by the data of the bit plane to be processed, and outputting an enable signal to the encoding module providing the target encoding mode;
and the at least one coding module is connected with the coding mode prediction module and is used for carrying out coding operation on the data of the bit plane to be processed when an enabling signal is received so as to generate the coded data corresponding to the bit plane to be processed.
7. An encoding method applied to an encoding circuit, the method comprising:
extracting data of a plurality of bit planes from the data of the original image by using a bit plane data separation module in the coding circuit;
carrying out bit plane coding on the data of the bit planes by utilizing a plurality of bit plane encoders in a coding circuit to obtain coded data corresponding to the bit planes respectively;
and entropy coding the coded data corresponding to each bit plane by using an entropy coder connected with a bit plane coder in a coding circuit to obtain compressed code streams corresponding to the bit planes so as to generate compressed image data of the original image.
8. The method of claim 7, wherein after obtaining the compressed codestreams corresponding to the plurality of bit planes, further comprising:
and sequencing the compressed code streams corresponding to the bit planes by using a selector in the coding circuit and outputting the sequenced compressed code streams.
9. The method of claim 7, wherein the data of each bit plane comprises a sign bit of the bit plane, a magnitude of the bit plane, and a valid state variable of the bit plane;
extracting data of a plurality of bit planes from data of the original image, including:
carrying out bit plane separation on data of an original image by using a bit plane separation module in a bit plane data separation module to obtain the amplitude of each bit plane and the sign bit of each bit plane;
and acquiring the effective state variable of each bit plane according to the amplitude of each bit plane by using an effective state variable prediction module in the bit plane data separation module.
10. The method of claim 9, wherein the valid state variables comprise significance state variables and magnitude refinement state variables, and wherein obtaining the valid state variables for the specified location of the target bit-plane based on the magnitude of each bit-plane comprises:
performing OR operation on the amplitudes of all bit planes above the target bit plane and the corresponding positions of the designated positions, wherein the importance state variable of the highest layer bit plane and the highest layer bit plane is 0, and the importance state variable of the designated positions of the target bit plane is obtained;
and the amplitude refinement state variable of the specified position of the target bit plane is the importance state variable of the corresponding position of the bit plane on the target bit plane.
11. The method of claim 7, wherein bit-plane coding the data of the plurality of bit-planes to obtain coded data corresponding to each of the plurality of bit-planes comprises:
predicting a target coding mode which can be adopted by data of each bit plane by using a coding mode prediction module in a bit plane encoder, and outputting an enable signal to a coding module in the bit plane encoder which provides a corresponding target coding mode;
and when receiving an enabling signal, the encoding module performs encoding operation on data input into a target bit plane of a bit plane encoder to which the encoding module belongs to generate encoded data corresponding to the target bit plane.
12. The method of claim 11, wherein the valid state variables comprise significance state variables, and wherein predicting a target encoding mode that can be used for data of each bit plane comprises:
if the importance state variables of the current data to be coded and the neighborhood data of the current data to be coded are both 0, determining a run coding mode as the target coding mode;
if the importance states of the current data to be coded are all 0 and at least one of the importance state variables of the neighborhood data of the current data to be coded is not 0, determining a zero coding mode as the target coding mode;
if the amplitude of the current data to be coded is 1, determining a symbol coding mode as the target coding mode;
if the importance state variables of the current data to be coded are all 1, determining an amplitude refinement coding mode as the target coding mode;
and the current data to be coded is partial data to be coded in the data of the target bit plane.
13. An encoding device, characterized by comprising: a memory and a processor;
the memory to store one or more computer instructions;
the processor to execute the one or more computer instructions to:
extracting data of a plurality of bit planes from data of an original image by using a bit plane data separation module in an encoding circuit;
carrying out bit plane coding on the data of the bit planes by utilizing a plurality of bit plane encoders in a coding circuit to obtain coded data corresponding to the bit planes respectively;
and entropy coding the coded data corresponding to the bit planes by using an entropy coder connected with a bit plane coder in a coding circuit to obtain compressed code streams corresponding to the bit planes so as to generate compressed image data of the original image.
14. A computer-readable storage medium storing a computer program, wherein the computer program, when executed by one or more processors, causes the one or more processors to perform acts comprising:
extracting data of a plurality of bit planes from data of an original image by using a bit plane data separation module in an encoding circuit;
carrying out bit plane coding on the data of the bit planes by utilizing a plurality of bit plane encoders in a coding circuit to obtain coded data corresponding to the bit planes respectively;
and entropy coding the coded data corresponding to the bit planes by using an entropy coder connected with a bit plane coder in a coding circuit to obtain compressed code streams corresponding to the bit planes so as to generate compressed image data of the original image.
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