CN113035830A - Semiconductor structure and manufacturing method thereof - Google Patents
Semiconductor structure and manufacturing method thereof Download PDFInfo
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- CN113035830A CN113035830A CN202110255894.9A CN202110255894A CN113035830A CN 113035830 A CN113035830 A CN 113035830A CN 202110255894 A CN202110255894 A CN 202110255894A CN 113035830 A CN113035830 A CN 113035830A
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- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
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- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0231—Manufacturing methods of the redistribution layers
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0233—Structure of the redistribution layers
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0237—Disposition of the redistribution layers
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Abstract
The present disclosure provides a semiconductor structure and a method for manufacturing the same, in the case of a shortage of BGA (Ball Grid Array) substrates and a low yield of FOSub (Fan-Out Bonding) substrates, the present disclosure uses the Bonding of the Substrate (Substrate) and the redistribution interposer (RDL interposer) to replace a multilayer BGA Substrate, and uses the FCB (Flip Chip Bonding) technique to bond the Substrate and the redistribution interposer, and uses the molding (molding) technique to manufacture the redistribution interposer, thereby improving the product yield.
Description
Technical Field
The present disclosure relates to the field of semiconductor technology, and more particularly, to a semiconductor structure and a method for fabricating the same.
Background
At present, the multilayer BGA substrate can contain both thick circuit and thin circuit, but due to the factors of large number of substrate layers and large size of semiconductor, the BGA substrate is seriously short and has short supply. For this reason, although an FOSub (Fan-Out bonded Substrate) Substrate has been developed, the development of an FOSub Substrate in which a Fan-Out line (thin line) and a Substrate line (thick line) are bonded and electrically connected through Via (Via hole) is still in need of verification of reliability and thermal stress analysis, and is not economical.
Disclosure of Invention
The present disclosure provides semiconductor structures and methods of fabricating the same.
In a first aspect, the present disclosure provides a semiconductor structure comprising: a substrate; the rewiring interposer is arranged on the substrate and comprises a rewiring layer, a conductive column, a first molding layer and an electric contact piece, wherein the first molding layer is arranged on the electric contact piece, the conductive column is embedded into the first molding layer, the rewiring layer is arranged on the first molding layer, and the first molding layer is made of an organic material.
In some alternative embodiments, the rerouting interposer further comprises: the seed layer is arranged between the first die sealing layer and the electric contact and comprises a barrier layer and a conductive layer which are sequentially arranged from bottom to top.
In some optional embodiments, the surface of the conductive pillar near the seed layer is a curved surface.
In some alternative embodiments, the height of the conductive posts is between 60 microns and 100 microns and/or the diameter of the conductive posts is 80 microns.
In some alternative embodiments, the first mold layer has an upper surface and a lower surface, the upper surface having a roughness greater than a roughness of the lower surface.
In some optional embodiments, the semiconductor structure further comprises: the first underfill material covers the electrical contact and fills a gap between the first molding layer and the substrate.
In some optional embodiments, the semiconductor structure further comprises: and the chip is arranged on the rewiring intermediate layer.
In some optional embodiments, the semiconductor structure further comprises: and the second underfill material fills the gap between the chip and the redistribution interposer.
In some optional embodiments, the semiconductor structure further comprises: and the second molding material is used for coating the rewiring medium layer, the second bottom filling material and the chip.
In some alternative embodiments, the rigidity of the first mold seal layer is greater than the rigidity of the second mold seal material.
In some alternative embodiments, the second mold encapsulant exposes the back side of the chip; and the semiconductor structure further comprises: and the heat sink is arranged on the chip.
In some optional embodiments, the semiconductor structure further comprises: and the base plate is arranged on the external electric contact.
In some alternative embodiments, the chip is an application specific integrated circuit ASIC chip and/or a high bandwidth memory HBM.
In a second aspect, the present disclosure provides a method of fabricating a semiconductor structure, the method comprising: arranging a conductive column on the first carrier; filling the first mold sealing material to cover the conductive post; grinding the upper surface of the first mold sealing material to expose the conductive column to form a first mold sealing layer; arranging a rewiring layer on the upper surface of the first molding layer; arranging an electric contact on the lower surface of the first molding layer, wherein the conductive column, the first molding layer, the redistribution layer and the electric contact form a redistribution interposer together; the redistribution interposer is disposed on the upper surface of the substrate such that the redistribution interposer is in electrical communication with the substrate via the electrical contacts.
In some optional embodiments, before providing the conductive pillars on the first carrier, the method further comprises: disposing a barrier layer on the first support; a conductive layer is disposed on the barrier layer, and the barrier layer and the conductive layer together form a seed layer.
In some optional embodiments, the method further comprises: and filling the first underfill material to cover the electrical contact and fill the gap between the first molding layer and the substrate.
In some optional embodiments, the method further comprises: the chip is disposed on the redistribution interposer.
In some optional embodiments, the method further comprises: and filling a second underfill material to fill the gap between the chip and the redistribution interposer.
In some optional embodiments, the method further comprises: a second molding compound is disposed to encapsulate the redistribution interposer, the second underfill material, and the chip.
In some optional embodiments, the method further comprises: grinding the upper surface of the second mold sealing material to expose the back surface of the chip; a heat sink is arranged on the back of the chip.
In some optional embodiments, the method further comprises: external electrical contacts are provided on the lower surface of the base plate.
Due to the severe shortage of multilayer BGA substrates on the market and the need for reliability and thermal stress analysis verification in the development of FOSub substrates, there is a need to develop a product that can replace BGA substrates. In addition, in the conventional FOSub Substrate structure, Fan-Out (Fan-Out) and Substrate (Substrate) are combined through an adhesive material (adhesive material) and a via (via), and due to the fact that offset occurs between Fan-Out and Substrate, laser drilling causes no hole at the bottom of the via, and the via cannot accurately communicate with Fan-Out and Substrate, the FOSub Substrate may have electrical functional problems such as open circuit, over resistance, no function, signal error and the like, and the yield is low.
The substrate and the redistribution interposer are combined by the FCB technology and the first underfill material is filled, so that the FCB technology is stable in manufacturing process and high in yield. The combination of the conductive columns and the first mold sealing layer is realized through a molding (molding) technology, the rewiring interposer is obtained, a conductive channel is manufactured without a laser drilling process and an electroplating process, the phenomenon that the electric communication cannot be realized due to the fact that holes are not formed in the bottoms of the via holes or the electroplating is incomplete can be avoided, the electric communication is guaranteed, and the yield of products is improved.
Drawings
Other features, objects and advantages of the disclosure will become more apparent upon reading of the following detailed description of non-limiting embodiments thereof, made with reference to the accompanying drawings in which:
FIG. 1 is a schematic structural diagram of one embodiment of a semiconductor structure according to the present disclosure;
FIG. 2 is a partial enlarged view of one embodiment of a semiconductor structure according to the present disclosure;
fig. 3A to 3L are schematic structural diagrams in the fabrication of a semiconductor structure according to the present disclosure.
Description of the symbols:
1-substrate, 2-rewiring interposer, 201-electrical contact, 202-conductive pillar, 203-first encapsulant, 204-rewiring layer, 205-seed layer, 2051-barrier layer, 2052-conductive layer, 3-chip, 4-second underfill, 5-heat sink, 6-external electrical contact, 7-first carrier, 8-second carrier, 9-second encapsulant, 10-first underfill.
Detailed Description
The following description of the embodiments of the present disclosure will be provided in conjunction with the accompanying drawings and examples, and those skilled in the art can easily understand the technical problems and effects of the present disclosure. It is to be understood that the specific embodiments described herein are merely illustrative of the relevant invention and not restrictive of the invention. In addition, for convenience of description, only portions related to the related invention are shown in the drawings.
It should be noted that the structures, proportions, and dimensions shown in the drawings and described in the specification are for the understanding and reading of the present disclosure, and are not intended to limit the conditions under which the present disclosure can be implemented, so they are not technically significant, and any modifications of the structures, changes in the proportions and adjustments of the dimensions should be made without affecting the efficacy and attainment of the same. In the present specification, the terms "upper", "first", "second" and "first" are used for clarity of description only, and are not intended to limit the scope of the present disclosure, and changes or modifications in relative relationships thereof should be construed as being within the scope of the present disclosure without substantial technical changes.
In addition, the embodiments and features of the embodiments in the present disclosure may be combined with each other without conflict. The present disclosure will be described in detail below with reference to the accompanying drawings in conjunction with embodiments.
Referring to fig. 1, fig. 1 shows a schematic structural diagram of one embodiment of a semiconductor structure according to the present disclosure. As shown in fig. 1, the semiconductor structure may include: a substrate 1 and a redistribution interposer 2. The redistribution interposer 2 is disposed on the substrate 1, the redistribution interposer 2 may include a redistribution layer 204, a conductive pillar 202, a first molding compound 203, and an electrical contact 201, the first molding compound 203 is disposed on the electrical contact 201, the conductive pillar 202 is embedded in the first molding compound 203, the redistribution layer 204 is disposed on the first molding compound 203, and the first molding compound 203 is made of an organic material.
The substrate 1 may be a coreless substrate or a cored substrate. The substrate 1 may include organic and/or inorganic substances, and the organic substances may be, for example: polyamide fibers (Polyamide, PA), Polyimide (PI), Epoxy resins (Epoxy), Poly-p-Phenylene Benzobisoxazole (PBO) fibers, FR-4 Epoxy glass cloth laminates, PP (PrePreg, PrePreg or so-called PrePreg, PrePreg), ABF (Ajinomoto Build-up Film), and the like, and inorganic substances may be, for example, silicon (Si), glass (glass), ceramics (ceramic), silicon oxide, silicon nitride, tantalum oxide, and the like. The substrate 1 may also be a PCB (Printed Circuit Board), and may be made of a rigid substrate material such as a copper clad laminate material or a flexible substrate material such as a PI material. The substrate 1 may also be a BGA substrate.
Various wires, vias, buried vias or blind vias may be provided in the redistribution layer 204 to enable line connections. It should be noted that the size or direction of the through hole, buried hole or blind hole is not specifically limited. If a via, buried via or blind via is provided, the via, buried via or blind via may be filled with or contain a conductive material such as a metal or metal alloy. Here, the metal may be, for example, gold (Au), silver (Ag), aluminum (Al), copper (Cu), or an alloy thereof.
The conductive posts 202 may provide a conductive function, and may be made of a conductive material such as a metal or a metal alloy.
The first molding layer 203 may use an organic material, and the organic material may be, for example, Epoxy resin (Epoxy resin), Filler (Filler), Catalyst (Catalyst), Pigment (Pigment), Release Agent (Release Agent), Flame Retardant (Flame Retardant), Coupling Agent (Coupling Agent), Hardener (hardner), Low Stress absorbent (Low Stress Absorber), Adhesion Promoter (Adhesion Promoter), Ion trap (Ion Trapping Agent). In the manufacturing process, the redistribution interposer 2 is manufactured by molding (molding) technology, so the redistribution interposer 2 includes the first mold seal layer 203 manufactured by the organic mold seal material.
The electrical contact 201 may be any type of electrical contact, such as a solder bump (solder bump) or a conductive pillar bump (pillar bump). Here, the redistribution interposer 2 connects the redistribution layer 204 and the substrate 1 via the electrical contacts 201.
In some alternative embodiments, the rerouting interposer 2 may further include: a seed layer 205 disposed between the first molding layer 203 and the electrical contact 201, the seed layer 205 may include a barrier layer 2051 and a conductive layer 2052 disposed in sequence from bottom to top.
Here, the seed layer 205 may have a function of providing a conductive function so that the conductive pillar 202 plating proceeds smoothly. The barrier layer 2051 may be used to prevent diffusion between the electrical contact 201 and the conductive layer 2052, for example titanium may be used. The conductive layer 2052 can be used for electrical communication, and can be made of a conductive material such as a metal or a metal alloy, for example, copper.
Referring to fig. 2, fig. 2 illustrates a partial enlarged view of one embodiment of a semiconductor structure of the present disclosure.
In some alternative embodiments, as shown in fig. 2, the surface of the conductive pillars 202 proximate to the seed layer 205 may be curved.
In the process of electroplating the conductive pillars 202, the conductive pillars 202 are defined by a photoresist (photosensitive material), and during the processes of exposure, development and etching, a retraction phenomenon may occur at the bottoms of the conductive pillars 202, that is, the surfaces of the conductive pillars 202 close to the seed layer 205 are curved.
In some alternative embodiments, the height of the conductive posts 202 may be between 60 microns and 100 microns and/or the diameter of the conductive posts 202 is 80 microns.
In some alternative embodiments, the first molding layer 203 may have an upper surface and a lower surface, and the roughness of the upper surface may be greater than the roughness of the lower surface.
In the manufacturing process, the first mold sealing layer 203 is required to be filled to cover the conductive pillars 202, and the upper surface of the first mold sealing layer 203 is polished to expose the conductive pillars 202, because the roughness of the upper surface is increased after the upper surface of the first mold sealing layer 203 is polished, the roughness of the upper surface may be larger than that of the lower surface compared to the lower surface without being polished.
In some optional embodiments, the semiconductor structure may further include a first underfill material 10. The first underfill material 10 may cover the electrical contacts 201 and fill the gap between the first molding layer 203 and the substrate 1.
The first underfill material 10 may be, for example, Capillary Underfill (CUF), Molded Underfill (MUF), Non-conductive Paste (NCP), or the like. The first underfill material 10 may fill the voids for reinforcement purposes.
In some alternative embodiments, the semiconductor structure further comprises a chip 3. The chip 3 may be provided on the redistribution interposer 2.
Here, the chip 3 may be a chip of various sizes and various functions. Micro bumps (micro bumps) or pre-solders (pre-solder) may be disposed on the active surface of the chip 3.
In some optional embodiments, the semiconductor structure further comprises a second underfill material 4. The second underfill material 4 may fill the gap between the chip 3 and the redistribution interposer 2.
The second underfill material 4 may be, for example, Capillary Underfill (CUF), Molded Underfill (MUF), Non-conductive Paste (NCP), or the like. The second underfill material 4 can improve the active surface of the protection chip 3 and improve the bonding force between the chip 3 and the redistribution interposer 2.
In some optional embodiments, the semiconductor structure further comprises a second mold material 9. The second mold sealing material 9 may cover the redistribution interposer 2, the second underfill material 4, and the chip 3.
The second molding material 9 may be an Epoxy resin (Epoxy resin), a Filler (Filler), a Catalyst (Catalyst), a Pigment (Pigment), a Release Agent (Release Agent), a Flame Retardant (Flame Retardant), a Coupling Agent (Coupling Agent), a curing Agent (hardner), a Low Stress absorbent (Low Stress absorbent), an Adhesion Promoter (Adhesion Promoter), an Ion Trapping Agent (Ion Trapping Agent), or the like.
In some alternative embodiments, the rigidity of the first mold seal layer 203 may be greater than the rigidity of the second mold seal material 9.
Here, the second molding compound 9 may cover the redistribution interposer 2, the second underfill 4, and the chip 3 to protect them, and the redistribution layer 204 may be disposed on the first molding compound 203 with respect to the second molding compound 9, and the first molding compound 203 also needs to provide a function of supporting the redistribution layer 204, so that the rigidity of the first molding compound 203 may be greater than that of the second molding compound 9 with respect to the second molding compound 9 that does not need to provide a supporting function.
In practice, the rigidity of the mold seal material may be controlled by selecting mold seal materials of different rigidities, or the rigidity of the mold seal material may be controlled by controlling the particle size ratio of the filler in the same mold seal material.
In some alternative embodiments, the second mold material 9 may expose the back side of the chip 3; and the semiconductor structure may further comprise a heat sink 5 provided on the chip 3.
The heat sink 5 may be a heat sink 5 or other suitable heat dissipating structure. The heat sink 5 may also be a conductive material such as aluminum (Al), copper (Cu), chromium (Cr), tin (Sn), gold (Au), silver (Ag), nickel (Ni), stainless steel, or other conductive material.
A heat sink 5 is arranged on the chip 3, and heat generated by the chip 3 can be transferred to the heat sink 5 and then transferred to the environment through the heat sink 5. Generally, the surface area of the heat sink 5 is made relatively large, and the contact surface with air is large, so that heat transfer is facilitated and the heat dissipation efficiency is improved.
In some alternative embodiments, the semiconductor structure may further comprise an external electrical contact 6. The base plate 1 is provided on external electrical contacts 6.
The external electrical contact 6 may be, for example, a wire (Trace), a Bump (Bump), a Solder Ball (Solder Ball), or the like, to electrically connect the semiconductor structure to the outside.
In some alternative embodiments, the chip 3 may be an application specific integrated circuit ASIC chip and/or a high bandwidth memory HBM.
The semiconductor structure provided by the present disclosure replaces a multilayer BGA Substrate by combining the Substrate 1(Substrate) and the redistribution interposer 2(RDL interposer) in the case of shortage of the current BGA Substrate and low yield of the FOSub Substrate.
Fig. 3A to 3L show schematic structural views in the manufacturing process of the semiconductor structure of the present disclosure. The figures have been simplified for a better understanding of various aspects of the disclosure.
Referring to fig. 3A, a conductive pillar 202 is disposed on the first carrier 7.
Here, the conductive post 202 may be provided using an electroplating process.
In some optional embodiments, before providing the conductive pillars 202 on the first carrier 7, the method further comprises: providing a barrier layer 2051 on the first carrier 7; a conductive layer 2052 is disposed over the barrier layer 2051, the barrier layer 2051 and the conductivity collectively forming the seed layer 205.
Referring to fig. 3B, the first mold compound is filled to encapsulate the conductive pillars 202. The upper surface of the first molding compound is polished to expose the conductive pillars 202, so as to form a first molding layer 203.
Referring to fig. 3C, a redistribution layer 204 is disposed on the upper surface of the first molding layer 203.
Referring to fig. 3D, the first carrier 7 is removed, the redistribution layer 204 is disposed on the second carrier 8, the electrical contact 201 is disposed on the lower surface of the first molding compound 203, and the conductive pillar 202, the first molding compound 203, the redistribution layer 204 and the electrical contact 201 together form the redistribution interposer 2.
Referring to fig. 3E, the second carrier 8 is removed.
Referring to fig. 3F, the redistribution interposer 2 is disposed on the upper surface of the substrate 1, such that the redistribution interposer 2 is in electrical communication with the substrate 1 via the electrical contacts 201.
Referring to fig. 3G, in some alternative embodiments, the method may further include: the first underfill material 10 is filled to cover the electrical contacts 201 and fill the gap between the first molding compound 203 and the substrate 1.
Referring to fig. 3H, in some alternative embodiments, the method may further include: the chip 3 is disposed on the redistribution interposer 2.
Here, the electrical communication of the chip 3 with the substrate 1 is achieved by means of FCB technology, i.e. with electrical contacts 201.
Referring to fig. 3I, in some alternative embodiments, the method may further include: the second underfill material 4 is filled to fill the gap between the chip 3 and the redistribution interposer 2.
Referring to fig. 3J, in some alternative embodiments, the method may further include: the second molding compound 9 is disposed to cover the redistribution interposer 2, the second underfill 4, and the chip 3.
Referring to fig. 3K, in some alternative embodiments, the method may further include: the upper surface of the second mold sealing material 9 is ground to expose the back surface of the chip 3.
Referring to fig. 3L, in some alternative embodiments, the method may further include: a heat sink 5 is provided on the back surface of the chip 3. External electrical contacts 6 are provided on the lower surface of the base plate 1.
In the FOSub Substrate structure in the prior art, Fan-Out and Substrate are combined through a bonding material and a via (via), and the FOSub Substrate may have electrical functional problems such as open circuit, over resistance, no function, signal error and the like due to the fact that offset occurs between Fan-Out and Substrate, no hole is formed at the bottom of the via caused by laser drilling, and the via cannot accurately communicate with Fan-Out and Substrate, and thus the yield is low.
Specifically, the FCB technology is used to combine the substrate 1 and the redistribution interposer 2 and fill the first underfill material 10, so that the FCB technology has a stable process and a high yield. The combination of the conductive pillars 202 and the first mold layer 203 is realized by a molding (molding) technology, so as to obtain the redistribution interposer 2, and a conductive channel is manufactured without a laser drilling process and a plating process, thereby avoiding the phenomenon that the bottom of the via hole is not opened or the plating is incomplete, which causes the electrical connection to be impossible.
The method for manufacturing the semiconductor structure, which is provided by the disclosure, combines the substrate 1 and the redistribution interposer 2 by using the FCB technology, and manufactures the redistribution interposer 2 by using a molding (molding) technology, thereby improving the product yield compared with the existing FOsub substrate.
While the present disclosure has been described and illustrated with reference to particular embodiments thereof, such description and illustration are not intended to limit the present disclosure. It will be clearly understood by those skilled in the art that various changes may be made and equivalents may be substituted for elements thereof within the embodiments without departing from the true spirit and scope of the disclosure as defined by the appended claims. The illustrations may not be drawn to scale. There may be a difference between the technical reproduction and the actual implementation in the present disclosure due to variables in the manufacturing process, and the like. There may be other embodiments of the disclosure that are not specifically illustrated. The specification and drawings are to be regarded in an illustrative rather than a restrictive sense. Modifications may be made to adapt a particular situation, material, composition of matter, method, or process to the objective, spirit and scope of the present disclosure. All such modifications are intended to fall within the scope of the appended claims. Although the methods disclosed herein have been described with reference to particular operations performed in a particular order, it should be understood that these operations may be combined, sub-divided, or reordered to form equivalent methods without departing from the teachings of the present disclosure. Accordingly, unless specifically indicated herein, the order and grouping of the operations is not a limitation of the present disclosure.
Claims (20)
1. A semiconductor structure, comprising:
a substrate;
the rewiring interposer is arranged on the substrate and comprises a rewiring layer, a conductive post, a first mold sealing layer and an electric contact piece, wherein the first mold sealing layer is arranged on the electric contact piece, the conductive post is embedded into the first mold sealing layer, the rewiring layer is arranged on the first mold sealing layer, and the first mold sealing layer is made of an organic material.
2. The semiconductor structure of claim 1, wherein the redistribution interposer further comprises:
the seed layer is arranged between the first die sealing layer and the electric contact and comprises a barrier layer and a conducting layer which are sequentially arranged from bottom to top.
3. The semiconductor structure of claim 2, wherein the surface of the conductive pillar proximate to the seed layer is curved.
4. The semiconductor structure of claim 1, wherein the conductive pillars have a height of between 60 microns and 100 microns and/or a diameter of 80 microns.
5. The semiconductor structure of claim 1, wherein the first mold layer has an upper surface and a lower surface, the upper surface having a roughness greater than a roughness of the lower surface.
6. The semiconductor structure of claim 1, wherein the semiconductor structure further comprises:
and the first underfill material covers the electric contact and fills a gap between the first molding layer and the substrate.
7. The semiconductor structure of claim 1, wherein the semiconductor structure further comprises:
and the chip is arranged on the rewiring interposer.
8. The semiconductor structure of claim 7, wherein the semiconductor structure further comprises:
a second underfill material filling a gap between the die and the redistribution interposer.
9. The semiconductor structure of claim 8, wherein the semiconductor structure further comprises:
and the second molding material is used for coating the rewiring interposer, the second underfill material and the chip.
10. The semiconductor structure of claim 9, wherein a rigidity of the first mold seal layer is greater than a rigidity of the second mold seal material.
11. The semiconductor structure of claim 9 or 10, wherein the second mold encapsulant exposes a back surface of the chip; and
the semiconductor structure further includes: and the heat sink is arranged on the chip.
12. The semiconductor structure of claim 9 or 10, wherein the semiconductor structure further comprises:
an external electrical contact, the substrate being disposed on the external electrical contact.
13. The semiconductor structure of claim 1, wherein the chip is an Application Specific Integrated Circuit (ASIC) chip and/or a High Bandwidth Memory (HBM).
14. A method of fabricating a semiconductor structure, comprising:
arranging a conductive column on the first carrier;
filling a first mold sealing material to coat the conductive post;
grinding the upper surface of the first mold sealing material to expose the conductive column to form a first mold sealing layer;
arranging a rewiring layer on the upper surface of the first mold sealing layer;
providing electrical contacts on a lower surface of the first encapsulation layer, the conductive pillars, the first encapsulation layer, the redistribution layer, and the electrical contacts collectively forming a redistribution interposer;
disposing the redistribution interposer on an upper surface of a substrate such that the redistribution interposer is in electrical communication with the substrate through the electrical contacts.
15. The method of claim 14, wherein prior to said disposing conductive posts on the first carrier, the method further comprises:
providing a barrier layer on the first support;
and arranging a conductive layer on the barrier layer, wherein the barrier layer and the conductive layer jointly form a seed layer.
16. The method of claim 14, wherein the method further comprises:
and filling a first underfill material to cover the electrical contact and fill a gap between the first molding compound and the substrate.
17. The method of claim 16, wherein the method further comprises:
disposing a chip on the redistribution interposer.
18. The method of claim 17, wherein the method further comprises:
and filling a second underfill material to fill the gap between the chip and the redistribution interposer.
19. The method of claim 18, wherein the method further comprises:
and arranging a second molding material to coat the redistribution interposer, the second underfill material and the chip.
20. The method of claim 19, wherein the method further comprises:
grinding the upper surface of the second molding material to expose the back surface of the chip;
and arranging a heat sink on the back surface of the chip.
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