CN113035799B - Three-dimensional packaging structure - Google Patents
Three-dimensional packaging structure Download PDFInfo
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- CN113035799B CN113035799B CN201911359333.2A CN201911359333A CN113035799B CN 113035799 B CN113035799 B CN 113035799B CN 201911359333 A CN201911359333 A CN 201911359333A CN 113035799 B CN113035799 B CN 113035799B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/46—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements involving the transfer of heat by flowing fluids
- H01L23/473—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements involving the transfer of heat by flowing fluids by flowing liquids
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
- H01L25/03—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H10D89/00
- H01L25/0652—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H10D89/00 the devices being arranged next and on each other, i.e. mixed assemblies
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
The disclosure relates to a three-dimensional packaging structure, belongs to the packaging field, and can realize high-efficiency heat dissipation. A three-dimensional package structure includes a plurality of stacked chips, and further includes micro flow channels between the stacked chips, and micro pumps for pushing coolant to circulate in the micro flow channels to bring heat from the inside to the outside of the three-dimensional package structure.
Description
Technical Field
The present disclosure relates to the field of wafer level packaging, and in particular, to a three-dimensional packaging structure.
Background
At present, a mainstream heat dissipation mode of three-dimensional packaging is to conduct heat generated by chip operation inside a packaging body to the surface by means of heat conduction, and then heat dissipation is completed by heat convection or heat conduction. In order to ensure the heat dissipation effect, the heat resistance of the heat dissipation path is required to be reduced as much as possible, however, in the three-dimensional packaging, the interface heat resistance is difficult to be well controlled, so that the heat dissipation efficiency of the existing scheme is low.
Disclosure of Invention
The purpose of the present disclosure is to provide a three-dimensional package structure capable of achieving efficient heat dissipation.
According to a first embodiment of the present disclosure, there is provided a three-dimensional package structure including a plurality of stacked chips, the three-dimensional package structure further including a micro flow channel between the stacked chips, and a micro pump for pushing a coolant to circulate in the micro flow channel to bring heat from an inside to an outside of the three-dimensional package structure.
Optionally, the micro flow channel is made of a thermally conductive material.
Optionally, the micro flow channel is made of at least one of metal and semiconductor materials.
Optionally, the micro flow channels have dimensions comparable to those of the inter-layer electrical interconnections of the stacked chips.
Optionally, the thickness of the micro flow channel is in the range of 1 micron to 100 microns.
Optionally, the three-dimensional package structure further comprises a dielectric filled between the micro-fluidic channels and the inter-layer electrical interconnects of the stacked chips.
Optionally, the micropump is integrated at a topmost or bottommost portion of the three-dimensional package structure.
Optionally, the micropump is combined with a heat sink of the three-dimensional package structure.
Optionally, the micro-channels between different stacks are connected by mold and/or chip through holes, commonly connected to coolant inlets and outlets connected to the micro-pump.
By adopting the technical scheme, as the micro-flow channel is integrated in the three-dimensional packaging structure, the three-dimensional packaging structure provides possibility for three-dimensional stacking of more layers, and can greatly improve the heat dissipation capacity of the three-dimensional packaging structure, thereby effectively reducing the working temperature of the functional chip, improving the upper power limit of the functional chip, and compared with other existing heat dissipation modes, the three-dimensional packaging structure has the advantages of lower shape factor, lower cost, stronger universality and the like. In addition, through the micro-channel graphic design, the IPD is allowed to be integrated, and meanwhile, a solution is provided for enhancing the heat dissipation capacity aiming at hot spots. The three-dimensional packaging structure can be manufactured by adopting a wafer-level manufacturing process compatible with a silicon-based manufacturing process, and the mass production capacity and the process stability are ensured.
Additional features and advantages of the present disclosure will be set forth in the detailed description which follows.
Drawings
The accompanying drawings are included to provide a further understanding of the disclosure, and are incorporated in and constitute a part of this specification, illustrate the disclosure and together with the description serve to explain, but do not limit the disclosure. In the drawings:
fig. 1 shows a schematic side view of a three-dimensional package structure according to one embodiment of the present disclosure.
Fig. 2 illustrates yet another schematic side view of a three-dimensional package structure according to one embodiment of the present disclosure.
Fig. 3 shows a flow chart of a method of fabricating a three-dimensional package structure according to one embodiment of the present disclosure.
Fig. 4a-4h illustrate in side view a flow chart of a method of fabricating a three-dimensional package structure according to an embodiment of the present disclosure.
Detailed Description
Specific embodiments of the present disclosure are described in detail below with reference to the accompanying drawings. It should be understood that the detailed description and specific examples, while indicating and illustrating the disclosure, are not intended to limit the disclosure.
Fig. 1 shows a schematic side view of a three-dimensional package structure according to one embodiment of the present disclosure. As shown in fig. 1, the three-dimensional package structure includes a plurality of stacked chips 1, and further includes a micro flow channel 2 and a micro pump 3. The micro flow channels 2 are located between the stacked chips 1, which are micro channels in which coolant can circulate, and can realize heat dissipation of the chips 1 located on both sides of the micro flow channels 2. Since fig. 1 is a side view of a three-dimensional package structure, the micro flow channels 2 are interconnected in a planar direction. The micro pump 3 is used to push the coolant to circulate in the micro flow channel 2 to bring heat from the inside to the outside of the three-dimensional package structure. The micro pump 3 may be implemented using micro electro mechanical system technology or may be implemented using a micro electronic pump according to the size of the package.
The three-dimensional package structure illustrated in fig. 1 includes 3-layer chips, but it should be understood by those skilled in the art that the present disclosure is not limited to the number of layers of chips included in the three-dimensional package structure. In addition, each layer of chip can be a package packaged by any packaging mode, such as a Fan-out (Fan-out), a chip-level package (CHIP SCALE PACKAGE, CSP) and the like, each package can be independently manufactured, each package can comprise one or more chips, and each package can also be an unpackaged bare chip. As long as the dimensions are appropriate and the conditions are satisfied, it is compatible with the three-dimensional package structure according to the embodiments of the present disclosure.
The micro flow channels 2 are made of a heat conductive material so that the coolant flowing in the micro flow channels 2 can absorb heat from the chip 1 through the micro flow channels 2, thereby achieving heat dissipation of the chip 1 through the circulation flow of the coolant. For example, the micro flow channel 2 may be made of at least one material selected from the group consisting of a metal, a semiconductor material, and the like. The metal may be copper, nickel, gold, silver, metal alloy, etc., and the semiconductor material may be silicon, silicon carbide, etc.
The size of the micro flow channel 2 is comparable to the size of the interlayer electrical interconnections of the stacked chips 1. Thus, the preparation of the micro flow channel 2 and the preparation of the interlayer electrical interconnection, even the preparation of the integrated passive device (INTEGRATED PASSIVE DEVICES, IPD) structure, do not conflict with each other and can be performed cooperatively.
The thickness of the micro flow channel 2 may be in the range of 1 to 100 micrometers, for example, may vary from 10 micrometers or less to tens of micrometers. Thus, the preparation process of the micro flow channel 2 can be compatible with the existing silicon-based process and wafer-level process.
The micro flow channels 2 between the different stacks may be connected by means of Through-mould vias (Through Molding Via, TMV) and/or Through-chip vias (TDV) to be commonly connected to coolant inlets and outlets connected to the micro pump 3. Therefore, the micro-channels 2 among different lamination layers integrally form a circulation loop, which is beneficial to heat dissipation of the three-dimensional packaging structure. For example, in fig. 1, the black region is a mold, the gray region is a metal layer for forming interlayer electrical interconnections, through holes are formed in the mold, and micro flow channels between the respective layers are interconnected with the micro pump 3 through the through holes. It will be appreciated by those skilled in the art that the via structure shown in fig. 1 is merely an example and is not limiting of the present disclosure.
The micropump 3 may be integrated at the very top or very bottom of the three-dimensional package structure. In this way, the micro pump 3 can push the coolant to circulate in all micro channels 2, and is also beneficial to optimizing the three-dimensional packaging structure, so that the three-dimensional packaging structure is more compact.
The micropump 3 may be combined with a heat sink of a three-dimensional package structure. Thus, the three-dimensional package structure can be made more compact.
By adopting the technical scheme, as the micro-flow channel is integrated in the three-dimensional packaging structure, the three-dimensional packaging structure provides possibility for three-dimensional stacking of more layers, and can greatly improve the heat dissipation capacity of the three-dimensional packaging structure, thereby effectively reducing the working temperature of the functional chip, improving the upper power limit of the functional chip, and compared with other existing heat dissipation modes, the three-dimensional packaging structure has the advantages of lower shape factor, lower cost, stronger universality and the like. In addition, through the micro-channel graphic design, the IPD is allowed to be integrated, and meanwhile, a solution is provided for enhancing the heat dissipation capacity aiming at hot spots. The three-dimensional packaging structure can be manufactured by adopting a wafer-level manufacturing process compatible with a silicon-based manufacturing process, and the mass production capacity and the process stability are ensured.
Fig. 2 illustrates yet another schematic side view of a three-dimensional package structure according to one embodiment of the present disclosure. As shown in fig. 2, the three-dimensional package structure further includes a dielectric 4 filled between the micro flow channels 2 and the interlayer electrical interconnections of the stacked chips 1 for preventing short circuits or crosstalk. The dielectric 4 may be made of any non-conductive material. The layout of dielectric 4 shown in fig. 2 is merely an example and does not constitute a limitation of the present disclosure.
With further reference to fig. 2, the three-dimensional package structure further comprises a carrier 5 for carrying the entire three-dimensional package structure.
Fig. 3 shows a flow chart of a method of fabricating a three-dimensional package structure according to one embodiment of the present disclosure. The method is used to prepare a three-dimensional package structure as described above with reference to fig. 1 and 2. As shown in fig. 3, the method includes:
In step S31, micro flow channels and interlayer electrical interconnections are prepared on at least one side of each layer of chips;
in step S32, bonding the chips of each layer to obtain a three-dimensional package, and
In step S33, the three-dimensional package is connected to the micro pump.
By adopting the technical scheme, as the micro-flow channel is integrated in the three-dimensional packaging structure, the three-dimensional packaging structure provides possibility for three-dimensional stacking of more layers, and can greatly improve the heat dissipation capacity of the three-dimensional packaging structure, thereby effectively reducing the working temperature of the functional chip, improving the upper power limit of the functional chip, and compared with other existing heat dissipation modes, the three-dimensional packaging structure has the advantages of lower shape factor, lower cost, stronger universality and the like. In addition, through the micro-channel graphic design, the IPD is allowed to be integrated, and meanwhile, a solution is provided for enhancing the heat dissipation capacity aiming at hot spots. The preparation method of the three-dimensional packaging structure uses a wafer-level manufacturing process compatible with a silicon-based preparation process, and ensures batch production capacity and process stability.
Fig. 4a-4h illustrate in side view a flow chart of a method of fabricating a three-dimensional package structure according to an embodiment of the present disclosure.
First, as shown in fig. 4a, the chip 1 and the first carrier 5 are temporarily bonded to obtain a temporarily bonded package. Wherein the chip 1 may be temporarily bonded to the first carrier 5 using metal bonding or hybrid bonding. The first carrier 5 is used to support the chip 1 during the three-dimensional packaging process.
Then, as shown in fig. 4b, a mold 6 is formed on the temporary bonding package and a rewiring layer 7 and a via hole 8 are prepared. The mold 6, the rewiring layer 7, the through holes 8, and the like can be prepared by existing preparation processes, so that the preparation method of the three-dimensional package structure according to the embodiment of the present disclosure is more compatible.
Then, as shown in fig. 4c, the micro flow channels 2 and the interlayer electrical interconnections are prepared on the temporary bonding package in which the rewiring layer and the through holes are formed. In fig. 4c, only a part, for example, half of the micro flow channels 2 are prepared, and when the chips of the respective layers are bonded in the subsequent step, the micro flow channels prepared on the chips of the respective layers are also bonded to each other, thereby forming a completely closed micro flow channel structure. Of course, it is also possible to prepare a completely closed micro flow channel structure on each layer of chips in fig. 4 c. The micro flow channel 2 can be prepared by at least one of electroplating, etching and physical vapor deposition.
With further reference to fig. 4c, in this step, a charging medium 4 may also be filled between the micro fluidic channel 2 and the inter-layer electrical interconnect for preventing shorting and cross talk. The dielectric 4 may be prepared using at least one of electroplating, etching, physical vapor deposition.
Then, as shown in fig. 4d, a second carrier is bonded on the micro flow channel, the interlayer electrical interconnect.
Then, the first carrier is de-bonded from the chip as shown in fig. 4 e. In this way, the temporary bond package is transferred from the first carrier to the second carrier by the operations of fig. 4d and 4e, so that the preparation of micro flow channels, inter-layer electrical interconnections, etc. on the other side of the chip 1 can be continued.
Then, as shown in fig. 4f, a micro flow channel and an interlayer electrical interconnect are prepared on the other side of the chip 1.
Then, as shown in fig. 4g, the bonding of the two structures of fig. 4c and 4f will be completed, so that the bonding of the chips of different layers can be achieved. After bonding, the second carrier is debonded, and the debonded structure continues to bond with the structure shown in fig. 4f or fig. 4c, and the repetition is performed, so that a multilayer chip stack can be achieved.
Then, if the laminated chips are connected to the micro pump 3 as shown by 4h, the preparation of the three-dimensional package structure is completed. The three-dimensional package structure shown in fig. 4h includes 3-layered chips 1. In fig. 4h, the micro pump 3 is located at the top of the three-dimensional package structure, and the micro channels 2 between different layers are connected through holes (e.g., mold through holes and/or chip through holes) and commonly connected to a coolant inlet and outlet connected to the micro pump 3. In practical applications, however, the location of the micropump 3 may be arranged according to an actual three-dimensional package structure, for example, may also be located at the bottommost, middle, etc. of the three-dimensional package structure. Alternatively, the micropump 3 may be combined with a heat sink of a three-dimensional package structure.
By the preparation flow of fig. 4a to 4h, three functions of mechanical connection, electrical interconnection and heat dissipation structure preparation can be completed through one step of wafer level bonding, so that the three-dimensional package structure preparation method according to the embodiment of the disclosure is more suitable for use.
The preferred embodiments of the present disclosure have been described in detail above with reference to the accompanying drawings, but the present disclosure is not limited to the specific details of the embodiments described above, and various simple modifications may be made to the technical solutions of the present disclosure within the scope of the technical concept of the present disclosure, and all the simple modifications belong to the protection scope of the present disclosure.
In addition, the specific features described in the above embodiments may be combined in any suitable manner without contradiction. The various possible combinations are not described further in this disclosure in order to avoid unnecessary repetition.
Moreover, any combination between the various embodiments of the present disclosure is possible as long as it does not depart from the spirit of the present disclosure, which should also be construed as the disclosure of the present disclosure.
Claims (8)
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| KR20100100301A (en) * | 2009-03-06 | 2010-09-15 | 주식회사 하이닉스반도체 | Semiconductor package |
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| US8563365B2 (en) * | 2011-03-09 | 2013-10-22 | Georgia Tech Research Corporation | Air-gap C4 fluidic I/O interconnects and methods of fabricating same |
| CN106449569B (en) * | 2016-10-24 | 2018-11-23 | 华进半导体封装先导技术研发中心有限公司 | Laminated chips fluid channel radiator structure and preparation method |
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