CN113012731B - Data latch circuit structure suitable for large bit width CAM - Google Patents
Data latch circuit structure suitable for large bit width CAM Download PDFInfo
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- CN113012731B CN113012731B CN202110222865.2A CN202110222865A CN113012731B CN 113012731 B CN113012731 B CN 113012731B CN 202110222865 A CN202110222865 A CN 202110222865A CN 113012731 B CN113012731 B CN 113012731B
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- G—PHYSICS
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- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
- G11C7/106—Data output latches
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- G—PHYSICS
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- G11C16/00—Erasable programmable read-only memories
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Abstract
The invention provides a data latch circuit structure diagram suitable for a large-bit-width CAM, which completes the latch function of large-bit-width CAM port data by adopting a latch pulse signal generated by a CAM internal self-timing circuit to cooperate with a set of latches of a data port.
Description
Technical Field
The invention relates to the technical field of microelectronics and memory, in particular to a data latch circuit structure suitable for a large-bit-width CAM.
Background
CAM (Content Accessible Memory, content addressable memory) can compare stored data with data to be compared in full parallel, and realize single cycle searching function, so that the CAM (CAM) has high speed and wide application. The method is mainly used in various high-speed searching applications, such as Data Accelerators (DA), translation look-aside buffers (TLB) in a virtual storage system, data compression, image extraction, and network intrusion monitoring and bioinformatic systems, so as to respectively realize real-time pattern matching and gene pattern searching. Currently, the most prominent commercial application of CAM is to classify and forward IP packets in network routers. In the above application environment, the data size of a single piece of information of a system to which the hardware search engine belongs is usually large, and the CAM adopts a data port with wider data bits, so that the problems of huge latch units, complex structure, large flip power consumption and the like of a large-bit broadband which need to be solved in the CAM design are solved. FIG. 1 is a schematic diagram of a typical CAM circuit architecture, the entire circuit consisting of 7 main blocks of CAM memory array, address decoding, input latching, read/write/inquiry drive circuits, matching circuits, encoder and timing control logic.
In a synchronous timing system, external data is input and then sent to an internal circuit after being synchronized by a timing element, and the most commonly used timing element is a latch and a flip-flop at present.
The most common technique for existing latches is to take the form of pass gate multiplexing switches, as shown in figure 2. A positive level sensitive latch consisting of 1 transmission gate. The latch is transparent when the clock CLK is high, so that external data D reaches the output terminal Q through it; when CLK falls low, the latch becomes opaque, at which time a feedback path is established along a pair of inverters within the latch, allowing the current output Q state to be maintained at all times. Thus, for a particular one of the inputs D, the latch must meet the setup and hold time requirements near the falling edge when the clock goes from high to low for proper sampling.
Thus, the positive level pulse width of the clock increases the retention time of the latch, requiring the input data D to be issued after the rising edge of the clock but must be held after the falling edge. Therefore, the common latch is adopted to latch CAM input data, so that the holding time required by the data is relatively long, once the holding time is found to be invalid after the design is completed, the system can only be solved by redesigning logic but not slowing down clocks, and the design iteration is high in cost, time-consuming and labor-consuming.
The master-slave positive edge trigger structure formed by two stages of latches is shown in fig. 3, wherein the first stage of latches is called a master latch, and the second stage is a slave latch. When CLK is low, the output QM of the low transparent master latch changes with input D, while the high transparent slave latch Q holds its original value; when the clock transitions from 0 to 1, the master latch becomes opaque, QM remains at the D value before the clock transitions, and the slave latch becomes transparent, transferring the value held at the QM end of the master latch to the slave latch output Q, at which point the master latch has been disconnected from the current input D, the change in D does not affect the Q output.
In the manner that the CAM input data port adopts the trigger to register data, compared with a latch, the number of transistors used for clock driving is doubled, the capacitance load of a clock signal becomes heavy, and especially in the case of a large-bit-width data port, the data latch structure becomes huge and complex, which directly influences the load of a clock network and the flip-flop power consumption.
Disclosure of Invention
Aiming at the problems that in the prior art, a mode of carrying out data registration on a CAM input data port by adopting a trigger causes the capacitance load of a clock signal to become heavy and the load of a data latch structure cannot meet the requirement of large-bit-width data, the invention provides the data latch circuit structure suitable for the large-bit-width CAM, which has the advantages of simple structure, self-adaptation of latching pulse width and memory speed, stability and reliability and meets the latching function of large-bit-width CAM port data.
The invention is realized by the following technical scheme:
a data latch circuit structure suitable for large bit width CAM includes a clocked latch, a latch pulse generating circuit and an analog bit line feedback loop; the input end of the latch pulse generating circuit is connected with an external clock, and the output initial pulse of the latch pulse generating circuit returns to an initial state through a feedback pulse after passing through an analog bit line feedback loop to form a complete pulse signal; the analog bit line feedback loop includes an analog bit line; a plurality of dummy memory cells are mounted on the analog bit line and used for simulating the discharging process of the bit line by the capacitive load on the bit line; the latch port of the latch pulse generating circuit generates a data latch pulse by a read-write enabling signal and sends the data latch pulse to the clock latch of the CAM data port.
Preferably, the number of dummy memory cells mounted on the analog bit line is the same as the number of actual memory cells on one bit line in the memory array.
Preferably, the discharge rate of the analog bit line is equal to the actual bit line in the memory array.
Preferably, the width of the latch pulse varies equally with the discharge variation of the actual bit line in the memory array.
Preferably, the port latch of the latch pulse generating circuit employs a clocked latch.
Preferably, the feedback signal pulse generated by the analog bit line corresponds to the setting of the read-write access time of the CAM memory to the memory array, so that the data of the CAM memory is written and read normally.
Preferably, the dummy cell load on the analog bit line is adapted to different voltages, temperatures and process corner operating conditions to generate different discharge times for the initial pulse for determining the latch time of the feedback signal pulse on the analog bit line matched with the read-write access time of the CAM memory.
Compared with the prior art, the invention has the following beneficial technical effects:
the invention provides a data latch circuit structure diagram suitable for a large-bit-width CAM, which completes the latch function of large-bit-width CAM port data by adopting a latch pulse signal generated by a CAM internal self-timing circuit to cooperate with a set of latches of a data port.
Drawings
FIG. 1 is a prior art CAM circuit architecture;
FIG. 2 is a prior art latch circuit configuration implemented using pass gate multiplexing;
FIG. 3 is a master-slave positive edge flip-flop constructed of two stages of latches in the prior art;
FIG. 4 is a block diagram of a data latch circuit suitable for use in a large bit width CAM in accordance with the present invention;
FIG. 5 is a diagram showing internal signal relationships in a data latch circuit configuration suitable for large bit width CAM according to the present invention;
fig. 6 is a functional block diagram of a data latch circuit architecture suitable for use in a large bit width CAM.
Detailed Description
The invention will now be described in further detail with reference to specific examples, which are intended to illustrate, but not to limit, the invention.
The invention provides a data latch circuit structure suitable for large bit width CAM, as shown in figure 4, comprising a clock latch, a latch pulse generating circuit and an analog bit line feedback loop; the input end of the latch pulse generating circuit is connected with an external clock, and the output initial pulse of the latch pulse generating circuit returns to an initial state through a feedback pulse after passing through an analog bit line feedback loop to form a complete pulse signal; the analog bit line feedback loop includes an analog bit line; a plurality of dummy memory cells are mounted on the analog bit line and used for simulating the discharging process of the bit line by the capacitive load on the bit line; the latch port of the latch pulse generating circuit generates a data latch pulse by a read-write enabling signal and sends the data latch pulse to the clock latch of the CAM data port.
The number of the dummy memory cells mounted on the analog bit line is the same as the number of the actual memory cells on one bit line in the memory array; the discharge speed of the analog bit line is equal to that of the actual bit line in the memory array; the width change of the latch pulse is equal to the discharge change of the actual bit line in the memory array; the port latch of the latch pulse generating circuit adopts a clocked latch.
According to fig. 5, an initial pulse is first generated at the time t of the rising edge of the external clock, then the initial pulse is discharged through the feedback loop and then pulled up to the initial state, thereby generating a feedback pulse (low-active) with a width tP, and finally, based on the feedback pulse, the latch pulse generating circuit generates a latch pulse for latching data in combination with read/write enable signals of other CAMs.
The analog bit line is provided with the dummy memory cells with the same number as one bit line in the memory array, the dummy memory cells have no actual memory function, and only serve as capacitive load on the bit line to simulate the bit line discharging process, and the analog bit line has the same discharging speed as the actual bit line in the memory array, so that the generated feedback signal pulse meets the requirement of the CAM memory on the access period of the memory array. And finally, the latch pulse generating circuit generates a final data latch pulse by utilizing the feedback signal pulse and combining the related read-write enabling signal, and sends the final data latch pulse to a clock latch of the CAM data port for latching external data, wherein the internal data of the CAM is not changed along with the external data in the latch period.
The port latch of the invention only uses one clock-controlled latch, which is simpler than the flip-flop in the prior art; the latching time is determined by feedback of the analog bit line, so that the sufficient and shortest CAM read-write access period is ensured; because the analog bit line adopts dummy units with the same number as the memory array as a load, the width of the latch pulse is consistent with the discharge time variation of the actual bit line in the memory array along with the environmental variation of temperature, voltage and the like, thereby ensuring the reliability of the operation.
And the feedback signal pulse generated by the analog bit line corresponds to the setting of the read-write access time of the CAM memory to the memory array, so that the data of the CAM memory are normally written in and read out. The dummy unit load on the analog bit line is self-adaptive to working conditions of different voltages, temperatures and process angles to generate different discharge times for the initial pulse, and the different discharge times are used for determining the latch time of the feedback signal pulse on the analog bit line matched with the read-write access time of the CAM memory.
Examples
As shown in fig. 6, the DATA latch circuit structure applied to the large-bit-width CAM of the present invention is applied to the CAM function block diagram, the DATA port DATA bit width of the CAM is n, and the address bit width is m. The read-write data is latched by n latches of the data port and then connected with a read-write control circuit, and the read-write control circuit reads or writes the read-write data into a corresponding bit line in the memory array. And simultaneously, the external address ADD [ m & lt 1 & gt controls the corresponding word line to be opened after address decoding, so that data is read out or written into the corresponding memory cell through the bit line.
When the read-write is started, the pulse latch circuit initiates an initial pulse according to the arrival of the rising edge of the external clock. At this time, an analog bit line feedback loop formed by connecting a row of dummy memory cells having no memory function to bit lines starts to discharge to clock the latch pulse generating circuit, and the initial pulse is pulled back to the initial state after the discharge is completed, thereby forming a complete feedback pulse signal. The latch pulse generating circuit processes the feedback pulse signal and sends the feedback pulse signal to the latches of the n data ports to complete the latching of the port data, thereby ensuring the stability of the data on the bit lines in the CAM read-write period.
Claims (6)
1. A data latch circuit structure suitable for large bit width CAM, comprising a clocked latch, a latch pulse generating circuit and an analog bit line feedback loop; the input end of the latch pulse generating circuit is connected with an external clock, and the output initial pulse of the latch pulse generating circuit returns to an initial state through a feedback pulse after passing through an analog bit line feedback loop to form a complete pulse signal; the analog bit line feedback loop includes an analog bit line; a plurality of dummy memory cells are mounted on the analog bit line and used for simulating the discharging process of the bit line by the capacitive load on the bit line; the latch port of the latch pulse generating circuit generates a data latch pulse through a read-write enabling signal and sends the data latch pulse to the clock latch of the CAM data port;
the number of the dummy memory cells mounted on the analog bit line is the same as the number of the actual memory cells on one bit line in the memory array.
2. A data latch circuit structure for a large bit width CAM according to claim 1 wherein the discharge rate of the analog bit line is equal to the discharge rate of the actual bit line in the memory array.
3. A data latch circuit structure for a large bit width CAM according to claim 1 wherein the width of the latch pulse varies equally with the discharge variation of the actual bit line in the memory array.
4. A data latch circuit structure for a large bit width CAM as in claim 1 wherein the port latch of said latch pulse generating circuit employs a clocked latch.
5. The data latch circuit structure according to claim 1, wherein the feedback signal pulse generated by the analog bit line corresponds to a setting of a read-write access time of the CAM memory to the memory array, so that data of the CAM memory is written and read normally.
6. The data latch circuit structure according to claim 1, wherein the dummy cell load on the analog bit line is adapted to different voltages, temperatures and process corner operating conditions to generate different discharge times for the initial pulse for determining the latch time of the feedback signal pulse on the analog bit line matched with the read-write access time of the CAM memory.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202110222865.2A CN113012731B (en) | 2021-02-26 | 2021-02-26 | Data latch circuit structure suitable for large bit width CAM |
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| CN202110222865.2A CN113012731B (en) | 2021-02-26 | 2021-02-26 | Data latch circuit structure suitable for large bit width CAM |
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| CN113012731B true CN113012731B (en) | 2023-05-09 |
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| US6678196B2 (en) * | 2001-07-06 | 2004-01-13 | Micron Technology, Inc. | Writing to and reading from a RAM or a CAM using current drivers and current sensing logic |
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2021
- 2021-02-26 CN CN202110222865.2A patent/CN113012731B/en active Active
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| CN101552600A (en) * | 2008-04-01 | 2009-10-07 | 阿尔特拉公司 | Robust time borrowing pulse latches |
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