CN112799599B - A data storage method, computing core, chip and electronic device - Google Patents

Abstract

The present disclosure relates to a data storage method, a computing core, a chip and an electronic device, the method is applied to a computing core of a processor, each computing core includes a processing part and a storage part, and the storage part includes two or more storage units. The processing component sequentially writes the weight data and processing data of each convolution layer into each storage unit for storage according to the processing order of the convolution layers in the multi-layer convolution operation process; each storage unit receives and stores the weight data and the processing data. the processed data. In addition, the adjacent layer data can be dynamically covered while calculating, which increases the remaining continuous dynamic available space, frees up more data space for subsequent calculations, improves the space-time operation efficiency of the computing core, and thus improves the chip performance.

Description

A data storage method, computing core, chip and electronic device

technical field

The present disclosure relates to the field of neuromorphic engineering, and in particular, to a data storage method, a computing core, a chip and an electronic device.

Background technique

The convolution operation is a common operation in neural networks. In the process of mapping, the many-core neuromorphic chip stores and transmits the data that needs to be subjected to convolution operations. These data can be divided into static data and dynamic data, among which, static data is not erasable, and dynamic data can be continuously erased. The memory space occupied by static data in the chip is relatively fixed and cannot be overwritten. The memory space occupied by dynamic data in the chip can be changed and overwritten according to the timing requirements. Static data may include the weights of the convolution kernels of the neural network, and dynamic data may include processing data.

In the process of data storage and transmission, it is easy to generate coverage and destruction of data in the overlapping area. Even if the data is first moved to stagger the overlapping area and then sent, the computing clock will be increased and the computing efficiency of the chip will be reduced. The memory access of the chip takes a long time, occupies a large space capacity, and the dynamic reuse efficiency is low.

SUMMARY OF THE INVENTION

In view of this, the present disclosure proposes a data storage method, a computing core, a chip and an electronic device.

According to an aspect of the present disclosure, a data storage method is provided, which is applied to a computing core of a processor, the processor includes a plurality of computing cores, each computing core includes a processing component and a storage component, wherein the storage component Include more than two storage units.

The method includes: the processing unit sequentially writes the weight data and processing data of each convolution layer into each storage unit for storage according to the processing order of the convolution layers in the multi-layer convolution operation process; receiving and storing the weight data and the processing data;

Wherein, in the storage unit, the processing data and weight data of the same convolution layer are stored in different storage units; in the same storage unit, the weight data space for storing the weight data and the processing data for storing the processing data are stored in the same storage unit. The data space is arranged in sequence according to the first address direction;

Among them, the weight data space for storing the weight data of each convolution layer is arranged in the first address direction according to the processing order of the convolution layer; the processing data space for storing the processing data of each convolution layer is according to the processing order of the convolution layer, Discharge in sequence along the first address direction;

Among them, in the weight data space storing the weight data of the same convolution layer and the processing data space storing the processing data of the same convolution layer, the weight data and the processing data are arranged in sequence according to the second address direction, and the first address The direction is opposite to the direction of the second address.

In a possible implementation manner, the first address direction is a high address to low address direction, and the second address direction is a low address to high address direction.

In a possible implementation, the method further includes:

The processing component sends the operation result data of each convolution layer in the multi-layer convolution operation process into each storage unit for storage;

Each storage unit receives and stores the operation result data, wherein the operation result data of any convolution layer and the processing data of the convolution layer are stored in the same storage unit, and are shared with the processing data of the next convolution layer. space.

In a possible implementation, the method further includes:

The processing component writes first data received from outside the computing core to a storage unit, and reads second data from the storage unit to send to the outside of the computing core;

Wherein, in multiple write operations, the start addresses of each write operation are arranged in the direction of the first address, and the first data is written in the direction of the second address in each write operation;

In multiple read operations, the start addresses of each read operation are arranged in the direction of the first address, and the second data is read in the direction of the second address in each read operation.

In a possible implementation manner, in the storage unit, the storage order of the processing data and weight data for each convolutional layer conforms to the convolution operation process of depth direction first, then horizontal direction, and then vertical direction.

In a possible implementation manner, each layer of convolution operation process uses multiple convolution kernel groups, and each convolution kernel group includes multiple convolution kernels;

In the storage unit, the weight data of each convolution kernel group in the convolution operation of each layer is stored in sequence, and the storage order of the weight data of each convolution kernel group is according to the numbering order of the convolution kernel, the convolution kernel The kernel depth direction, horizontal direction, and vertical direction are stored.

According to another aspect of the present disclosure, a computing core is provided, the computing core includes a processing component and a storage component;

The processing unit sequentially writes the weight data and processing data of each convolution layer into each storage unit for storage according to the processing order of the convolution layers in the multi-layer convolution operation process;

The storage unit includes two or more storage units, and each storage unit receives and stores the weight data and the processing data;

Wherein, in the storage unit, the processing data and weight data of the same convolution layer are stored in different storage units; in the same storage unit, the weight data space for storing the weight data and the processing data for storing the processing data are stored in the same storage unit. The data space is arranged in sequence according to the first address direction;

Among them, the weight data space for storing the weight data of each convolution layer is arranged in the first address direction according to the processing order of the convolution layer; the processing data space for storing the processing data of each convolution layer is according to the processing order of the convolution layer, Discharge in sequence along the first address direction;

Among them, in the weight data space storing the weight data of the same convolution layer and the processing data space storing the processing data of the same convolution layer, the weight data and the processing data are arranged in sequence according to the second address direction, and the first address The direction is opposite to the direction of the second address.

For the above computing core, in a possible implementation manner, the first address direction is a high address to low address direction, and the second address direction is a low address to high address direction.

For the above computing core, in a possible implementation manner, the processing component is further configured to send the operation result data of each convolution layer in the multi-layer convolution operation process into each storage unit for storage;

Each storage unit receives and stores the operation result data, wherein the operation result data of any convolution layer and the processing data of the convolution layer are stored in the same storage unit, and are shared with the processing data of the next convolution layer. space.

For the above computing core, in a possible implementation manner, the processing component is further configured to write the first data received from outside the computing core into the storage unit, and read the second data from the storage unit to send the data to the storage unit. The calculation is sent out of the core;

Wherein, in multiple write operations, the start addresses of each write operation are arranged in the direction of the first address, and the first data is written in the direction of the second address in each write operation;

In multiple read operations, the start addresses of each read operation are arranged in the direction of the first address, and the second data is read in the direction of the second address in each read operation.

For the above calculation kernel, in a possible implementation manner, in the storage unit, the storage order of the processing data and the weight data for each convolutional layer conforms to the depth direction first, then the horizontal direction, and then the vertical convolution. operation process.

For the above calculation kernel, in a possible implementation manner, each layer of convolution operation process uses multiple convolution kernel groups, and each convolution kernel group includes multiple convolution kernels;

In the storage unit, the weight data of each convolution kernel group in the convolution operation of each layer is stored in sequence, and the storage order of the weight data of each convolution kernel group is according to the numbering order of the convolution kernel, the convolution kernel The kernel depth direction, horizontal direction, and vertical direction are stored.

According to another aspect of the present disclosure, there is provided an artificial intelligence chip including a plurality of computing cores.

According to another aspect of the present disclosure, there is provided an electronic device including one or more artificial intelligence chips.

According to the embodiments of the present disclosure, by storing the weight data and the processing data respectively in the weight data space and the processing data space of each storage unit according to the processing order of the convolution layer according to the first address direction, the data of adjacent convolution layers can be processed. Dynamic coverage while computing increases the remaining continuous dynamic free space and frees up more data space for subsequent computing. The weight data and processing data of the same convolutional layer are stored in order according to the second address direction, which can highly match the convolution operation process of depth, then horizontal, and then vertical, and improve the fit between the storage process and the convolution operation process. Spend. In the case where the address of the data to be sent and the address of the data to be received in the storage unit overlap, by arranging the starting addresses of each read and write operation in the multiple read and write operations according to the first address direction, it is possible to solve the problem because At the same time, multiple read and write operations performed by the processing unit result in the destruction and coverage of the data in the overlapping area of the storage unit, which improves the space-time operation efficiency of the computing core, thereby improving the performance of the chip.

Other features and aspects of the present disclosure will become apparent from the following detailed description of exemplary embodiments with reference to the accompanying drawings.

Description of drawings

The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate exemplary embodiments, features, and aspects of the disclosure, and together with the description, serve to explain the principles of the disclosure.

FIG. 1 shows a schematic diagram of a computing core according to an embodiment of the present disclosure.

Figure 2a shows a schematic diagram of data storage in the related art.

FIG. 2b shows a schematic diagram of data storage according to an embodiment of the present disclosure.

FIG. 3 shows a flowchart according to an embodiment of the present disclosure.

FIG. 4a shows a schematic diagram of data transmission in a storage unit in the related art.

FIG. 4b shows a schematic diagram of data transmission according to an embodiment of the present disclosure.

FIG. 5 shows a flowchart according to an embodiment of the present disclosure.

FIG. 6 shows a schematic diagram of a processing data storage sequence according to an embodiment of the present disclosure.

FIG. 7 is a schematic diagram illustrating a storage sequence of weight data according to an embodiment of the present disclosure.

FIG. 8 is a schematic diagram showing the principle of storage order of a convolution operation process according to an embodiment of the present disclosure.

FIG. 9 shows a block diagram of an electronic device according to an embodiment of the present disclosure.

FIG. 10 shows a block diagram of an electronic device according to an embodiment of the present disclosure.

Detailed ways

The technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, but not all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those skilled in the art without creative efforts shall fall within the protection scope of the present disclosure.

It should be understood that the terms "first", "second", "third" and "fourth" in the claims, description and drawings of the present disclosure are used to distinguish different objects, rather than to describe a specific order . The terms "comprising" and "comprising" as used in the specification and claims of the present disclosure indicate the presence of the described feature, integer, step, operation, element and/or component, but do not exclude one or more other features, integers , step, operation, element, component and/or the presence or addition of a collection thereof.

It should also be understood that the terminology used in the present disclosure is for the purpose of describing particular embodiments only and is not intended to limit the present disclosure. As used in this disclosure and the claims, the singular forms "a," "an," and "the" are intended to include the plural unless the context clearly dictates otherwise. It should further be understood that, as used in this disclosure and the claims, the term "and/or" refers to and including any and all possible treatments of one or more of the associated listed items.

As used in this specification and in the claims, the term "if" may be contextually interpreted as "when" or "once" or "in response to determining" or "in response to detecting". Similarly, the phrases "if it is determined" or "if the [described condition or event] is detected" may be interpreted, depending on the context, to mean "once it is determined" or "in response to the determination" or "once the [described condition or event] is detected. ]" or "in response to detection of the [described condition or event]".

It should also be understood that, as a container for storing data, a tensor can be regarded as a multidimensional array. Image data, as well as other perceptual data (eg, audio, video, etc.), can be represented as multidimensional tensors and stored in memory in binary form. In order to facilitate the understanding of the technical solutions of the present disclosure, image data may be used as an example for processing data hereinafter. The image data used in this specification of the present disclosure is for the purpose of describing particular embodiments only, and is not intended to limit the present disclosure. The present disclosure is applicable to processing data including video, audio, images, etc., which may be stored in memory in binary form.

FIG. 1 shows a schematic diagram of a computing core according to an embodiment of the present disclosure. The data storage method according to the embodiment of the present disclosure is applied to a computing core of a processor, where the processor includes a plurality of computing cores.

As shown in FIG. 1, each computing core includes a processing unit and a storage unit. The processing components may include dendritic units, axonal units, soma units, and routing units. The storage unit may include two or more storage units, the storage units may be used to store the processing data and the weight data, the space in which the processing data is stored in the storage unit may be referred to as the processing data space, and the space in which the weight data is stored may be referred to as the processing data space. It is called the weight data space.

In a possible implementation manner, the processor may be a brain-like computing chip, that is, taking the processing mode of the brain as a reference, by simulating the transmission and processing of information by neurons in the brain, the processing efficiency is improved and the power consumption is reduced . The processor may include multiple computing cores, and the computing cores may independently process different tasks, such as convolution operation tasks, pooling tasks, or fully connected tasks, etc.; the same task may also be processed in parallel, that is, each computing The kernel can process different parts of the same task assigned, for example, the convolution operation task of some layers in the multi-layer convolutional neural network operation task. It should be noted that the present disclosure does not limit the number of computing cores in the chip and the tasks executed by the computing cores.

Within the computing core, processing means and storage means may be provided. Processing components may include dendritic units, axonal units, soma units, and routing units. The processing component can simulate the information processing mode of neurons in the brain, in which the dendritic unit is used to receive signals, the axonal unit is used to send spike signals, the cell body unit is used for integrated transformation of signals, and the routing unit is used to communicate with other computing cores. to transmit information. The processing unit in the computing core can perform read and write access to multiple storage units of the storage unit to perform data interaction with the storage unit in the computing core, and can respectively undertake their own data processing tasks and/or data transmission tasks to obtain data processing results, or communicate with other computing cores. The present disclosure does not limit the application fields of the processing components.

In a possible implementation manner, the storage component may include more than two storage units, and the storage units may be static random-access memory (Static Random-Access Memory, SRAM). For example, the storage unit may include an SRAM with a read/write width of 32B and a capacity of 64KB. The present disclosure does not limit the read/write width and capacity of the storage unit.

In a possible implementation manner, the storage unit includes a processing data space and a weight data space. Among them, the processing data space can be used to store dynamic data, that is, data that may change during operation, data that needs to be input and output during operation, and data to be changed during associated operations. The weight data space can be used to store static data, that is, data used for control or reference during program execution. Static data may not change as the program runs, so static data may not change for a long period of time. For example, for a convolutional neural network structure, the static data can be the weight data of the convolution operation, and the dynamic data can be the processing data, such as the input data of the convolution layer (for example, it can be the input data of the convolution layer that has undergone shortcut processing) , which can be erased and overwritten as the processing data changes. For example, in the process of hierarchical iterative calculation of the convolutional neural network structure, the processing data is constantly modified according to the needs of the time series, and the old processing data is overwritten with the new processing data.

According to the computing core of the embodiment of the present disclosure, the processing component and the storage component can be arranged in the computing core, so that the storage component directly receives the read and write access of the processing component, without reading and writing the storage component outside the computing core, and the memory is optimized. Read and write speed, suitable for processing components of many-core architecture.

In a possible implementation manner, the method can be used to realize the storage and transmission of data in the multi-layer convolution operation process, wherein the data in the multi-layer convolution operation process includes the data in the multi-layer convolution operation process processing data and weight data.

For example, when applying a neural network algorithm to target an image, a multi-layer convolution operation is performed on the input image processing data. The basic data structure of a neural network is a layer. Various neural networks, including deep neural network DNN, convolutional neural network CNN, recurrent neural network RNN, and deep residual network ResNet, are all organically combined by multiple layers. formed neural network. A layer can be understood as a data processing module. Different data processing types need to use different layers, and different layers have different layer attributes, that is, the weights of the layers. One input or multiple inputs can be converted into one or more outputs under the action of weights belonging to different layers.

If a neural network is a relatively small network, one computing core can satisfy the resources required for processing each layer of the neural network, and the processing data and weight data of the neural network can be stored in a computing core.

If it is a very large neural network, the neural network has many layers, each layer needs to calculate a large amount of data, and one computing core cannot meet the resources required to process the neural network. In this case, multiple computing cores are required to cooperate and work together To calculate this large neural network, the neural network can be divided into multiple parts and sent to the corresponding computing cores allocated by the processor for computing processing. For example, assuming that the neural network includes 7 convolutional layers L1-L7, the processor can assign the processing data and weight data of the L1 and L2 convolutional layers to the calculation core A for calculation, and the convolutional layers L3 and L2. The processing data and weight data of the L4 layer are allocated to the calculation core B for calculation, and the processing data and weight data of the convolutional layer L5 layer-L7 layer are allocated to the calculation core C for calculation. It should be noted that the present disclosure does not limit the types of neural networks that the computing cores run, and how the neural networks are split and allocated to different computing cores.

In the related art, when the processor stores the data in the multi-layer convolution operation in the storage unit, the processing data (dynamic data) and the weight data (static data) in the multi-layer convolution operation are stored in different storage units. Separate storage on the unit. That is to say, the processor stores the weight data in one storage unit, and stores the processing data in another storage unit.

Figure 2a shows a schematic diagram of data storage in the related art. As shown in Figure 2a, there are two storage units in the figure, namely: storage unit MEM0 and storage unit MEM1. The storage space capacity of each storage unit is 64KB, and the read-write bit width is For 32B, the weight data W during the multi-layer convolution operation is stored in the storage unit MEM0, and the processed data X is stored in the storage unit MEM1. The L5 layer, the L6 layer, and the L7 layer can represent the corresponding convolution layers of the multi-layer convolutional neural network in the operation process. When performing the convolution operation of each layer, it is performed in the order of L5 layer, L6 layer, L7 layer... .

The weight data of the L5 layer, L6 layer, and L7 layer are placed in the storage unit MEM0. According to the second address direction, the weight data W of the L5 layer in size of 8KB, the weight data W of the L6 layer in size of 18KB, and the size of 8KB are stored in sequence according to the second address direction. The L7 layer weight data W, the remaining continuous dynamic free space is 30KB. Wherein, the second address direction in this document may be a direction from a low address to a high address, and the continuous dynamic free space is a blank space where no data is stored.

The processing data of the L5 layer, the L6 layer, and the L7 layer are stored in another storage unit MEM1. According to the second address direction, the L5 layer processing data X of 28KB size, the L6 layer processing data X of 15KB size, and the processing data of 15KB size are stored in sequence according to the second address direction. The L7 layer processes data X, and the remaining continuous dynamic free space is 6KB.

When the convolution operation of the entire node unit of the L5 layer, L6 layer, and L7 layer is completed, it needs to be sent to other computing cores, and at the same time, the data sent by the computing core corresponding to the previous node unit is received. , therefore, the computing core cannot calculate the L6 layer and output the calculation result of the L6 layer to the L7 layer, while dynamically covering the data of the space occupied by the L6 layer.

Therefore, the processing data and weight data are arranged in the respective storage units according to the processing order of the convolution layer, and are arranged in the positive order of the storage units according to the second address direction, which will result in a low dynamic data reuse rate and a small remaining continuous space, which cannot be used for The same layer of data is dynamically covered while being calculated, which affects the storage space for subsequent calculations, and the storage process will be accompanied by the continuous transfer of data, increasing the computing time.

In view of the above-mentioned problems of data storage in the related art as shown in FIG. 2a, FIG. 3 shows a flowchart of a data storage method according to an embodiment of the present disclosure. The method shown in Figure 3 may include the following steps:

Step S1, the processing component sequentially writes the weight data and processing data of each convolution layer into each storage unit for storage according to the processing order of the convolution layers in the multi-layer convolution operation process.

Step S2, each storage unit receives and stores the weight data and the processing data.

In a possible implementation manner, in the same storage unit, the weight data space in which the weight data is stored and the processing data space in which the processing data is stored are arranged in sequence according to the first address direction. Herein the first address direction may be a high address to low address direction, the first address direction being opposite to the second address direction.

For example, FIG. 2 b shows a schematic diagram of data storage according to an embodiment of the present disclosure. As shown in FIG. 2 b , it is assumed that the storage component includes two storage units: a storage unit MEM0 and a storage unit MEM1 . Each memory cell can use SRAM with a read-write width of 32B and a capacity of 64KB. The L5 layer, the L6 layer, and the L7 layer can represent the corresponding convolution layers of the multi-layer convolutional neural network in the operation process.

As shown in Figure 2b, in the storage unit MEM0, according to the first address direction, the weight data space for storing 8KB static data W, the processing data space for storing 30KB (15KB+15KB) dynamic data X, and the remaining 40KB continuous dynamic free space.

As shown in FIG. 2b, in the storage unit MEM1, according to the first address direction, the weight data space for storing 26KB (18KB+8KB) of static data W, the processing data space for storing 28KB dynamic data X, and The remaining 10KB of continuous dynamic free space.

Each storage unit includes a processing data space that can store dynamic data and a weight data space that can store static data, and the weight data space that stores weighted data and the processing data space that stores processing data are in order according to the first address direction. Emissions can increase the remaining available continuous dynamic free space of the storage unit.

In a possible implementation manner, in the storage unit, the processing data and weight data of the same convolutional layer are stored in different storage units; the processing data and weight data of different convolutional layers may be stored in the same storage unit storage unit storage.

For example, as shown in Figure 2b, the processing component sends the weight data W of the L5 layer into the weight data space of the storage unit MEM0, and sends the processed data X of the L5 layer into the processing data space of the storage unit MEM1; The weight data W of the L6 layer is sent to the weight data space of the storage unit MEM1, the processing data X of the L6 layer is sent to the processing data space of the storage unit MEM0; the weight data W of the L7 layer is sent to the weight data space of the storage unit MEM1 In the value data space, the processing data X of the L7 layer is sent to the processing data space of the storage unit MEM0.

Since the processing data and weight data of the same convolution layer are stored in different storage units, the processing component can access multiple storage units in parallel to read the processing data and weight data, thereby improving the computing efficiency of the computing core.

In a possible implementation manner, the weight data space for storing the weight data of each convolutional layer is arranged in the first address direction according to the processing order of the convolutional layers; the processing data space for storing the processed data of each convolutional layer is According to the processing order of the convolution layer, they are sequentially arranged along the first address direction.

For example, as shown in FIG. 2b, the weight data W of the L5 layer and the processing data X of the L6 layer and the L7 layer are in the storage unit MEM0, and the weight data W of the L5 layer of 8KB in size can be stored in the first address direction. The L6 layer processing data X with a size of 15KB, the L7 layer processing data X with a size of 15KB, and the remaining continuous dynamic free space of 40KB.

The weight data W of the L6 layer and the L7 layer and the processing data X of the L5 layer can be stored in the storage unit MEM1 in sequence along the first address direction. , 28KB of L5 layer processing data X, and the remaining continuous dynamic free space of 10KB.

Compared with the remaining continuous dynamic free space of the storage unit MEM0 and the storage unit MEM1 in the related art of FIG. 2a 36KB (MEM0:30KB+MEM1:6KB), the remaining continuous dynamic free space of the storage unit MEM0 and the storage unit MEM1 in FIG. 2b is 50KB (MEM0 : 40KB+MEM1: 10KB), the continuous dynamic free space of the storage unit can be improved by adopting the method used in the embodiment of the present disclosure.

In a possible implementation manner, the processing component sends the operation result data of each convolution layer in the multi-layer convolution operation process to each storage unit for storage, and each storage unit receives and stores the operation result data . The operation result data of any convolutional layer and the processing data of the convolutional layer are stored in the same storage unit, and share the storage space with the processing data of the next convolutional layer.

For example, compared with the related technology shown in FIG. 2a, the processing data X of the L6 layer cannot be dynamically covered while being calculated, and the space occupied by the L6 layer cannot be dynamically covered while outputting the operation result data of the L6 layer as the processed data X of the L7 layer. The processing data X of the L6 layer stored in . As shown in Figure 2b, the processing unit can dynamically cover the processing data X of the L6 layer in the storage unit MEM0 while calculating, and the convolution operation result data of the L6 layer can be used as the processing data X of the L7 layer. The result directly covers the processed data X of the L6 layer that has been processed as the processed data X of the L7 layer, that is, the result data of the L6 layer convolution operation can share the storage space with the processed data X of the adjacent L7 layer, and reuse the storage space. An area of a cell that makes enough space for subsequent computations.

Therefore, in the method, by setting the weight data space and the processing data space for the storage unit, under the condition that the processing data and weight data of the same layer are sent to different storage units for storage, the weight value can be stored according to the processing order of the convolution layer. The data space and the processing data space store weight data and processing data respectively according to the first address direction, and can dynamically cover the adjacent layer data while calculating, which increases the remaining continuous dynamic free space and frees up more space for subsequent calculations. It can improve the space-time operation efficiency of the computing core and improve the performance of the chip.

In the related art, when the multi-layer convolution operation and storage are performed on the processing data by the calculation core, when the calculation of the convolution data of one layer is completed and the calculation of the next layer is entered, the data that the calculation core has calculated this time needs to be sent to other calculations. The core is stored, and at the same time, the data of the previous layer of convolution operation is received. Often receiving and sending data are in the same piece of storage space, which may be accompanied by overlapping spaces.

FIG. 4a shows a schematic diagram of data transmission in a storage unit in the related art. As shown in Figure 4a, the capacity of the data to be received by the storage unit MEM1 is 28KB, the capacity of the data to be sent is 28KB, and the overlapping space capacity of the address of the data to be sent and the address of the data to be received is 14KB, that is, the address of the storage unit MEM1 is Data space from 0x5400 to 0x6200.

If the forward-sequence transmission method is adopted from the data space to be sent and the data space to be received in the storage unit, that is, in the multiple read and write operations of the processing unit to the storage unit, the starting address of each read and write operation is based on the second address. Orientation arrangement. The first data with a data capacity of 12KB received by the storage unit MEM1 for the first time (corresponding to the data space of the storage unit MEM1 with an address of 0x5400~0x6000) will change the second data to be sent for the second time (corresponding to the storage unit MEM1 with an address of 0x5200~ 0x5E00 data space) is destroyed and overwritten, and the corresponding storage unit MEM1 address of the destroyed part is 0x5400~0x5E00. As a result, the subsequent second data to be sent is erroneous data.

Wherein, the first data may be data to be received by a storage unit that occurs in a write operation to the storage unit; the second data may be data to be sent to a storage unit that occurs in a read operation to the storage unit.

If the data in the data area that needs to be sent is first moved upwards and moved 14KB of space, so that there is no overlap between the two. Then, the data is sent in sequence according to the second address direction, which will also increase the transmission delay and the calculation clock due to the increased movement of the data process, thereby increasing the operating burden of the chip and reducing the operating efficiency of the chip.

In a possible implementation manner, the processing component may write the first data received from outside the computing core into a storage unit, and read the second data from the storage unit to send to the outside of the computing core.

In multiple write operations, the start addresses of each write operation are arranged in the direction of the first address, and the first data is written in the direction of the second address in each write operation.

In multiple read operations, the start addresses of each read operation are arranged in the direction of the first address, and the second data is read in the direction of the second address in each read operation.

For example, FIG. 4b shows a schematic diagram of data transmission according to an embodiment of the present disclosure. As shown in FIG. 4b , the starting address of the second data of 12 KB to be sent by the storage unit MEM1 for the first time is 0x5600, and the starting address of the first data of 12 KB to be received for the first time is 0x6400. The starting address of the second data with a capacity of 12KB to be sent for the second time is 0x4A00, and at the same time, the starting address of the first data with a capacity of 12KB to be received for the second time is 0x5800. The starting address of the second data with a capacity of 4KB to be sent for the third time is 0x4600, and at the same time, the starting address of the first data with a capacity of 4KB to be received for the third time is 0x5400.

As shown in Figure 4b, the starting addresses of the three read operations in the memory unit MEM1 are: 0x5600, 0x4A00, 0x4600, and the starting addresses of the three write operations are: 0x6400, 0x5800, 0x5400, that is, each read and write The start addresses of the operations are arranged in the direction of the first address. Moreover, in each read and write operation, the first data or the second data can be read and written in the direction of the second address according to the starting address. It should be understood that the processing unit can perform multiple read and write operations on the storage unit, and the present disclosure does not limit the data capacity of each read and write operation by the processing unit and the specific number of read and write operations.

In the storage unit, the data sent away can be reused at the next moment in the space area. For example, the second time that the storage unit MEM1 receives the first data with the capacity of 12KB, it needs to occupy the data space of the address 0x5800~0x6400, because the last time, that is, the first time, the storage unit MEM1 has been read by the processing unit to take away the second data , and release the data space occupied by addresses 0x5600 to 0x6200 to avoid the destruction and coverage of the overlapping space of addresses 0x5800 to 0x6200. Similarly, the storage unit MEM1 needs to occupy the data space of the address 0x5400~0x5800 to receive the first data with the capacity of 12KB for the third time, because the second data has been taken away from the storage unit MEM1 for the first time and the occupied address 0x5600~0x6200 has been released. The data space, and the data space occupied by the address 0x4A00~0x5600 released by the second data taken away for the second time, the data space of the address 0x4A00~0x6200 is released by the first and second storage unit MEM1 in total, so as to avoid causing damage to the first time. The data space of addresses 0x5400 to 0x5800 required for receiving the first data three times is destroyed and overwritten.

Therefore, in the data transmission process shown in FIG. 4b, in the case where the address of the data to be sent and the address of the data to be received overlap in the storage unit, there is no storage unit caused by multiple read and write operations performed by the processing unit at the same time. Data in the overlapping area is destroyed and covered, and there is no additional time caused by moving data to avoid data destruction, eliminating routing transmission delay, thereby improving the chip's space-time computing efficiency and improving chip performance.

In a possible implementation manner, in the weight data space storing the weight data of the same convolution layer and the processing data space storing the processing data of the same convolution layer, the weight data and the processing data respectively follow the second address The directions are arranged in sequence, with the first address direction being opposite to the second address direction.

Some examples of sorting the weight data and processing data are given below. For each convolutional layer, the sorted weight data and processing data of the layer can be sorted according to the order (such as serial number 0, 1, 2, ... order), in the weight data space of the layer, they are arranged in order according to the second address direction, and in the processing data space of the layer, they are arranged in order according to the second address direction.

FIG. 5 shows a flowchart according to an embodiment of the present disclosure. As shown in Figure 5, for the storage method of data in each layer of convolution operation process in the multi-layer convolution operation process, the following steps may be included:

Step S31, the processing component determines the storage order of the processing data and the weight data in each convolutional layer.

In a possible implementation manner, for the processing data in the convolution operation process of each layer in the multi-layer convolution operation process, the processing component determines that the storage order of the processing data in each convolution layer is the depth direction first , then landscape orientation, then portrait orientation.

FIG. 6 shows a schematic diagram of a processing data storage sequence according to an embodiment of the present disclosure. Assuming that the bit width of the storage unit of the computing core is 32B, the processing data in the layer may be inputted whole image data (512 pixels) divided into a series of images with a size of 4×4 pixels in 32 consecutive frames. As shown in FIG. 6 , the left cuboid in FIG. 6 can represent the processing data in the layer. There are 32 layers in total along the depth direction (z-axis direction), and each layer corresponds to a frame of 4×4 pixel image. .

The processing unit can determine the storage sequence of the processed data in each convolutional layer, that is, determine the sequence in which each small cube in the left cuboid in FIG. 6 is sent to the storage unit. The processing unit can label each small cube in the left cuboid of FIG. 6 according to the depth direction (z-axis direction), then the lateral direction (x-axis direction), and then the longitudinal direction (y-axis direction) of the cuboid on the left side of FIG. 6 , so The corresponding relationship between the label serial number and the coordinates (x, y, z) is:

Among them, M is the depth of the processed data, that is, the dimension in the z direction.

第2帧图像对应的序号为：

依次类推，第32帧图像对应的序号为：

Therefore, the sequence number corresponding to the first frame image is:

The serial number corresponding to the second frame image is:

By analogy, the serial number corresponding to the 32nd frame image is:

The serial number sequence of each small cube in the left cuboid of FIG. 6 represents the processing data storage sequence determined by the processing component.

In a possible implementation manner, each layer of convolution operation process uses multiple convolution kernel groups, each convolution kernel group includes multiple convolution kernels, and in the storage unit, each layer of convolution kernels The weight data of each convolution kernel group in the operation is stored in sequence, and the storage order of the weight data of each convolution kernel group is stored according to the number sequence of the convolution kernel, the depth direction of the convolution kernel, the horizontal direction, and the vertical direction.

For example, for the weight data in the convolution operation process of each layer in the multi-layer convolution operation process, the processing component may first number and group the convolution kernels, and then follow the numbering order of the convolution kernels in each group. , the depth direction of the convolution kernel, the horizontal direction of the convolution kernel, and the order of the longitudinal direction of the convolution kernel determine the storage order of groups.

Wherein, the weight data includes multiple groups of convolution kernels, and each group includes multiple convolution kernels. The processing component may group the convolution kernels in the weight data according to the depth of the processing data, and the number of convolution kernels in each group may be the same as the depth of the processing data.

FIG. 7 is a schematic diagram illustrating a storage sequence of weight data according to an embodiment of the present disclosure. As shown in Figure 7, each cuboid on the left side of the figure represents a convolution kernel, and the 64 convolution kernels in the figure can be numbered W ₀ , W ₁ , . . . , W ₆₃ first. Corresponding to the processing data depth (M=32) shown in Figure 6, the convolution kernels can be grouped by 32, and each 32 convolution kernels are grouped into 2 groups (N=2), W ₀ , W ₁ , ..., W ₃₁ is the first group, W ₃₂ , W ₃₃ , ..., W ₆₃ are the second group, and the number N of the divided groups may represent the depth of the weight data.

The processing unit may determine the storage order of the weight data in each convolutional layer, that is, determine the sequence in which each small cube in each rectangular parallelepiped on the left side of FIG. 7 is sent to the storage unit.

The processing component may divide the cuboid on the left side of FIG. 7 into N groups (N=2), and determine a storage order for storing the weight data group by group according to the grouping order.

For the storage order of each group of convolution kernels, you can first follow the convolution kernel numbering order, and then follow the depth direction of the convolution kernel (z-axis direction), the horizontal direction of the convolution kernel (x-axis direction), and the longitudinal direction of the convolution kernel. The direction (y-axis direction) is assigned to each small cube in each rectangular parallelepiped on the left side of FIG. 7 . Among them, the order direction of the convolution kernel number corresponds to the depth direction of the processed data.

The corresponding relationship between the marked serial number and the coordinates (x, y, z) is:

According to the corresponding relationship between the serial number and the coordinates (x, y, z), for the weight data of N=1 group, the serial number corresponding to the convolution kernel W ₀ is: [0 32 64 96 128 160 192 224 256 288 320 352 384 416 448 480], the serial number corresponding to the convolution kernel W ₁ is: [1 33 65 97 129 161 193 225 257 289 321 353 385 417 449481], and so on, the serial number of the convolution kernel W ₃₁ is: [31 63 95 127 159 191 223 255 287 319 351 383415 447 479 511].

Similarly, for N=2 sets of weight data, the serial number corresponding to the convolution kernel W ₃₂ is: [512 544 576 608 640672 704 736 768 800 832 864 896 928 960 992], and the serial number corresponding to the convolution kernel W ₃₃ is: [513 545577 609 641 673 705 737 769 801 833 865 897 929 961 993], and so on, the serial number corresponding to the convolution kernel W ₆₃ is: [543 575 607 639 671 1103 735 767 799 920 31 59 99.9.

The sequence of the serial numbers of the small cubes in the rectangular parallelepipeds on the left side of FIG. 7 may represent the storage sequence of the weight data determined by the processing component.

Step S32, the processing component sends the processing data and the weight data to a storage unit according to the storage order of the processing data and the weight data.

In a possible implementation manner, the processing unit sends the processing data into the processing data space of the storage unit in the storage unit according to the storage sequence of the processing data in the second address direction.

For example, as shown in FIG. 6 , the serial numbers marked on the cubes in the figure may correspond to the storage addresses of the storage units, and the processing unit may send the pixel values corresponding to the serial numbers marked on the cubes by accessing the addresses corresponding to the storage units. storage unit. The processing component can send the pixel value corresponding to the serial number 0 cube into the address 0x0000 space in the storage unit by accessing the address 0x0000 in the storage unit corresponding to the serial number 0 cube; the processing component can access the storage unit corresponding to the serial number 1 cube by accessing the storage unit. Address 0x0001, send the pixel value corresponding to the cube with the serial number 1 into the address 0x0001 space in the storage unit; and so on, the processing unit can access the address 0x01FF in the storage unit corresponding to the cube with the serial number 511, and send the pixel value corresponding to the cube with the serial number 511. into the address 0x01FF space in the storage unit.

As shown in FIG. 6 , the processing unit sends the processed data into the storage unit in the depth direction, then the horizontal direction, and then the vertical direction according to the sequence of the marked serial numbers.

In a possible implementation manner, the processing component sends the weight data into the weight data space of the storage unit in the storage component according to the storage order of the weight data in the second address direction.

For example, as shown in FIG. 7 , the serial numbers marked on the cubes in the figure may correspond to the storage addresses of the storage units, and the processing unit may send the weight data corresponding to the serial numbers marked on the cubes by accessing the addresses corresponding to the storage units. into the storage unit. The processing component can send the weight corresponding to the serial number 0 cube into the address 0x0000 space in the storage unit by accessing the address 0x0000 in the storage unit corresponding to the serial number 0 cube; the processing component can access the storage unit corresponding to the serial number 1 cube by accessing the address 0x0000. Address 0x0001, send the weight corresponding to the cube of serial number 1 into the address 0x0001 space in the storage unit; and so on, the processing unit can access the address 0x03FF in the storage unit corresponding to the cube of serial number 1023, and send the weight corresponding to the cube of serial number 1023 to the space of address 0x0001. into the address 0x03FF space in the storage unit.

As shown in FIG. 7 , according to the sequence of the numbered convolution kernels, the processing unit firstly divides the convolution kernel numbering sequence, then the convolution kernel depth direction, the convolution kernel horizontal direction, and the convolution kernel longitudinal direction, grouping the weight data into one group. The groups are sequentially fed into the storage unit.

Step S33, the storage unit receives and stores the processing data and the weight data.

The weight data may be stored first, and then the processing data. The weight data may be stored in the weight data space of one storage unit, and the processing data may be stored in the processing data space of another storage unit.

In a possible implementation manner, in the storage unit, the storage order of the processing data and weight data for each convolutional layer conforms to the convolution operation process of depth direction first, then horizontal direction, and then vertical direction.

FIG. 8 is a schematic diagram showing the principle of storage order of a convolution operation process according to an embodiment of the present disclosure. As shown in Figure 8, assuming that the processing data is image data, it can be represented by a three-dimensional tensor X[i,j,m], as follows:

X[i,j,m], i=1,2,...,I, j=1,2,...,J, m=1,2,...,M

I indicates that the image data X[i,j,m] has I pixels in the vertical dimension, J indicates that the image data X[i,j,m] has J pixels in the horizontal dimension, and M indicates that the image data X[i, j,m] has M pixels in the depth dimension, and the size of the processed data is I×J×M.

Among them, the image data of M depth can be M frames of continuous sequence images converted from video, can be split from a whole image into M sub-images of equal size, or can be image data with a channel depth of M, This disclosure does not limit this.

For example, to perform N groups of 3×3 fixed window size sliding window convolution operations on M pieces of processing data, if N groups of 3×3 fixed window size sliding window convolution operations are performed on the pictures one by one, each To process a piece of image data, it is necessary to access the storage unit once to read the convolution kernel, and the storage unit needs to be read M times repeatedly, resulting in frequent access to the storage unit. Therefore, the three-dimensional sliding window convolution operation can be performed on the processing data according to the depth direction, and the convolution kernel (ie the weight data) read once for the storage unit can perform the sliding window convolution operation on the M input images at the same time to realize the input Parallel operations on images.

As shown in Figure 8, assuming that there are M pictures in the depth direction, C[k _x k _y ,m] represents the image data obtained by the sliding window of the sliding convolution. Sliding in the data, this application does not limit the sliding mode of the sliding window.

The weight data corresponding to the image data C[k _x k _y ,m] obtained by the sliding window is K[k _x k _y ,m,n]. In FIG. 8 , the weight data K[k _x k _y , m,n] has N groups, each with M convolution kernels, corresponding to the processed data of depth M. The image data C[k _x k _y ,m] obtained by the sliding window can be the same as each group of convolution kernels K[k _x k _y ,m,n](n=1,2 ,…,N) to perform multiplication and addition operations respectively.

Since the convolution operation is performed on the image data X[i,j,m], that is, the multiplication and addition operation is performed on the image data X[i,j,m]. According to the multiplication commutative law and the addition commutative law, the order of the convolution operation process is adjusted. , the result of the convolution operation remains unchanged. Therefore, in order to reduce the number of accesses to the storage unit, the order of the convolution operation process can be adjusted, first along the depth M direction, then along the horizontal direction J, and the vertical direction I to perform operations.

The corresponding formula of the operation process is as follows:

Among them, C[k _x k _y ,m] represents the image data obtained by the sliding window, that is, the data of the input image corresponding to the size of the convolution kernel, K[k _x k _y ,m,n] represents the convolution weight, kx *ky represents the size of a convolution kernel. The convolution weights are divided into N groups according to the depth direction M, and each group has M convolution kernels. This convolution process is to first multiply and add the convolution kernel along the depth direction M. According to The size of the convolution kernel is kx*ky, and the sliding window convolution operation of the remaining data is completed along the horizontal J and vertical I respectively.

According to the convolution operation process of the processing unit in the depth first, in the horizontal direction, and then in the vertical direction, it is beneficial to realize the parallel processing of data and improve the computing efficiency of the chip. For the processed data and weight data in the convolution operation process, the processing component can store the processed data in the depth direction, then the horizontal direction, and then the vertical direction, and the weight data in the order of convolution kernel numbering first, then the volume The depth direction of the accumulation kernel, the horizontal direction of the convolution kernel, and the vertical direction of the convolution kernel are stored in a group of storage sequences, so that the processed data and weight data stored first can be read and participated in the operation first, and the height matching first depth, then horizontal, The vertical convolution operation process improves the fit between the stored process and the convolution operation process, and improves the calculation efficiency.

The present disclosure also provides a computing core. Figure 1 shows an example of a computing core that includes processing components and storage components.

In a possible implementation manner, the processing unit sequentially writes the weight data and processing data of each convolution layer into each storage unit for storage according to the processing order of the convolution layers in the multi-layer convolution operation process .

The storage unit includes two or more storage units, and each storage unit receives and stores the weight data and the processing data.

Wherein, in the storage unit, the processing data and weight data of the same convolution layer are stored in different storage units; in the same storage unit, the weight data space for storing the weight data and the processing data for storing the processing data are stored in the same storage unit. The data spaces are arranged in sequence according to the first address direction.

Among them, the weight data space for storing the weight data of each convolution layer is arranged in the first address direction according to the processing order of the convolution layer; the processing data space for storing the processing data of each convolution layer is according to the processing order of the convolution layer, Arranged sequentially in the direction of the first address.

Among them, in the weight data space storing the weight data of the same convolution layer and the processing data space storing the processing data of the same convolution layer, the weight data and the processing data are arranged in sequence according to the second address direction, and the first address The direction is opposite to the direction of the second address.

In a possible implementation manner, the first address direction is a high address to low address direction, and the second address direction is a low address to high address direction.

In a possible implementation manner, the processing component is further configured to send the operation result data of each convolution layer in the multi-layer convolution operation process into each storage unit for storage;

Each storage unit receives and stores the operation result data, wherein the operation result data of any convolution layer and the processing data of the convolution layer are stored in the same storage unit, and are shared with the processing data of the next convolution layer. space.

In a possible implementation manner, the processing component is further configured to write the first data received from outside the computing core into a storage unit, and read the second data from the storage unit to send the data outside the computing core ;

Wherein, in multiple write operations, the start addresses of each write operation are arranged in the direction of the first address, and the first data is written in the direction of the second address in each write operation;

In multiple read operations, the start addresses of each read operation are arranged in the direction of the first address, and the second data is read in the direction of the second address in each read operation.

In a possible implementation manner, in the storage unit, the storage order of the processing data and weight data for each convolutional layer conforms to the convolution operation process of depth direction first, then horizontal direction, and then vertical direction.

In a possible implementation manner, each layer of convolution operation process uses multiple convolution kernel groups, and each convolution kernel group includes multiple convolution kernels;

In the storage unit, the weight data of each convolution kernel group in the convolution operation of each layer is stored in sequence, and the storage order of the weight data of each convolution kernel group is according to the numbering order of the convolution kernel, the convolution kernel The kernel depth direction, horizontal direction, and vertical direction are stored.

For the above-mentioned implementation of the computing core, reference may be made to the description of the part about the data storage method above, and details are not repeated here.

In a possible implementation manner, an embodiment of the present disclosure further provides an artificial intelligence chip, where the chip includes at least one computing core as described above. The chip may include multiple processors, and the processors may include multiple computing cores, and the present disclosure does not limit the number of computing cores in the chip.

In a possible implementation manner, an embodiment of the present disclosure provides an electronic device, including one or more of the above-mentioned artificial intelligence chips.

FIG. 9 is a structural diagram illustrating a combined processing apparatus 1200 according to an embodiment of the present disclosure. As shown in FIG. 9 , the combined processing device 1200 includes a computing processing device 1202 (eg, the above-mentioned artificial intelligence processor including multiple computing cores), an interface device 1204 , other processing devices 1206 and a storage device 1208 . According to different application scenarios, the computing processing device may include one or more computing devices 1210 (eg, computing cores).

In one possible implementation, the computing processing apparatus of the present disclosure may be configured to perform user-specified operations. In an exemplary application, the computing processing device may be implemented as a single-core artificial intelligence processor or a multi-core artificial intelligence processor. Similarly, one or more computing devices included within a computing processing device may be implemented as an artificial intelligence processor core or as part of a hardware structure of an artificial intelligence processor core. When multiple computing devices are implemented as an artificial intelligence processor core or a part of the hardware structure of an artificial intelligence processor core, for the computing processing device of the present disclosure, they can be regarded as having a single-core structure or a homogeneous multi-core structure.

In an exemplary operation, the computing processing apparatus of the present disclosure may interact with other processing apparatuses through an interface apparatus to jointly complete an operation specified by a user. According to different implementations, other processing devices of the present disclosure may include one of general-purpose and/or special-purpose processors such as a central processing unit (Central Processing Unit, CPU), a graphics processing unit (Graphics Processing Unit, GPU), and an artificial intelligence processor. one or more types of processors. These processors may include, but are not limited to, Digital Signal Processors (DSPs), Application Specific Integrated Circuits (ASICs), Field-Programmable Gate Arrays (FPGAs) or other programmable Logic devices, discrete gate or transistor logic devices, discrete hardware components, etc., and the number thereof can be determined according to actual needs. As mentioned above, only for the computing processing device of the present disclosure, it can be regarded as having a single-core structure or a homogeneous multi-core structure. However, when computing processing devices and other processing devices are considered together, the two can be viewed as forming a heterogeneous multi-core structure.

In one or more embodiments, the other processing device may serve as an interface between the computing processing device of the present disclosure (which may be embodied as a related computing device for artificial intelligence such as neural network operations) and external data and control, performing operations including but not limited to Limited to basic controls such as data movement, starting and/or stopping computing devices. In other embodiments, other processing apparatuses may also cooperate with the computing processing apparatus to jointly complete computing tasks.

In one or more embodiments, the interface device may be used to transfer data and control instructions between the computing processing device and other processing devices. For example, the computing and processing device may obtain input data from other processing devices via the interface device, and write the input data into the on-chip storage device (or memory) of the computing and processing device. Further, the computing and processing device may obtain control instructions from other processing devices via the interface device, and write them into a control cache on the computing and processing device chip. Alternatively or alternatively, the interface device can also read the data in the storage device of the computing processing device and transmit it to other processing devices.

Additionally or alternatively, the combined processing device of the present disclosure may also include a storage device. As shown in the figure, the storage device is connected to the computing processing device and the other processing device, respectively. In one or more embodiments, a storage device may be used to store data of the computing processing device and/or the other processing device. For example, the data may be data that cannot be fully stored in an internal or on-chip storage device of a computing processing device or other processing device.

According to different application scenarios, the artificial intelligence chip of the present disclosure can be used in servers, cloud servers, server clusters, data processing devices, robots, computers, printers, scanners, tablet computers, smart terminals, PC equipment, IoT terminals, and mobile terminals. , mobile phones, driving recorders, navigators, sensors, cameras, cameras, video cameras, projectors, watches, headphones, mobile storage, wearable devices, visual terminals, autonomous driving terminals, vehicles, household appliances, and/or medical equipment . The vehicles include airplanes, ships and/or vehicles; the household appliances include televisions, air conditioners, microwave ovens, refrigerators, rice cookers, humidifiers, washing machines, electric lamps, gas stoves, and range hoods; the medical equipment includes nuclear magnetic resonance instruments, B-ultrasound and/or electrocardiograph.

FIG. 10 shows a block diagram of an electronic device 1900 according to an embodiment of the present disclosure. For example, the electronic device 1900 may be provided as a server. 10, an electronic device 1900 includes a processing component 1922 (eg, an artificial intelligence processor including a plurality of computing cores), which further includes one or more computing cores, and a memory resource, represented by memory 1932, for storing Instructions for execution of processing components 1922, such as applications. An application program stored in memory 1932 may include one or more modules, each corresponding to a set of instructions. Additionally, the processing component 1922 is configured to execute instructions to perform the above-described methods.

The electronic device 1900 may also include a power supply assembly 1926 configured to perform power management of the electronic device 1900, a wired or wireless network interface 1950 configured to connect the electronic device 1900 to a network, and an input output (I/O) interface 1958 . Electronic device 1900 may operate based on an operating system stored in memory 1932, such as Windows Server™, Mac OS X™, Unix™, Linux™, FreeBSD™ or the like.

In the present disclosure, units illustrated as separate components may or may not be physically separate, and components shown as units may or may not be physical units. The aforementioned components or elements may be co-located or distributed over multiple network elements. In addition, according to actual needs, some or all of the units may be selected to achieve the purpose of the solutions described in the embodiments of the present disclosure. In addition, in some scenarios, multiple units in the embodiments of the present disclosure may be integrated into one unit or each unit physically exists independently.

In the above-mentioned embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference may be made to the relevant descriptions of other embodiments. The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity, all possible combinations of the technical features in the above embodiments are not described. However, as long as there is no contradiction in the combination of these technical features, it should be It is considered to be the range described in this specification.

The electronic device or processor of the present disclosure can also be applied to the Internet, Internet of Things, data center, energy, transportation, public administration, manufacturing, education, power grid, telecommunications, finance, retail, construction site, medical and other fields. Further, the electronic device or processor of the present disclosure can also be used in application scenarios related to artificial intelligence, big data and/or cloud computing, such as the cloud, edge terminal, and terminal. In one or more embodiments, electronic devices or processors with high computing power according to the present disclosure can be applied to cloud devices (eg, cloud servers), while electronic devices or processors with low power consumption can be applied to terminal devices and / or edge devices (such as smartphones or cameras). In one or more embodiments, the hardware information of the cloud device and the hardware information of the terminal device and/or the edge device are compatible with each other, so that the hardware resources of the cloud device can be retrieved from the hardware information of the terminal device and/or the edge device according to the hardware information of the terminal device and/or the edge device. Match the appropriate hardware resources to simulate the hardware resources of terminal devices and/or edge devices, so as to complete the unified management, scheduling and collaborative work of device-cloud integration or cloud-edge-device integration.

Various embodiments of the present disclosure have been described above, and the foregoing descriptions are exemplary, not exhaustive, and not limiting of the disclosed embodiments. Numerous modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the various embodiments, the practical application or improvement over the technology in the marketplace, or to enable others of ordinary skill in the art to understand the various embodiments disclosed herein.

Claims (12)

1. A data storage method, characterized in that, applied to a computing core of a processor, the processor includes a plurality of computing cores, and each computing core includes a processing component and a storage component, wherein the storage component includes two the above storage unit; The method includes: The processing component sequentially writes the weight data and processing data of each convolution layer into each storage unit for storage according to the processing order of the convolution layers in the multi-layer convolution operation process; Each storage unit receives and stores the weight data and the processing data; Wherein, in the storage unit, the processing data and weight data of the same convolution layer are stored in different storage units; in the same storage unit, the weight data space for storing the weight data and the processing data for storing the processing data are stored in the same storage unit. The data space is arranged in sequence according to the first address direction; Among them, the weight data space for storing the weight data of each convolution layer is arranged in the first address direction according to the processing order of the convolution layer; the processing data space for storing the processing data of each convolution layer is according to the processing order of the convolution layer, Discharge in sequence along the first address direction; Among them, in the weight data space storing the weight data of the same convolution layer and the processing data space storing the processing data of the same convolution layer, the weight data and the processing data are arranged in sequence according to the second address direction, and the first address The direction is opposite to the direction of the second address; The first address direction is a high address to a low address direction, and the second address direction is a low address to a high address direction. 2. The method according to claim 1, wherein the method further comprises: The processing component sends the operation result data of each convolution layer in the multi-layer convolution operation process into each storage unit for storage; Each storage unit receives and stores the operation result data, wherein the operation result data of any convolution layer and the processing data of the convolution layer are stored in the same storage unit, and are shared with the processing data of the next convolution layer. space. 3. The method according to claim 1, wherein the method further comprises: The processing component writes first data received from outside the computing core to a storage unit, and reads second data from the storage unit to send to the outside of the computing core; Wherein, in multiple write operations, the start addresses of each write operation are arranged in the direction of the first address, and the first data is written in the direction of the second address in each write operation; In multiple read operations, the start addresses of each read operation are arranged in the direction of the first address, and the second data is read in the direction of the second address in each read operation. 4. The method according to claim 1, wherein, in the storage unit, the storage order of the processing data and the weight data for each convolutional layer conforms to the depth direction first, then the horizontal direction, and then the vertical volume. Product operation process. 5. The method according to claim 1 or 4, wherein each layer of convolution operation process uses a plurality of convolution kernel groups, and each convolution kernel group includes a plurality of convolution kernels; In the storage unit, the weight data of each convolution kernel group in the convolution operation of each layer is stored in sequence, and the storage order of the weight data of each convolution kernel group is according to the numbering order of the convolution kernel, the convolution kernel The kernel depth direction, horizontal direction, and vertical direction are stored. 6. A computing core, characterized in that the computing core comprises a processing component and a storage component; The processing component sequentially writes the weight data and processing data of each convolution layer into each storage unit for storage according to the processing order of the convolution layers in the multi-layer convolution operation process; The storage unit includes two or more storage units, and each storage unit receives and stores the weight data and the processing data; Wherein, in the storage unit, the processing data and weight data of the same convolution layer are stored in different storage units; in the same storage unit, the weight data space for storing the weight data and the processing data for storing the processing data are stored in the same storage unit. The data space is arranged in sequence according to the first address direction; Among them, the weight data space for storing the weight data of each convolution layer is arranged in the first address direction according to the processing order of the convolution layer; the processing data space for storing the processing data of each convolution layer is according to the processing order of the convolution layer, Discharge in sequence along the first address direction; Among them, in the weight data space storing the weight data of the same convolution layer and the processing data space storing the processing data of the same convolution layer, the weight data and the processing data are arranged in sequence according to the second address direction, and the first address The direction is opposite to the direction of the second address; The first address direction is a high address to a low address direction, and the second address direction is a low address to a high address direction. 7. computing kernel according to claim 6, is characterized in that, described processing unit is also used for the operation result data of each convolution layer in described multi-layer convolution operation process is sent into each storage unit for storage; Each storage unit receives and stores the operation result data, wherein the operation result data of any convolution layer and the processing data of the convolution layer are stored in the same storage unit, and are shared with the processing data of the next convolution layer. space. 8. The computing core according to claim 6, wherein the processing component is further configured to write the first data received from outside the computing core into a storage unit, and read the second data from the storage unit to send to the outside of the computing core; Wherein, in multiple write operations, the start addresses of each write operation are arranged in the direction of the first address, and the first data is written in the direction of the second address in each write operation; In multiple read operations, the start addresses of each read operation are arranged in the direction of the first address, and the second data is read in the direction of the second address in each read operation. 9. The computing kernel according to claim 6, wherein, in the storage unit, the storage order of the processing data and the weight data for each convolutional layer conforms to the depth direction first, then the horizontal direction, and then the vertical direction. Convolution operation process. 10. The computing kernel according to claim 6 or 9, wherein each layer of convolution operation process uses a plurality of convolution kernel groups, and each convolution kernel group includes a plurality of convolution kernels; In the storage unit, the weight data of each convolution kernel group in the convolution operation of each layer is stored in sequence, and the storage order of the weight data of each convolution kernel group is according to the numbering order of the convolution kernel, the convolution kernel The kernel depth direction, horizontal direction, and vertical direction are stored. 11. An artificial intelligence chip, wherein the chip comprises a plurality of computing cores according to any one of claims 6-10. 12. An electronic device, comprising one or more artificial intelligence chips according to claim 11.

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