CN112670339A - Gallium nitride power device and manufacturing method thereof - Google Patents
Gallium nitride power device and manufacturing method thereof Download PDFInfo
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Abstract
The invention discloses a gallium nitride power device and a manufacturing method thereof; the gallium nitride power device comprises a substrate layer, a buffer layer, a channel layer, a barrier layer, a p-type gallium nitride block layer and a gate metal block layer which are sequentially connected from bottom to top; the gate metal block layer comprises a first gate metal layer and a second gate metal layer which are connected; the first gate metal layer is in ohmic contact with the p-type gallium nitride block layer, and the second gate metal layer is in schottky contact with the p-type gallium nitride block layer. According to the gallium nitride power device and the manufacturing method thereof, the ohmic gate and the Schottky gate are mixed with the metal gate structure, the respective advantages of the ohmic gate and the Schottky gate are combined, the threshold voltage of the device is improved, the electric leakage of the gate is reduced, the output current capability of the device is enhanced, the problem of mistaken turn-on of an HEMT device is avoided, and the reliability of the device is improved.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a gallium nitride power device and a manufacturing method thereof.
Background
Gallium nitride (hereinafter, referred to as GaN) is one of the third generation wide bandgap semiconductors, and has excellent physical properties such as a wide bandgap and a high breakdown field. Due to the spontaneous polarization and piezoelectric polarization characteristics of the GaN-based semiconductor, the AlGaN/GaN heterojunction interface can generate high-confinement property and high-concentration two-dimensional electron gas (2DEG) under the condition of unintentional doping, and has high electron mobility and high saturated electron drift velocity. Therefore, the AlGaN/GaN heterojunction can be used for constructing a High Electron Mobility Transistor (HEMT), and the GaN HEMT can be suitable for high-temperature, high-voltage, high-frequency and high-power density applications and has good application prospects in the fields of microwave radio frequency, power electronics and the like.
The AlGaN/GaN heterojunction has 2DEG after being formed, so the HEMT is a normally open depletion mode device, unsafe problems such as mistaken opening and the like easily exist in power electronic application, and the reliability of the HEMT device is influenced.
Disclosure of Invention
The first objective of the present invention is to provide a gallium nitride power device to solve the problems of low threshold voltage and false turn-on of the conventional HEMT device.
In order to achieve the purpose, the technical scheme provided by the invention is as follows:
a gallium nitride power device comprises a substrate layer, a buffer layer, a channel layer, a barrier layer, a p-type gallium nitride block layer and a gate metal block layer which are sequentially connected from bottom to top; the gate metal block layer comprises a first gate metal layer and a second gate metal layer which are connected; the first gate metal layer is in ohmic contact with the p-type gallium nitride block layer, and the second gate metal layer is in schottky contact with the p-type gallium nitride block layer.
Further, the second gate metal layer wraps the first gate metal layer.
Further, the top surface of the barrier layer is connected with a source electrode and a drain electrode; the source electrode and the drain electrode are respectively positioned on two sides of the p-type gallium nitride block layer and are in ohmic contact with the barrier layer.
Further, the device comprises a dielectric layer connected with the barrier layer; the dielectric layer coats the p-type gallium nitride block layer, the second gate metal layer, the source electrode and the drain electrode; the dielectric layer is provided with a first opening connected with the source electrode, a second opening connected with the drain electrode and a third opening connected with the second gate metal layer; the first interconnected metal layer connected with the source electrode is installed in the first opening, the second interconnected metal layer connected with the drain electrode is installed in the second opening, and the third interconnected metal layer connected with the second grid metal layer is installed in the third opening.
A second object of the present invention is to provide a method for manufacturing a gallium nitride power device, including:
depositing a buffer layer, a channel layer, a barrier layer, and a p-type gallium nitride bulk layer on a substrate;
preparing a first gate metal layer on the p-type gallium nitride block layer, wherein the first gate metal layer is in ohmic contact with the p-type gallium nitride block layer, and the area size of the first gate metal layer is smaller than that of the p-type gallium nitride block layer;
and preparing a second gate metal layer on the first gate metal layer and the p-type gallium nitride block layer, wherein the second gate metal layer is in Schottky contact with the p-type gallium nitride block layer.
Further, the manufacturing method includes:
preparing a source electrode and a drain electrode on the barrier layer; the source electrode and the drain electrode are respectively positioned on two sides of the p-type gallium nitride block layer and are in ohmic contact with the barrier layer.
Further, the manufacturing method includes:
depositing a dielectric layer on the barrier layer, wherein the dielectric layer coats the p-type gallium nitride block layer, the second gate metal layer, the source electrode and the drain electrode.
Further, the manufacturing method includes:
forming a first opening connected with the source electrode, a second opening connected with the drain electrode and a third opening connected with the second gate metal layer on the dielectric layer;
and preparing a first interconnection metal layer connected with the source electrode on the first opening, preparing a second interconnection metal layer connected with the drain electrode on the second opening, and preparing a third interconnection metal layer connected with the second gate metal layer on the third opening.
Further, the manufacturing method includes:
depositing a passivation layer on the surface of the dielectric layer;
and a fourth opening connected with the first interconnection metal layer, a fifth opening connected with the second interconnection metal layer and a sixth opening connected with the third interconnection metal layer are formed in the passivation layer.
Further, the manufacturing method includes:
and forming an isolation region on two sides of the barrier layer and the channel layer by mesa etching or ion implantation.
In summary, the gallium nitride power device and the manufacturing method thereof adopt the metal gate structure of the ohmic gate and the schottky gate, and combine the advantages of the ohmic gate and the schottky gate, thereby improving the threshold voltage of the device, reducing the leakage of the gate, enhancing the output current capability of the device, avoiding the problem of mistaken turn-on of the HEMT device, and improving the reliability of the device.
Advantages of the above additional aspects will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention.
Drawings
Fig. 1 is a schematic structural diagram of a gallium nitride power device according to an embodiment of the invention;
fig. 2 is a schematic structural diagram of a gallium nitride power device according to an embodiment of the present invention after a buffer layer, a channel layer, a barrier layer, and a p-type gallium nitride layer are deposited on a substrate;
fig. 3 is a schematic structural diagram of a gallium nitride power device manufactured by the method according to the embodiment of the invention after etching p-type gallium nitride in a non-gate region;
fig. 4 is a schematic structural diagram of a gallium nitride power device according to an embodiment of the present invention after source and drain electrodes are fabricated;
fig. 5 is a schematic structural diagram of a gallium nitride power device according to an embodiment of the present invention after a first gate metal layer is prepared;
fig. 6 is a schematic structural diagram of a gallium nitride power device according to an embodiment of the present invention after a second gate metal layer is prepared;
fig. 7 is a schematic structural diagram after an isolation region is prepared in the method for manufacturing a gallium nitride power device according to the embodiment of the invention;
FIG. 8 is a schematic structural diagram of a gallium nitride power device according to an embodiment of the present invention after a dielectric layer is deposited on a barrier layer;
fig. 9 is a schematic structural diagram of a gallium nitride power device according to an embodiment of the present invention after a dielectric layer is opened and an interconnection metal layer is prepared.
In the drawings, the components represented by the respective reference numerals are listed below:
1. a substrate layer; 2. a buffer layer; 3. a channel layer; 4. a barrier layer; 5. a p-type gallium nitride layer; 6. a p-type gallium nitride bulk layer; 7. a first gate metal layer; 8. a second gate metal layer; 9. a source electrode; 10. a drain electrode; 11. a dielectric layer; 12. a passivation layer; 13. a first interconnect metal layer; 14. a second interconnect metal layer; 15. a third interconnect metal layer; 16. a fourth opening; 17. fifth opening; 18. a sixth opening; 19. and (4) an isolation region.
Detailed Description
The principles and features of this invention are described below in conjunction with the following drawings, which are set forth by way of illustration only and are not intended to limit the scope of the invention.
Referring to fig. 1, the present embodiment provides a gallium nitride power device, which includes a substrate layer 1, a buffer layer 2, a channel layer 3, a barrier layer 4, a p-type gallium nitride block layer 6, a gate metal block layer, and other specific hierarchical structures that are sequentially connected from bottom to top.
The substrate layer 1 of this embodiment may be made of SiC, Si, sapphire, or GaN. The GaN channel layer 3 has a thickness of 50 to 500 nm. The buffer layer 2 is made of various combinations of AlGaN, AlN, and GaN, and has a total thickness of 1-7 μm. The barrier layer 4 is made of AlGaN, the thickness of the AlGaN is 10-30nm, and the Al component is 5% -30%. A1-5 nm AlN layer may be interposed between the AlGaN barrier layer 4 and the GaN channel layer 3. The p-type gallium nitride bulk layer 6 has excellent thicknessIs selected from 50-200nm, and p-type doping concentration is 1e16-1e20cm3。
Based on the problems in the background art, the inventor finds that the main reason that the conventional HEMT device has the problem of false turn-on is an ohmic gate structure, the ohmic gate structure is that gate metal and p-type gallium nitride form ohmic contact, and due to a hole injection effect, the output current of the device can be improved by adopting the type of gate metal, but the threshold voltage is low and is only a few tenths of volts, and the gate leakage is large; the low threshold voltage is the main reason for the problem of false turn-on.
However, if the schottky gate is used instead of the ohmic gate, the problem of relatively low output current occurs, so that the inventor makes innovative assumptions and a large number of experiments to provide a p-type gallium nitride enhancement type HEMT device with mixed metal of the ohmic gate and the schottky gate.
Based on this, the gate metal block layer of the present embodiment is distinguished from the single connection mode of the prior art, which includes the first gate metal layer 7 and the second gate metal layer 8 connected; the first gate metal layer 7 of this embodiment is in ohmic contact with the p-type gan bulk layer 6, and the second gate metal layer 8 of this embodiment is in schottky contact with the p-type gan bulk layer 6. The first gate metal layer 7 of this embodiment may be a Ni/Au metal stack, and the total thickness is preferably 50-500nm, and the second gate metal layer 8 may be a Ni/Au, W/Ti, or other metal stack.
By adopting the structure, the problems of large grid leakage and low threshold voltage of the ohmic grid p-type gallium nitride HEMT and low output current of the Schottky grid p-type gallium nitride HEMT are solved, the respective advantages of the ohmic grid p-type gallium nitride HEMT and the Schottky grid p-type gallium nitride HEMT are combined, the threshold voltage of the device is improved, the grid leakage is reduced, the output current capability of the device is enhanced, the problem of mistaken switching-on of the HEMT device is avoided, and the reliability of the device is improved.
Specifically, the second gate metal layer 8 of this embodiment wraps the first gate metal layer 7, and the bottom surfaces of the first gate metal layer 7 and the second gate metal layer 8 are both connected to the p-type GaN bulk layer 6, so as to implement the ohmic contact and the schottky contact.
Further, the barrier layer 4 of the present embodiment has a source electrode 9 and a drain electrode 10 connected to the top surface thereof; the source electrode 9 and the drain electrode 10 are respectively located on both sides of the p-type gallium nitride bulk layer 6, and are in ohmic contact with the barrier layer 4. The source electrode 9 and the drain electrode 10 may be a Ti/Al metal laminate, and the total thickness is preferably 50-500 nm.
Based on the above structure, the present embodiment further includes a dielectric layer 11 and a passivation layer 12; wherein the dielectric layer 11 is deposited directly on the barrier layer 4; the material of the dielectric layer 11 may be SiO, SiO2、SiN、SiON、ZrO2、HfO2、Al2O3One or more of them.
The dielectric layer 11 of this embodiment wraps the p-type gallium nitride block layer 6, the second gate metal layer 8, the source 9 and the drain 10; a first opening connected with the source electrode 9, a second opening connected with the drain electrode 10, and a third opening connected with the second gate metal layer 8 are formed in the dielectric layer 11, and it should be noted that the connection of the openings with the source electrode 9, the drain electrode 10, or the second gate metal layer 8 means that one end of the openings is connected to the source electrode 9, the drain electrode 10, or the second gate metal layer 8, so that a first interconnection metal layer 13 connected with the source electrode 9 can be installed in the first opening, a second interconnection metal layer 14 connected with the drain electrode 10 can be installed in the second opening, and a third interconnection metal layer 15 connected with the second gate metal layer 8 can be installed in the third opening. It should be noted that, since the interconnection metal layer fills the three openings, the openings are not labeled.
The passivation layer 12 of this embodiment is directly deposited on the dielectric layer 11, and covers the upper portion of the first interconnection metal layer 13, the upper portion of the second interconnection metal layer 14, and the upper portion of the third interconnection metal layer 15, and a fourth opening 16 connected to the first interconnection metal layer 13, a fifth opening 17 connected to the second interconnection metal layer 14, and a sixth opening 18 connected to the third interconnection metal layer 15 are formed on the deposited passivation layer 12, where the purpose of the fourth opening 16, the fifth opening 17, and the sixth opening 18 designed in this embodiment is to implement connection between the first interconnection metal layer 13, the second interconnection metal layer 14, and the third metal layer and other components. The passivation layer 12 of this embodiment may be made of one or more of SiN, SiO2, or polyimide.
In addition, in the embodiment, the isolation region 19 is formed on both sides of the barrier layer 4 and the channel layer 3 by mesa etching or ion implantation, the depth of the isolation region 19 is 100 nm and 500nm, and the depth of the isolation region 19 extends from the top surface of the barrier layer 4 into the channel layer 3.
Based on the specific structure of the gallium nitride power device, the embodiment further provides a method for manufacturing the gallium nitride power device, which includes the following steps:
a. a buffer layer 2, a channel layer 3, a barrier layer 4, and a p-type gallium nitride layer 5 are deposited on the substrate to form the structure in fig. 2.
b. And etching the p-type gallium nitride layer 5 in the non-gate region to form the p-type gallium nitride layer 5 into a p-type gallium nitride block layer 6 with the area far smaller than that of the barrier layer 4. The etching method can be RIE and ICP, and the thickness of the p-type gallium nitride layer of the etched non-gate area is less than 5nm to form the structure in the figure 3.
c. Source 9 and drain 10 metals are prepared and rapidly thermally annealed to form ohmic contacts. The rapid thermal annealing temperature is 400-900 ℃ for 10-200 s to form the structure shown in fig. 4.
d. Preparing a first gate metal layer 7 on the p-type gallium nitride block layer 6, and performing rapid thermal annealing to form ohmic contact, wherein the area size of the first gate metal layer 7 is smaller than that of the p-type gallium nitride block layer 6; the rapid thermal annealing temperature is 400-900 ℃ for 10-200 s to form the structure shown in FIG. 5.
e. A second gate metal layer 8 is fabricated on the first gate metal layer 7 and the p-type gallium nitride bulk layer 6, the second gate metal layer 8 schottky contacting the p-type gallium nitride bulk layer 6 to form the structure of fig. 6.
f. Mesa etching or ion implantation to form the isolation region 19, wherein the etching depth or ion implantation depth exceeds the depth of the channel layer 3, typically 100 nm and 500nm, to form the structure in fig. 7.
g. And depositing a dielectric layer 11 on the barrier layer 4, wherein the dielectric layer 11 covers the p-type gallium nitride block layer 6, the first gate metal layer 7, the second gate metal layer 8, the source electrode 9 and the drain electrode 10, and the deposition method can be a PECVD (plasma enhanced chemical vapor deposition), LPCVD (low pressure chemical vapor deposition) or ALD (atomic layer deposition) method with the thickness of 50-2000nm to form the structure in the graph 8.
h. A first opening connected with the source electrode 9, a second opening connected with the drain electrode 10 and a third opening connected with the second gate metal layer 8 are formed in the dielectric layer 11; preparing a first interconnection metal layer 13 connected with the source electrode 9 on the first opening, preparing a second interconnection metal layer 14 connected with the drain electrode 10 on the second opening, and preparing a third interconnection metal layer 15 connected with the second gate metal layer 8 on the third opening; to form the structure of fig. 9. The interconnection metal layer may be a Ti/Al metal stack.
i. Depositing a passivation layer 12 on the surface of the dielectric layer 11; and a fourth opening 16 connecting the first interconnect metal layer 13, a fifth opening 17 connecting the second interconnect metal layer 14 and a sixth opening 18 connecting the third interconnect metal layer 15 are opened in the deposited passivation layer 12 to form the finished structure of fig. 1.
In the description of the present invention, it is to be understood that the terms "inside", "outside", and the like, indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience in describing the present invention and simplifying the description, but do not indicate or imply that the device referred to must have a specific orientation, be constructed in a specific orientation, and be operated, and should not be construed as limiting the present invention.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise.
In the present invention, unless otherwise specifically stated or limited, the terms "mounted," "connected," and the like are to be construed broadly and may, for example, be fixedly connected, detachably connected, or integrally formed. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention, and that variations, modifications, substitutions and alterations can be made to the above embodiments by those of ordinary skill in the art within the scope of the present invention.
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