CN112447679A - Power semiconductor device and manufacturing method thereof - Google Patents
Power semiconductor device and manufacturing method thereof Download PDFInfo
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- CN112447679A CN112447679A CN201910818893.3A CN201910818893A CN112447679A CN 112447679 A CN112447679 A CN 112447679A CN 201910818893 A CN201910818893 A CN 201910818893A CN 112447679 A CN112447679 A CN 112447679A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 41
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 15
- 239000002184 metal Substances 0.000 claims abstract description 41
- 238000000034 method Methods 0.000 claims description 36
- 210000004027 cell Anatomy 0.000 claims description 11
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 11
- 229920005591 polysilicon Polymers 0.000 claims description 11
- 239000000758 substrate Substances 0.000 claims description 10
- 239000000463 material Substances 0.000 claims description 9
- 210000003850 cellular structure Anatomy 0.000 claims description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 4
- 229910052710 silicon Inorganic materials 0.000 claims description 4
- 239000010703 silicon Substances 0.000 claims description 4
- 230000008020 evaporation Effects 0.000 claims description 3
- 238000001704 evaporation Methods 0.000 claims description 3
- 238000004544 sputter deposition Methods 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 2
- 238000005516 engineering process Methods 0.000 abstract description 3
- 238000000059 patterning Methods 0.000 description 5
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 230000002093 peripheral effect Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000001413 cellular effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 230000003137 locomotive effect Effects 0.000 description 1
- 238000004857 zone melting Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/647—Resistive arrangements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions
- H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions
- H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
- H10D64/311—Gate electrodes for field-effect devices
- H10D64/411—Gate electrodes for field-effect devices for FETs
- H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
- H10D64/517—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers
- H10D64/518—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers characterised by their lengths or sectional shapes
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions
- H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
- H10D64/311—Gate electrodes for field-effect devices
- H10D64/411—Gate electrodes for field-effect devices for FETs
- H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
- H10D64/517—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers
- H10D64/519—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers characterised by their top-view geometrical layouts
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
- H10D12/411—Insulated-gate bipolar transistors [IGBT]
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Abstract
本申请涉及半导体技术领域，公开了一种功率半导体器件及其制作方法，功率半导体器件包括：栅极结构和多个元胞结构；栅极结构包括电阻区和接线区，接线区设有连接金属层，元胞结构的栅极与接线区的连接金属层电连接；电阻区包括电阻走线、和沿电阻走线的延伸方向分布的多个连接焊盘，每一个连接焊盘与电阻走线电连接，以将电阻走线分隔为相互串联的多段电阻。本申请公开的功率半导体器件，将外部电阻集成到栅极结构上，从而降低IGBT和MOSFET器件栅极的电压操控难度，提高精准性。
The application relates to the field of semiconductor technology, and discloses a power semiconductor device and a manufacturing method thereof. The power semiconductor device includes: a gate structure and a plurality of cell structures; the gate structure includes a resistance region and a wiring region, and the wiring region is provided with a connecting metal layer, the gate of the cell structure is electrically connected to the connection metal layer of the wiring area; the resistance area includes a resistance trace and a plurality of connection pads distributed along the extension direction of the resistance trace, each connection pad and the resistance trace Electrically connected to separate resistor traces into segments of resistors in series. The power semiconductor device disclosed in the present application integrates an external resistor into the gate structure, thereby reducing the difficulty of voltage control of the gates of the IGBT and MOSFET devices and improving the accuracy.
Description
Technical Field
The present disclosure relates to the field of semiconductor technologies, and in particular, to a power semiconductor device and a method for manufacturing the same.
Background
Power semiconductor devices are widely used in various circuits such as power control circuits and driver circuits. Especially, the system has irreplaceable effects in the fields of various motors, photovoltaic inversion, smart power grids, new energy vehicles, electric locomotive traction drive and the like. With the development of power Semiconductor technology over several decades, IGBTs (Insulated Gate Bipolar Transistor) and MOSFETs (Metal-Oxide-Semiconductor Field-Effect-Transistor) gradually become mainstream devices in the Field of power electronics today.
The IGBT and the MOSFET are packaged into a single tube for use. In the whole circuit system, the control chip and other peripheral circuits of the IGBT and the MOSFET are driven, and the IGBT and the MOSFET are controlled to be switched on or switched off by the voltage acting on the grid electrodes of the IGBT and the MOSFET. IGBTs and MOSFETs are also packaged into modules for use. In the module, the driving IC controls the on or off of the IGBT and MOSFET devices by controlling the voltage applied to the gates of the IGBT and MOSFET devices. However, in any application, the resistance of the connecting gate has a great influence on the voltage on the gate, and even directly leads to the failure and damage of the whole circuit system or module. Therefore, in the peripheral circuit, some resistor devices are usually required to be added for adjustment, and in the module, the gate resistance and the wire bonding length of the device need to be precisely controlled, and even IGBT or MOSFET devices with different gate resistances need to be matched according to different wire bonding lengths.
The operation difficulty of the mode for controlling the voltage acting on the grids of the IGBT and the MOSFET device is higher, and the accuracy is not easy to control.
Disclosure of Invention
The application provides a power semiconductor device, with external resistance integrated to the grid structure on to reduce the voltage of IGBT and MOSFET device grid and control the degree of difficulty, improve the precision.
In order to achieve the above object, the present application provides a power semiconductor device including: a gate structure and a plurality of cell structures;
the grid structure comprises a resistance area and a wiring area;
the wiring region is provided with a connection metal layer, and the grid electrode of the cellular structure is electrically connected with the connection metal layer of the wiring region;
the resistance area comprises a resistance wire and a plurality of connecting bonding pads distributed along the extending direction of the resistance wire, and each connecting bonding pad is electrically connected with the resistance wire so as to divide the resistance wire into a plurality of sections of resistors which are connected in series.
The power semiconductor device in this application, grid structure include resistance district and wiring district, and wherein, the resistance district is walked including resistance and is walked a plurality of connection pads that the extending direction that walks along resistance distributes, and each connection pad is walked the line electricity with resistance and is connected, walks the line with resistance and separates for multistage resistance, and a plurality of resistance establish ties each other. Therefore, two connecting bonding pads at different positions are selected to be respectively connected with the power supply wiring and the connecting metal layer; or, selecting a connection pad at a determined position to be connected with the external wiring of the power supply, and selecting connection pads at different positions to be connected with the connection metal layer; or selecting connection pads at different positions to be connected with external wiring of the power supply, and selecting a connection pad at a determined position to be connected with the connection metal layer; so as to adjust the resistance value accessed by the wiring area, and further ensure that the voltage entering each cellular structure is the same. By adopting the mode, the resistance value of the resistor connected with the connecting metal layer in series can be conveniently and rapidly adjusted, and then the voltage of each cell structure connected with the connecting metal layer can be accurately adjusted.
Preferably, the resistance area further includes a substrate layer, a first dielectric layer and a second dielectric layer, the first dielectric layer is disposed on the substrate layer, the resistance wire is disposed on the first dielectric layer, the second dielectric layer is disposed between the resistance wire and the connection pad, a plurality of via holes are disposed in the second dielectric layer along the direction of the resistance wire, the connection pad is disposed above the via holes, and one end of the connection pad penetrates through the via holes to be electrically connected with the resistance wire.
Preferably, the resistor area further includes a substrate layer and a dielectric layer, the dielectric layer is located above the connection pads, the dielectric layer is provided with a plurality of hollow portions, the hollow portions and the connection pads are arranged in a one-to-one correspondence manner, and routing wires pass through the hollow portions and the connection pads corresponding to the hollow portions to be connected with the resistor routing wires.
Preferably, the material of the resistance trace is a polysilicon material after doping treatment.
Another object of the present invention is to provide a method for manufacturing a power semiconductor device, comprising the following steps;
forming a resistance layer on the base layer, and forming a resistance wire through a composition process;
the method comprises the steps of forming a metal layer on a resistor layer, forming a plurality of connecting bonding pads located in a resistor area and a connecting metal layer located in a wiring area through a composition process, wherein the connecting bonding pads are distributed along the extending direction of a resistor wire, and each connecting bonding pad is electrically connected with the resistor wire so as to divide the resistor wire into a plurality of sections of resistors which are connected in series.
Preferably, before forming the resistive layer, further comprising:
a dielectric layer is deposited on the base layer.
Preferably, after forming the resistive trace and before forming the metal layer on the resistive layer, the method further includes:
and depositing a dielectric layer on the resistor layer, and performing a composition process on the dielectric layer to form a plurality of via holes which are distributed along the extending direction of the resistor routing and correspond to the connecting pads one by one.
Preferably, the base layer is a semiconductor silicon epitaxial silicon wafer or a monocrystalline silicon wafer grown by a zone melting method.
Preferably, the resistive layer formed on the base layer includes:
forming a polysilicon layer on the base layer;
the polysilicon layer is doped to form the resistive layer.
Preferably, the forming of the metal layer on the resistive layer includes:
the metal layer is formed through a sputtering process or an evaporation process.
Drawings
Fig. 1 is a top view of a resistive layer of a power semiconductor device according to a first embodiment of the present disclosure;
fig. 2 is a top view of a dielectric layer of a power semiconductor device according to a first embodiment of the present disclosure;
fig. 3 is a top view of a metal layer of a power semiconductor device according to a first embodiment of the present disclosure;
fig. 4 is a perspective view of a stack of a dielectric layer and a resistive layer of a power semiconductor device according to a first embodiment of the present application;
fig. 5 is a perspective view showing a metal layer, a dielectric layer and a resistive layer of a power semiconductor device according to a first embodiment of the present application, which are stacked in this order;
fig. 6 is a side view of a power semiconductor device in accordance with one embodiment of the present application;
fig. 7 is a flowchart of a method for manufacturing a power semiconductor device according to a second embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Example 1
Referring to fig. 1 to 6, the present application provides a power semiconductor device, including: a gate structure and a plurality of cell structures;
the grid structure comprises a resistance region 1 and a wiring region 2;
the wiring region 2 is provided with a connecting metal layer, and the grid electrode of the cellular structure is electrically connected with the connecting metal layer of the wiring region 2;
the resistor area 1 includes a resistor trace 10 and a plurality of connection pads 120 distributed along an extending direction of the resistor trace 10, and each connection pad 120 is electrically connected to the resistor trace 10 to divide the resistor trace 10 into a plurality of series-connected resistors.
In the power semiconductor device in the embodiment of the application, the gate uniform wiring regions 2 of each unit cell structure are connected by the connecting metal layer 12; the resistance region 1 in the gate structure includes a resistance trace 10 and a plurality of connection pads 120 distributed along the extending direction of the resistance trace 10, and because each connection pad 120 is electrically connected to the resistance trace 10 to divide the resistance trace 10 into a plurality of sections of resistances, and the plurality of sections of resistances are connected in series, any two connection pads 120 in the plurality of connection pads 120 can be connected to an external power trace and a connection metal layer respectively; or, selecting a connection pad 120 at a certain position to be connected with the external power supply wiring, and selecting connection pads 120 at different positions to be connected with the connection metal layer; or, selecting the connection pads 120 at different positions to be connected with external power routing, and selecting the connection pad 120 at a determined position to be connected with the connection metal layer; the resistance between the two connection pads 120 is selected according to the voltage required by the cell structure connected to the metal layer, so that the voltage at the cell structure is the required voltage. In the prior art, the grid of the cellular structure needs to be connected with an external resistance component in series for adjustment, or the resistance and routing length at the cellular junction grid need to be accurately controlled; in the embodiment of the present application, in order to ensure that the voltage entering the gates of the cell structures is a set voltage, one of the connection pads 120 is used for being connected to an external power trace, and the other of the connection pads 120 is used for being connected to a connection metal layer of the wiring region 2, and the two connection pads 120 at different positions are selected to adjust the resistance value connected in series with the gates of the cell structures, so that the voltage value at the gates of the cell structures is a required voltage value.
It is assumed that the resistance values of the resistor trace 10 between two adjacent connection pads 120 are both α, and when a resistor with a resistance value of 3 α is required to be connected in series at the gate of the cell structure, one of the connection pads 120 is connected to the external power trace, and a connection pad 120 is provided between another one of the connection pads 120 and one of the connection pads 120, so that the resistance between another one of the connection pads 120 and one of the connection pads 120 is 3 α.
Or, one connection pad 120 connected to the external power trace among the connection pads 120 is located above the end of the resistance trace 10, and another connection pad 120 is located according to the actually required serial resistance value.
As an optional mode, the resistance region 1 further includes a substrate layer 13, a first dielectric layer and a second dielectric layer 11, the first dielectric layer is disposed on the substrate layer 13, the resistance trace 10 is disposed on the first dielectric layer, the second dielectric layer 11 is disposed between the resistance trace 10 and the connection pad 120, a plurality of via holes 110 are disposed in the second dielectric layer 11 along the direction of the resistance trace 10, the connection pad 120 is located above the via holes 110, and one end of the connection pad 120 penetrates through the via holes 110 and is electrically connected to the resistance trace 10.
In this embodiment, the resistor trace 10 is disposed on the first dielectric layer, and the second dielectric layer 11 is disposed between the resistor trace 10 and the connection pads 120, where the second dielectric layer 11 can separate the resistor trace 10 from the connection pads 120, so as to facilitate the arrangement of the connection pads 120; and the second dielectric layer 11 is provided with a plurality of via holes 110 along the extending direction of the resistor trace 10, the via holes 110 and the connection pads 120 are arranged in a one-to-one correspondence manner, and when the connection pads 120 are arranged above the via holes 110, the connection pads penetrate through the via holes 110 and are electrically connected with the resistor trace 10, so that the resistor trace 10 is divided into a plurality of sections of resistors, and a resistance value connected in series with a gate of a cellular structure is convenient to adjust.
As an optional mode, the resistance region 1 further includes a substrate layer 13 and a dielectric layer, the dielectric layer is located above the connection pad 120, the dielectric layer is provided with a plurality of hollow portions, the hollow portions are arranged in one-to-one correspondence with the connection pads 120, and the routing passes through the hollow portions and is electrically connected with the corresponding connection pads 120.
In this embodiment, the dielectric layer is disposed above the connection pad 120, and a hollow portion is disposed on the dielectric layer at a position corresponding to the connection pad 120, the routing wire passes through the hollow portion and is electrically connected to the connection pad 120, and the hollow portion is disposed to enable the connection pad 120 to be conveniently and electrically connected to the connection metal layer.
As an optional manner, the material of the resistor trace 10 is a polysilicon material after doping treatment.
In this embodiment, the material of the resistor trace 10 is preferably a polysilicon material after doping treatment, and the resistivity of the polysilicon material can be adjusted by adjusting the doping, so as to further adjust the resistance value of the resistor trace 10.
Example 2
Referring to fig. 7, another objective of the present invention is to provide a method for manufacturing a power semiconductor device, including the following steps;
forming a resistance layer on the base layer, and forming a resistance wire 10 through a composition process;
forming a metal layer 12 on the resistor layer, and forming a plurality of connection pads 120 located in the resistor region 1 and a connection metal layer 12 located in the wiring region 2 by a patterning process, wherein the connection pads 120 are distributed along the extending direction of the resistor trace 10, and each connection pad 120 is electrically connected with the resistor trace 10 to divide the resistor trace 10 into a plurality of sections of resistors connected in series with each other.
In this embodiment, the resistive layer and the metal layer 12 are formed on the power semiconductor device substrate, and the resistive trace 10 formed by the resistive layer, the plurality of connection pads 120 formed on the metal layer 12 and located in the resistive region 1, and the connection metal layer 12 formed on the wiring region 2 are formed by a patterning process, so that the manufacturing method of the power semiconductor device is relatively simple and is convenient to produce.
As an alternative, before forming the resistive layer 10, the method further comprises:
a dielectric layer is deposited on the base layer.
As an alternative, after forming the resistive trace 10 and before forming the metal layer 12 on the resistive layer, the method further includes:
a dielectric layer is deposited on the resistive layer, and a patterning process is performed on the dielectric layer to form a plurality of via holes 110 distributed along the extending direction of the resistive trace 10 and corresponding to the connection pads 120 one to one.
In this embodiment, a dielectric layer is deposited on the resistive layer to separate the metal layer 12 from the resistive layer, a plurality of vias 110 are formed on the dielectric layer through a patterning process, the vias 110 are disposed to facilitate electrical connection between the connection pads 120 and the resistive traces 10, and the formation of the vias 110 through the patterning process can provide a manufacturing speed of the power semiconductor device.
As an alternative, the base layer is a semiconductor silicon epitaxial wafer or a monocrystalline wafer grown by a float zone method.
As an alternative, the forming of the resistive layer on the base layer includes:
forming a polysilicon layer on the base layer;
the polysilicon layer is doped to form the resistive layer.
As an alternative, the forming of the metal layer 12 on the resistive layer includes:
the metal layer 12 is formed through a sputtering process or an evaporation process.
It will be apparent to those skilled in the art that various changes and modifications may be made in the embodiments of the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (10)
1. A power semiconductor device, comprising: a gate structure and a plurality of cell structures;
the grid structure comprises a resistance area and a wiring area;
the wiring region is provided with a connection metal layer, and the grid electrode of the cellular structure is electrically connected with the connection metal layer of the wiring region;
the resistance area comprises a resistance wire and a plurality of connecting bonding pads distributed along the extending direction of the resistance wire, and each connecting bonding pad is electrically connected with the resistance wire so as to divide the resistance wire into a plurality of sections of resistors which are connected in series.
2. The power semiconductor device according to claim 1, wherein the resistor region further includes a substrate layer, a first dielectric layer and a second dielectric layer, the first dielectric layer is disposed on the substrate layer, the resistor trace is disposed on the first dielectric layer, the second dielectric layer is disposed between the resistor trace and the connection pad, a plurality of via holes are disposed in the second dielectric layer along a direction of the resistor trace, the connection pad is disposed above the via holes, and one end of the connection pad penetrates through the via holes and is electrically connected to the resistor trace.
3. The power semiconductor device according to claim 1, wherein the resistor region further comprises a substrate layer and a dielectric layer, the dielectric layer is located above the connection pads, a plurality of hollowed portions are arranged on the dielectric layer, the hollowed portions are arranged in one-to-one correspondence with the connection pads, and routing wires pass through the hollowed portions and are connected with the corresponding connection pads.
4. The power semiconductor device according to claim 1, wherein the material of the resistive trace is a doped polysilicon material.
5. A method for manufacturing a power semiconductor device is characterized by comprising the following steps;
forming a resistance layer on the base layer, and forming a resistance wire through a composition process;
the method comprises the steps of forming a metal layer on a resistor layer, forming a plurality of connecting bonding pads located in a resistor area and a connecting metal layer located in a wiring area through a composition process, wherein the connecting bonding pads are distributed along the extending direction of a resistor wire, and each connecting bonding pad is electrically connected with the resistor wire so as to divide the resistor wire into a plurality of sections of resistors which are connected in series.
6. The method for manufacturing a power semiconductor device according to claim 5, further comprising, before forming the resistive layer:
a dielectric layer is deposited on the base layer.
7. The method for manufacturing a power semiconductor device according to claim 5, further comprising, after forming the resistive trace and before forming the metal layer on the resistive layer:
and depositing a dielectric layer on the resistor layer, and performing a composition process on the dielectric layer to form a plurality of via holes which are distributed along the extending direction of the resistor routing and correspond to the connecting pads one by one.
8. The method for manufacturing a power semiconductor device according to claim 5, wherein the base layer is a semiconductor silicon epitaxial wafer or a single crystal silicon wafer grown by a float zone method.
9. The method for manufacturing a power semiconductor device according to claim 5, wherein the forming of the resistive layer on the base layer includes:
forming a polysilicon layer on the base layer;
the polysilicon layer is doped to form the resistive layer.
10. The method for manufacturing a power semiconductor device according to claim 5, wherein the forming of the metal layer on the resistive layer comprises:
the metal layer is formed through a sputtering process or an evaporation process.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910818893.3A CN112447679A (en) | 2019-08-30 | 2019-08-30 | Power semiconductor device and manufacturing method thereof |
| PCT/CN2020/097746 WO2021036445A1 (en) | 2019-08-30 | 2020-06-23 | Power semiconductor device and fabrication method therefor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910818893.3A CN112447679A (en) | 2019-08-30 | 2019-08-30 | Power semiconductor device and manufacturing method thereof |
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| CN112447679A true CN112447679A (en) | 2021-03-05 |
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| CN201910818893.3A Pending CN112447679A (en) | 2019-08-30 | 2019-08-30 | Power semiconductor device and manufacturing method thereof |
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| CN (1) | CN112447679A (en) |
| WO (1) | WO2021036445A1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2022188703A1 (en) * | 2021-03-12 | 2022-09-15 | 重庆万国半导体科技有限公司 | Gate resistance adjustable super-junction power device and manufacturing method therefor |
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| WO2021036445A1 (en) | 2021-03-04 |
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