CN112416436B - Information processing method, information processing device and electronic equipment - Google Patents

Abstract

An information processing method, an information processing device, and electronic equipment. The information processing method includes: acquiring read information of a historical read request, where the historical read request indicates the first stored information requested to be read by the processor core at historical moments, and the read information includes the historical virtual address and the historical virtual address of the first stored information Physical address; according to the historical virtual address, predict the predicted virtual address where the processor core requests to read the second storage information at a future moment; judge whether the predicted virtual address and the historical virtual address are in the same virtual address page; respond to the predicted virtual address The address and the historical virtual address are in the same virtual address page, and the first predicted physical address is determined according to the historical virtual address, the historical physical address and the predicted virtual address. The information processing method can improve the timeliness of pre-extracting information.

Description

Information processing method, information processing device and electronic equipment

technical field

Embodiments of the present disclosure relate to an information processing method, an information processing device, and electronic equipment.

Background technique

Instruction data prefetching is one of the key technologies for improving the performance of a high-performance central processing unit (CPU). The cache can only hold data that has been recently accessed by the CPU core. When reading data that has never been accessed or data that has been kicked out due to cache size limitations, the CPU core still needs to wait for tens or even hundreds of clock cycles, resulting in performance loss. Instruction and data prefetching can prefetch the data to be used in advance according to the data access rules, thereby reducing the clock cycle of the CPU core waiting for data and improving the overall performance of the CPU.

Contents of the invention

At least one embodiment of the present disclosure provides an information processing method, including: acquiring read information of a historical read request, the historical read request is sent by the processor core of the processor, and the historical read request indicates that the processor core requested at a historical time Read the first storage information, the read information includes the historical virtual address and historical physical address of the first storage information, the historical physical address corresponds to the historical virtual address; according to the historical virtual address, predict the processor core to request to read at a future moment The predicted virtual address where the second storage information is located; judge whether the predicted virtual address and the historical virtual address are in the same virtual address page; in response to the predicted virtual address and the historical virtual address being in the same virtual address page, according to the historical virtual address, historical The physical address and the predicted virtual address determine a first predicted physical address, the first predicted physical address corresponding to the predicted virtual address.

For example, in the information processing method provided by an embodiment of the present disclosure, in response to the predicted virtual address and the historical virtual address being in the same virtual address page, the first predicted physical address is determined according to the historical virtual address, historical physical address and predicted virtual address , comprising: in response to the predicted virtual address and the historical virtual address being in the same virtual address page, taking the sum of the offset between the predicted virtual address and the historical virtual address and the historical physical address as the first predicted physical address.

For example, in the information processing method provided by an embodiment of the present disclosure, the processor includes a multi-level cache, and the multi-level cache includes at least a first-level cache and a second-level cache, and the first-level cache is a A cache that is connected and directly transmits data with the processor core, and the second-level cache is a cache that is electrically connected with the first-level cache and transmits data with the processor core through the first-level cache. The method also includes: determining the target of the second storage information Cache, the target cache includes a first-level cache or a second-level cache; judging whether the predicted virtual address and the historical virtual address are in the same virtual address page, including: in response to the target cache being the second-level cache, judging the predicted virtual address and the historical virtual address Whether the virtual address is in the same virtual address page.

For example, in the information processing method provided in an embodiment of the present disclosure, the processor further includes a prefetcher, and the method further includes: the prefetcher generates a first prefetch request according to the first predicted physical address, and the first prefetch request uses requesting to store the second storage information stored in the first predicted physical address into the second-level cache; the prefetcher sends the first prefetch request to the second-level cache; and the second-level cache responds to the first prefetch request, Cache the second storage information corresponding to the first predicted physical address in the second-level cache.

For example, in the information processing method provided by an embodiment of the present disclosure, the second-level cache caches the second storage information corresponding to the first predicted physical address in the second-level cache in response to the first prefetch request, including: The second level cache determines whether the second storage information corresponding to the first predicted physical address has been cached in the second level cache in response to the first prefetch request; in response to the second storage information corresponding to the first predicted physical address has been cached in the second level cache 2. Store information, discard the first prefetch request; and in response to the second level cache not caching the second storage information corresponding to the first predicted physical address, the second level cache fetches the first predicted physical address corresponding to the next level cache or memory the second storage information, and store the second storage information in the second-level cache.

For example, in the information processing method provided in an embodiment of the present disclosure, the prefetcher sends the first prefetch request to the second-level cache, including: the prefetcher sends the first prefetch request to the prefetch queue, so as to pass the prefetch The queue stores the first prefetch request; and in response to the free space in the second level cache, the prefetch queue sends the first prefetch request to the second level cache.

For example, in the information processing method provided by an embodiment of the present disclosure, the prefetcher sends the first prefetch request to the second-level cache, and further includes: in response to the storage space of the prefetch queue being full, discarding the first prefetch request request, or replace other prefetch requests in the prefetch queue with the first prefetch request.

For example, in the information processing method provided by an embodiment of the present disclosure, the processor further includes an address translation pipeline, and the method further includes: responding to the fact that the predicted virtual address and the historical virtual address are not in the same virtual address page, using the address translation pipeline to pair the predicted virtual address The address is translated to obtain the second predicted physical address.

For example, in the information processing method provided in an embodiment of the present disclosure, the information processing method further includes: the address translation pipeline generates a second prefetch request according to the second predicted physical address, and sends the second prefetch request to the prefetch queue; The prefetch queue sends a second prefetch request to the second-level cache in response to the second prefetch request; the second-level cache determines whether the second predicted physical address has been cached in the second-level cache in response to the second prefetch request Corresponding second storage information; in response to the second storage information corresponding to the second predicted physical address has been cached in the second-level cache, discarding the second prefetch request; in response to the second predicted physical address not being cached in the second-level cache Corresponding to the second storage information, the second-level cache fetches the second storage information corresponding to the second predicted physical address from the next-level cache or memory, and stores the second storage information in the second-level cache.

For example, in the information processing method provided by an embodiment of the present disclosure, when there are multiple predicted virtual addresses and the multiple predicted virtual addresses are in the same virtual address page, in response to the fact that the predicted virtual address and the historical virtual address are not in the same In a virtual address page, performing address translation on the predicted virtual address through an address translation pipeline to obtain a second predicted physical address includes: responding to multiple predicted virtual addresses not being in the same virtual address page as the historical virtual address, passing the address The translation pipeline performs address translation on a selected predicted virtual address among the multiple predicted virtual addresses to obtain a second predicted physical address; A second predicted physical address corresponding to other predicted virtual addresses other than the selected predicted virtual address.

For example, in the information processing method provided by an embodiment of the present disclosure, the selected predicted virtual address is the predicted virtual address that is first accessed by the processor core among the multiple predicted virtual addresses predicted by the prefetcher.

For example, in the information processing method provided by an embodiment of the present disclosure, the prefetch queue and the address translation pipeline share the same interface of the address cache, or the prefetch queue and the address translation pipeline respectively occupy different interfaces in the address cache.

For example, in the information processing method provided in an embodiment of the present disclosure, the information processing method further includes: in response to the target cache being the first-level cache, sending a third prefetch request to the address translation pipeline, so that the third prefetch request arrives The address translation pipeline, the third prefetch request includes a predicted virtual address; the address translation pipeline responds to the third prefetch request, translates the predicted virtual address into a third predicted physical address, and generates a fourth prefetch request according to the third predicted physical address ; Determine whether the second storage information corresponding to the third predicted physical address has been cached in the first-level cache; in response to the second storage information corresponding to the third predicted physical address has been cached in the first-level cache, discarding the fourth prefetch request; in response to the second storage information corresponding to the third predicted physical address not being cached in the first-level cache, sending a fourth prefetch request to the address cache, so that the address cache sends a fourth prefetch request to the second-level cache; the second The level cache extracts the second storage information corresponding to the third predicted physical address in response to the fourth prefetch request from the address cache, and sends the extracted second storage information to the address cache, so that the address cache sends the extracted second storage information to the first level cache. 2. Store information.

For example, in the information processing method provided by an embodiment of the present disclosure, judging whether the predicted virtual address and the historical virtual address are in the same virtual address page includes: determining the page size of the virtual address page where the historical virtual address is located; and based on The page size of the virtual address page determines whether the predicted virtual address and the historical virtual address are in the same virtual address page.

At least one embodiment of the present disclosure further provides an information processing device, including: an acquisition unit configured to acquire read information of a historical read request, the historical read request is sent by the processor core of the processor, and the historical read request indicates that the The processor core requests to read the first storage information at the historical moment, and the read information includes the historical virtual address and the historical physical address of the first storage information, and the historical physical address corresponds to the historical virtual address; the prediction unit is configured to, according to the historical virtual address, Predicting the predicted virtual address where the processor core requests to read the second storage information at a future moment; the judging unit is configured to judge whether the predicted virtual address and the historical virtual address are in the same virtual address page; and the address determining unit is configured to In response to the predicted virtual address being in the same virtual address page as the historical virtual address, a first predicted physical address is determined according to the historical virtual address, the historical physical address, and the predicted virtual address, the first predicted physical address corresponding to the predicted virtual address.

At least one embodiment of the present disclosure further provides an electronic device, including: a processor configured to implement instructions of the information processing method provided by any embodiment of the present disclosure.

Description of drawings

In order to illustrate the technical solutions of the embodiments of the present disclosure more clearly, the accompanying drawings of the embodiments will be briefly introduced below. Obviously, the accompanying drawings in the following description only relate to some embodiments of the present disclosure, rather than limiting the present disclosure .

FIG. 1 shows a schematic flowchart of a CPU core reading instructions or data;

FIG. 2 shows a schematic flow chart of prefetching data information by using a prefetcher;

Fig. 3 shows a flowchart of an information processing method provided by at least one embodiment of the present disclosure;

Fig. 4A shows a flowchart of another information processing method provided by at least one embodiment of the present disclosure;

Fig. 4B shows a schematic flowchart of an information processing method provided by at least one embodiment of the present disclosure;

Fig. 5 shows a flowchart of another information processing method provided by at least one embodiment of the present disclosure;

Fig. 6 shows a flowchart of another information processing method provided by at least one embodiment of the present disclosure;

Fig. 7 shows a schematic block diagram of an information processing device provided by at least one embodiment of the present disclosure;

Fig. 8 is a schematic block diagram of an electronic device provided by some embodiments of the present disclosure; and

Fig. 9 is a schematic block diagram of another electronic device provided by some embodiments of the present disclosure.

Detailed ways

In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present disclosure. Apparently, the described embodiments are some of the embodiments of the present disclosure, not all of them. Based on the described embodiments of the present disclosure, all other embodiments obtained by persons of ordinary skill in the art without creative effort fall within the protection scope of the present disclosure.

Unless otherwise defined, the technical terms or scientific terms used in the present disclosure shall have the usual meanings understood by those skilled in the art to which the present disclosure belongs. "First", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Likewise, words like "a", "an" or "the" do not denote a limitation of quantity, but mean that there is at least one. "Comprising" or "comprising" and similar words mean that the elements or items appearing before the word include the elements or items listed after the word and their equivalents, without excluding other elements or items. Words such as "connected" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "Down", "Left", "Right" and so on are only used to indicate the relative positional relationship. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

In a typical CPU architecture, program instructions and data are stored in memory, and the operating frequency of the CPU core is much higher than that of the memory. Therefore, obtaining data or instructions from the memory requires hundreds of CPU core clocks, which often causes the CPU core to idle because it cannot continue to run related instructions, resulting in performance loss. Therefore, modern high-performance CPU cores include a multi-level cache architecture to store recently accessed data, and at the same time use the prefetcher to discover the rules of CPU data access to prefetch the data and instructions to be accessed into the cache in advance. If it prefetches instructions, it is called an instruction prefetcher, and if it prefetches data, it is called a data prefetcher. The L1 (first level) cache prefetcher can prefetch instructions or data to the first level cache. However, due to the limited capacity of the L1 cache, excessively aggressive L1 cache prefetch will replace the original useful instructions or data in the L1 cache, causing overall performance loss instead. In order to cope with the above situation, since the capacity of the L2 (second level) cache is much larger than that of the L1 cache, the L2 cache prefetcher or the L1/L2 composite prefetcher can choose to prefetch these instructions or data to the L2 cache first. , and then prefetched into the L1 cache. The L2 cache prefetcher can prefetch instructions or data to the second-level cache, and the L1/L2 composite prefetcher can choose to prefetch these instructions or data into the L2 cache first or prefetch these instructions or data into the L1 cache middle.

For example, the L1 prefetcher may include an L1I (L1 Instruction, L1 instruction) prefetcher and an L1D (L1 Data, L1 data) prefetcher. The L1I prefetcher is used to prefetch instructions and the L1D prefetcher is used to prefetch data. It should be understood that the prefetcher in this paper may be an L1I prefetcher or an L1D prefetcher.

In addition, modern operating systems often support multiple processes running at the same time. In order to simplify multi-process management and enhance security, the application program uses a complete virtual address. For example, a 32-bit application program has a maximum of 2^32=4GB of virtual address space available. The virtual address space is mapped into multiple memory pages, and each memory page has its own physical storage address. For example, a segment of continuous virtual addresses is mapped to a memory page, and in this disclosure, the segment of continuous virtual addresses is called a virtual address page.

When a program accesses instructions and data, it must first translate their virtual addresses into physical addresses, and check whether the program's access is legal, and then go to the memory or cache to obtain the corresponding data and pass it to the CPU core. The process of converting from a virtual address to a physical address is called address translation. The mapping relationship between virtual addresses and physical addresses is stored in memory tables, and accessing these tables in memory also requires hundreds of clocks. In order to reduce these memory accesses, the CPU core uses a multi-level cache to store recently used mappings. These specific caches are called Table LookasideBuffer (TLB).

FIG. 1 shows a schematic flow chart of reading instructions or data by a CPU core.

As shown in FIG. 1 , reading instructions or data by the CPU core includes steps S110-S180.

Step S110: The CPU core provides the virtual address of the instruction or data to be read.

Step S120: Use the address translation pipeline to translate the virtual address into a physical address, and determine whether the instruction or data corresponding to the physical address is cached in the first-level cache. An address translation pipeline that translates virtual addresses into physical addresses may be included in the CPU. The address translation pipeline may include, for example, a logic circuit that performs operations according to the operation logic, and the logic circuit performs a series of operations according to the operation logic to translate a virtual address into a physical address.

For example, the address translation pipeline can translate a virtual address into a physical address by accessing a mapping relationship between a virtual address and a physical address cached in the TLB.

For example, the address translation pipeline may send a request to the first-level cache to acquire multiple tags in the first-level cache, and each of the multiple tags may perform a hash operation on the physical address cached in the first-level cache owned. Then, the address translation pipeline can perform a hash operation on the physical address to obtain a hash value, and compare the hash value with multiple tags obtained from the first-level cache. If multiple tags contain the hash value, it indicates that the instruction or data corresponding to the physical address is cached in the first-level cache. If the hash value is not included in multiple tags, it indicates that the instruction or data corresponding to the physical address is not cached in the first-level cache.

If the instruction or data corresponding to the physical address is cached in the first-level cache, step S130 and step S140 are executed. If the first-level cache does not cache the instruction or data corresponding to the physical address, execute steps S150-S180.

Step S130: Send a read request to the first-level cache.

Step S140: In response to the read request, the first-level cache fetches the instruction or data corresponding to the physical address from the first-level cache, and sends the instruction or data corresponding to the physical address to the CPU core in response to the read request.

Step S150: apply for a storage space from the address cache, and the storage space is used to store relevant information of the read request. The address cache may be, for example, a Missing Address Buffer (abbreviated as MAB) or a Missing Status Handling Register (abbreviated as MSHR).

The MAB or MSHR may be used to cache relevant information of the read request when the first level cache does not cache the instruction or data requested by the read request or the prefetch request. That is, when a read request or a prefetch request requests an instruction or data that is not in the first level cache and needs to be requested to the next level cache, the relevant information of the read request or prefetch request can be obtained by Stored in the MAB until the next level of cache returns the data information of the read request or prefetch request.

For example, in step S150, it may be to apply for a MAB item from the MAB, so that the MAB allocates a storage space, and sends the above-mentioned read request to the MAB.

Step S160: MAB sends a read request to the second-level cache.

Step S170: the second-level cache obtains the instruction or data corresponding to the physical address, and returns the instruction or data corresponding to the physical address to the MAB.

Step S180: MAB sends the instruction or data corresponding to the physical address to the first-level cache, so that the instruction or data corresponding to the physical address reaches the first-level cache, so that the first-level cache executes step S40, that is, sends the physical address to the CPU core. The instruction or data corresponding to the address.

Fig. 2 shows a schematic flowchart of prefetching data information by using a prefetcher. The prefetcher may be, for example, an L1/L2 composite prefetcher.

As shown in FIG. 2 , prefetching data information by using the L1/L2 composite prefetcher may include steps S210-S240, steps S251-S254, steps S261-S262, and steps S270-S280.

Step S210: The CPU core provides the virtual address of the instruction or data to be read.

Step S220: Use the address translation pipeline to translate the virtual address into a physical address, and send a read request including the physical address to the first-level cache and the L1/L2 composite prefetcher, so that the L1/L2 composite prefetcher uses the virtual address as The historical virtual address is trained by using the historical virtual address to obtain the predicted virtual address, and the first-level cache responds to the read request, and returns the instruction or data corresponding to the physical address to the CPU core.

Step S230: the L1/L2 composite prefetcher trains all or part of the historical virtual addresses, so as to predict the predicted virtual addresses of instructions or data to be acquired by the CPU core in the future.

Step S240: performing address translation on the predicted virtual address to obtain a predicted physical address, thereby generating a prefetch request according to the predicted physical address, and determining whether the first-level cache caches instructions or data corresponding to the predicted physical address. This step S240 is similar to the step S120 described above with reference to FIG. 1 , and will not be repeated here.

If the instruction or data corresponding to the predicted physical address is cached in the first-level cache, the prefetch request is discarded.

If the first-level cache does not cache the instruction or data corresponding to the physical address, if the prefetch request is an L1 prefetch request, then perform steps S251-S254 to prefetch the instruction or data into the L1 cache. If the prefetch request is an L2 prefetch request, then execute steps S261-S263 for prefetching instructions or data into the L2 cache.

Step S251: Apply for a MAB entry from the address buffer MAB, so that the MAB allocates the MAB entry, and send the above-mentioned L1 prefetch request to the MAB.

Step S252: the MAB sends an L1 prefetch request to the second-level cache.

Step S253: the second-level cache acquires the instruction or data corresponding to the predicted physical address, and returns the instruction or data corresponding to the predicted physical address to the MAB. The second-level cache, for example, may obtain the instruction or data corresponding to the predicted physical address from the next-level cache or itself. The second-level cache, for example, may perform step S270 and step S280 to obtain the instruction or data corresponding to the predicted physical address from the next-level cache, such as the last-level cache.

Step S254: The MAB sends the instruction or data corresponding to the physical address to the first-level cache, so that the instruction or data corresponding to the predicted physical address is cached in the first-level cache.

Step S261: Send the L2 prefetch request to the prefetch queue, so that the prefetch queue sends the L2 prefetch request to the second-level cache.

Step S262: the prefetch queue sends an L2 prefetch request to the second-level cache.

Step S263: the second-level cache judges whether the instruction or data corresponding to the predicted physical address in the L2 prefetch request has been cached in itself. If the cache is in itself, the L2 prefetch request is discarded. If it is not cached in itself, step S270 and step S280 are executed, so as to cache the instruction or data corresponding to the predicted physical address in the L2 prefetch request in the second-level cache.

Step S270: Send a prefetch request to the next-level cache, such as the last-level cache, so that the next-level cache can obtain the instruction or data corresponding to the predicted physical address.

Step S280: the last level cache sends the acquired instruction or data to the second level cache.

As shown in Figures 1 and 2, in a high-performance CPU, the prefetching process of instructions or data corresponding to the predicted virtual address predicted by the prefetcher (hereinafter referred to as "prefetching") corresponds to the virtual address issued by the CPU core. The normal reading process of instructions or data (hereinafter referred to as "normal reading") shares the address translation pipeline. In high-frequency, high-performance CPUs, the address translation pipeline may be multi-stage. Since prefetching has a lower priority than normal reading, a prefetch may need to wait for multiple clock cycles before it can enter the address translation pipeline, and the address translation itself also requires multiple pipeline clock cycles, so a prefetch requires multiple clocks Only then can it be sent to the next level cache. However, prefetching is often time-sensitive, and the corresponding CPU core access often occurs soon. The delay caused by address translation often causes the prefetched data to arrive at the first-level cache too late, resulting in invalid prefetching.

At least one embodiment of the present disclosure provides an information processing method, an information processing device, and an electronic device. The information processing method can determine the predicted physical address according to the historical physical address without obtaining the predicted physical address through an address translation pipeline, thereby reducing the time delay caused by address translation to prefetching and improving the timeliness of prefetching.

Fig. 3 shows a flowchart of an information processing method provided by at least one embodiment of the present disclosure. As shown in FIG. 3, the information processing method includes step S310-step S340.

Step S310: Obtain the read information of the historical read request. The history read request is sent by the processor core of the processor, the history read request indicates the first storage information that the processor core requests to read at the historical moment, and the read information includes the historical virtual address and the historical physical address of the first storage information, Historical physical addresses correspond to historical virtual addresses.

Step S320: According to the historical virtual address, predict the predicted virtual address where the second storage information that the processor core requests to read in the future is located.

Step S330: Determine whether the predicted virtual address and the historical virtual address are in the same virtual address page.

Step S340: In response to the fact that the predicted virtual address and the historical virtual address are in the same virtual address page, determine a first predicted physical address according to the historical virtual address, the historical physical address, and the predicted virtual address. The first predicted physical address corresponds to the predicted virtual address.

In the case that the predicted virtual address and the historical virtual address are in the same virtual address page, the information processing method can determine the first predicted physical address corresponding to the predicted virtual address according to the historical physical address corresponding to the historical virtual address. Address translation is performed on the virtual address, thereby at least partially avoiding the delay caused by address translation and improving the effectiveness of prefetching. In addition, since normal instruction and data reading often need to share the address translation pipeline with prefetching, this information processing method not only reduces the address translation of prefetching, but also reduces the address reading delay of normal reading, and reduces the prefetch Get the power consumption required for address translation.

For step S310, the historical reading request may be, for example, a reading request including historical virtual addresses issued by the CPU core at historical moments. The read information of the historical read request may include, for example, a historical virtual address and a historical physical address. The historical physical address may be obtained, for example, by performing address translation on the historical virtual address.

For example, the CPU core may send each read request to the address translation pipeline, and the address translation pipeline processes each read request in turn, so as to translate the virtual address in each read request into a physical address. Then the address translation pipeline sends the virtual address, physical address and other information corresponding to each read request to the prefetcher. These read requests are used as historical read requests, the virtual address corresponding to the read request is used as the historical virtual address, and the physical address translated from the historical virtual address is used as the historical physical address, so that the prefetcher uses the historical virtual address for training. In step S310, for example, the read information from the address translation pipeline may be received by the prefetcher. The prefetcher can be an L1 cache prefetcher, an L2 cache prefetcher, an L1/L2 composite prefetcher, or other prefetchers. The prefetcher can be an instruction prefetcher for prefetching instructions. The fetcher may also be a data prefetcher for prefetching data. In short, the present disclosure does not limit the type of cache prefetcher, and the method of the present disclosure is applicable to any prefetcher.

The first storage information may be, for example, instructions or data requested to be read by the CPU core at historical moments.

For step S320, for example, the prefetcher may train the historical virtual address to obtain the rule of the historical virtual address, so as to predict the predicted virtual address that the CPU core will access according to the rule, and the predicted physical address corresponding to the predicted virtual address stores the first 2. Store information.

For example, the historical virtual address includes 0X0000 0000, 0X0000 0002, 0X0000 0004, 0X0000 0006, then the prefetcher can predict that the predicted virtual address that the CPU core will access is 0X0000 0008.

For the prefetcher, using historical virtual address training to obtain CPU core access rules has the following advantages compared to using historical physical addresses. 1. The virtual address can be used by the prefetcher without address translation. 2. Using virtual addresses to train the prefetcher can discover the reading patterns across memory pages. Since two virtual address pages with consecutive virtual addresses may be allocated as discontinuous physical addresses, the prefetcher trained with physical addresses can only detect the reading pattern in one memory page, thus limiting the scope of the patterns it discovers. Accuracy and Validity. 3. The prefetcher is trained using virtual addresses to generate prefetch across memory pages. A prefetcher trained using physical addresses cannot generate a physical address for a memory page that has not been trained.

For step S330, for example, the page size of the virtual address page where the historical virtual address is located may be determined, and based on the page size of the virtual address page, it is determined whether the predicted virtual address and the historical virtual address are in the same virtual address page.

For example, the address range of each virtual address page may be determined according to the page size of the virtual address page, so as to determine whether the historical virtual address and the predicted virtual address are within the same address range. If they are in the same address range, it is judged that the predicted virtual address and the historical virtual address are in the same virtual address page.

For example, virtual addresses are numbered from 0, and the reference number of right-shifted bits can be determined according to the page size of the virtual address page, so that the predicted virtual address is right-shifted and the historical virtual address is right-shifted according to the right-shifted reference number of bits. If the two values obtained after the right shift of the predicted virtual address and the right shift of the historical virtual address are the same, then the predicted virtual address and the historical virtual address are in the same virtual address page.

For example, virtual addresses are numbered starting from 0, and the page size of the virtual address page is 4KB. Since 2 to the 12th power is equal to 4KB, you can compare whether the value obtained by shifting the predicted virtual address by 12 bits to the right and the historical virtual address by shifting 12 bits to the right equal to determine whether the predicted virtual address and the historical virtual address are in the same virtual address page. If the values obtained by right shifting the predicted virtual address by 12 bits and the right shifted 12 bits of the historical virtual address are equal, it can be determined that the predicted virtual address and the historical virtual address are in the same virtual address page.

It should be understood that although the page size of the virtual address page is 4KB in the above embodiment, the present disclosure is not limited to the virtual address page of 4KB. If a system can support the page size of multiple virtual address pages, then the size of the corresponding page can be sent to the prefetcher when training the prefetcher, so that the prefetcher can judge the historical virtual address and predict the virtual address based on the page size. Whether the address is in the same virtual address page, this can further increase the percentage of prefetch requests that do not require address translation, and improve the application range and performance of the information processing method provided by the present disclosure.

For step S340, if the predicted virtual address and the historical virtual address are in the same virtual address page, the first predicted physical address may be determined according to the historical virtual address, historical physical address and predicted virtual address.

In some embodiments of the present disclosure, for example, a sum of an offset between the predicted virtual address and the historical virtual address and the historical physical address may be used as the first predicted physical address. That is, the first predicted physical address may be calculated according to the following formula.

PPA＝HPA+(PVA－HVA)

Wherein, PPA represents the first predicted physical address, HPA represents the historical physical address, PVA represents the predicted virtual address, and HVA represents the historical virtual address.

The first predicted physical address of the predicted virtual address can be calculated very simply by using the above formula, thereby at least partly omitting the process of address translation.

In some embodiments of the present disclosure, the processor may include a multi-level cache, and the multi-level cache includes at least a first-level cache and a second-level cache. The first-level cache may be a cache that is electrically connected to the CPU core and can directly transmit data with the CPU core. The second-level cache is, for example, a cache that is electrically connected to the first-level cache and transmits data with the processor core through the first-level cache. For example, the processor includes a first-level cache, a second-level cache, ..., a last-level cache, and the storage capacity of the first-level cache, the second-level cache, ..., and the last-level cache can be sequentially increased, and the reading speed Decrease in turn, and the distance to the CPU core also increases in turn. For example, the first-level cache can be located closest to the CPU core, with the smallest storage capacity and the fastest read speed.

In some embodiments of the present disclosure, on the basis of the foregoing embodiments, the information processing method may further include determining the target cache of the second storage information, and the target cache includes the first-level cache or the second-level cache, and step S330 may be a response If the target cache is a second-level cache, it is determined whether the predicted virtual address and the historical virtual address are in the same virtual address page. That is, if the target cache is the second-level cache, it is judged whether the predicted virtual address and the historical virtual address are in the same virtual address page, so as to calculate the first predicted physical address for storing the second storage information according to the method provided in step S340.

In some other embodiments of the present disclosure, if the target cache is a first-level cache, the address translation pipeline may be used to obtain the third predicted physical address for storing the second storage information, and the second predicted physical address may be obtained from the third predicted physical address. The information is stored, and the second stored information is cached in the first-level cache. FIG. 6 below shows the implementation of this embodiment. For details, please refer to FIG. 6 and the corresponding description, and details will not be repeated here.

For example, if the prefetcher is an L1/L2 composite prefetcher, then the L1/L2 composite prefetcher may be a prefetcher for the second-level cache for the target cache, and calculate and store the second storage according to the method provided in step S340. The first predicted physical address of the information, and for the prefetch where the target cache is the first-level cache, the third predicted physical address for storing the second storage information can be obtained through an address translation pipeline.

In some other embodiments of the present disclosure, regardless of whether the target cache is the first-level cache or the second-level cache, the first predicted physical address for storing the second storage information may be calculated according to the method provided in step S340.

For example, in an embodiment where the target cache is the first-level cache and the first predicted physical address for storing the second storage information is calculated according to the method provided in step S340, the information processing method described above with reference to FIG. 3 may further include: The fetcher can generate a prefetch request according to the first predicted physical address, and send the prefetch request so that the prefetch request reaches the MAB, and the MAB sends the prefetch request to the second-level cache, and the second-level cache determines the second-level cache in response to the prefetch request. Whether the second storage information corresponding to the first predicted physical address has been cached in the level-1 cache. In response to the fact that the first-level cache has cached the second storage information corresponding to the first predicted physical address, the second-level cache notifies the address cache to discard the first prefetch request. In response to the fact that the first-level cache does not cache the second storage information corresponding to the first predicted physical address, the second-level cache extracts the second storage information corresponding to the first predicted physical address, and sends the extracted second storage information to the MAB, so that the MAB Sending the extracted second storage information to the first-level cache so that the second storage information is cached in the first-level cache.

In the above-mentioned embodiment, the second-level cache, for example, may be an Inclusive cache, so that it can be determined according to the state information in the second-level cache whether the first predicted physical address corresponding to the first-level cache has been cached. Second storage information. The second-level cache is an inclusive cache, that is, the second-level storage information stored in the second-level cache includes at least the first-level storage information stored in the first-level cache, and the second-level cache also includes state information. For example, the first-level storage information included in the first-level cache includes storage information A and storage information B, and if the second-level cache includes storage information, then the second-level storage information includes at least storage information A and storage information B. In addition to including storage information A and storage information B, the second-level storage information may also include storage information C and storage information D, for example.

The status information indicates whether the second-level storage information is located in the first-level cache, and whether the second-level storage information is located in the multi-level cache or in the internal memory. For example, if the second-level storage information includes storage information A, storage information B, and storage information C, then the second-level cache includes status information for each of storage information A, storage information B, and storage information C, and the status information may indicate that storage information A. Whether the storage information B and storage information C are cached in the first-level cache.

In some embodiments of the present disclosure, the second-level cache may include, for example, a logic circuit, and the logic circuit may obtain state information in the second-level cache, and judge the state information of the second storage information or the state of the first predicted physical address Whether the information is equal to the reference value. The reference value may be set by those skilled in the art according to actual requirements, for example, it may be 0 or 1. Step S355 is illustrated by taking a reference value of 1 indicating that the second-level storage information is in the first-level cache as an example. For example, the logic circuit can determine the state information of the second storage information from the second-level cache, and then the logic circuit can compare the state information with the reference value 1, and if the state information is equal to 1, it is determined that the first-level cache has cached the state information. Second storage information, if the state information is not equal to 1, it is determined that the second storage information is not cached in the first level cache.

In some embodiments of the present disclosure, the second storage information may be data or instructions. The second storage information may be stored in any level-1 cache in the multi-level cache of the processor, and the second storage information may also be stored in the memory. For example, if the second storage information is stored in the second-level cache, the second storage information is extracted from the second-level cache and cached in the first-level cache. If the second storage information is stored in the third-level cache, the second-level cache extracts the second storage information from the third-level cache and caches it in the first-level cache.

In some embodiments of the present disclosure, if the target cache is a second-level cache and the processor further includes a prefetcher, then the information processing method may further include the steps described below with reference to FIG. 4A on the basis of the foregoing embodiments.

Fig. 4A shows a flowchart of another information processing method provided by at least one embodiment of the present disclosure.

As shown in FIG. 4A , the information processing method may further include steps S350 to S370 on the basis of the foregoing embodiments.

Step S350: the prefetcher generates a first prefetch request according to the first predicted physical address. The first prefetch request is used to request to store the second storage information stored in the first predicted physical address into the second-level cache.

The prefetcher, for example, may be an L2 cache prefetcher or an L1/L2 composite prefetcher, and is used to cache the prefetched data information into the L2 cache.

Step S360: the prefetcher sends the first prefetch request to the second-level cache.

Step S370: the second-level cache caches the second storage information corresponding to the first predicted physical address in the second-level cache in response to the first prefetch request.

For example, in response to the first prefetch request, the second-level cache determines whether the second storage information corresponding to the first predicted physical address has been cached in the second-level cache. In response to the fact that the second level cache has cached the second storage information corresponding to the first predicted physical address, discarding the first prefetch request. In response to the fact that the second-level cache does not cache the second storage information corresponding to the first predicted physical address, the second-level cache fetches the second storage information corresponding to the first predicted physical address from the next-level cache or memory, and stores the second storage information in the second level cache.

In some embodiments of the present disclosure, in step S360, the prefetcher sending the first prefetch request to the second-level cache may include: the prefetcher sends the first prefetch request to the prefetch queue to pass the prefetch The fetch queue stores the first prefetch request, and in response to the free space in the second level cache, the prefetch queue sends the first prefetch request to the second level cache.

In the information processing method, a prefetching queue is added between the prefetcher and the second-level cache. The prefetch queue can cache the prefetch that does not require address translation, and then send these prefetches when the second-level cache can receive them, thus at least partially avoiding the loss of prefetch caused by the full storage space of the second-level cache .

In some embodiments of the present disclosure, those skilled in the art can set the size of the prefetch queue according to actual conditions.

In some embodiments of the present disclosure, the prefetcher sending the first prefetch request to the second-level cache further includes: in response to the storage space of the prefetch queue being full, discarding the first prefetch request, or using the first prefetch The fetch request replaces other prefetch requests in the prefetch queue.

For example, at least one other prefetch request queued at the end of the prefetch queue may be replaced with the first prefetch request.

In other embodiments of the present disclosure, the prefetcher may not send the first prefetch request to the second-level cache through the prefetch queue, but the prefetcher directly sends the first prefetch request to the second-level cache.

Fig. 4B shows a schematic flowchart of an information processing method provided by at least one embodiment of the present disclosure. The information processing method described above with reference to FIG. 3 and FIG. 4A will be described below with reference to FIG. 4B .

As shown in FIG. 4B , the information processing method may include the following operations.

Step S410: The CPU core gives the virtual address of the instruction or data to be read. The virtual address is, for example, the aforementioned historical virtual address.

Step S420: Use the address translation pipeline to translate the virtual address into a physical address, and send a read request including the physical address to the prefetcher, so that the prefetcher uses the virtual address as a historical virtual address and uses the historical virtual address to train And get the predicted virtual address. This physical address can be used as the aforementioned historical physical address.

Step S410 and step S420 may be a process for the prefetcher to obtain read information of historical read requests. For example, it may be performed according to the step S310 described in FIG. 3 above, which will not be repeated here.

Step S430: the prefetcher trains all or part of the historical physical addresses, so as to predict the predicted virtual addresses of instructions or data to be acquired by the CPU core at a future time. For example, it may be performed according to the step S320 described in FIG. 3 above, which will not be repeated here.

Step S440: Determine whether the predicted virtual address and the historical virtual address are in the same virtual address page. For example, it may be performed according to the step S330 described in FIG. 3 above, which will not be repeated here.

Step S450: In response to the predicted virtual address being in the same virtual address page as the historical virtual address, determine a first predicted physical address according to the historical virtual address, the historical physical address and the predicted virtual address. For example, it may be performed according to the step S340 described in FIG. 3 above, which will not be repeated here.

Step S460: the prefetcher generates a first prefetch request according to the first predicted physical address, and sends the first prefetch request to the prefetch queue. For example, step S350 described above in FIG. 4A may be performed, and details are not repeated here.

Step S470: the prefetch queue sends the first prefetch request to the second-level cache. For example, step S360 described above in FIG. 4A may be performed, and details are not repeated here.

Step S480: the second-level cache responds to the first prefetch request, and the second-level cache caches the second storage information corresponding to the first predicted physical address in the second-level cache in response to the first prefetch request. For example, step S370 described above in FIG. 4A may be performed. The second-level cache caches the second storage information corresponding to the first predicted physical address in the second-level cache in response to the first prefetch request, for example, it may include determining whether the first predicted physical address has been cached in the second-level cache. The second storage information, if the second-level cache determines that it has cached the second storage information, the second-level cache discards the first prefetch request. Or, if the second-level cache determines that it does not cache the second storage information, the second-level cache may extract the second storage information from the next-level cache or memory, so as to store the second storage information in itself. For example, the second-level cache can extract the second storage information from the last-level cache.

Fig. 5 shows a flowchart of another information processing method provided by at least one embodiment of the present disclosure.

As shown in FIG. 5 , the information processing method may further include step S510 on the basis of the method described in FIG. 3 .

Step S510: In response to the fact that the predicted virtual address and the historical virtual address are not in the same virtual address page, perform address translation on the predicted virtual address through the address translation pipeline to obtain a second predicted physical address.

As shown in FIG. 4B , for example, when the prefetcher determines that the predicted virtual address and the historical virtual address are not in the same virtual address page, the prefetcher may execute step S401 . Step S401 may include, for example, sending the predicted virtual address to an address translation pipeline, so that the address translation pipeline translates the predicted virtual address.

In some embodiments of the present disclosure, the predicted virtual address is sent to the address translation pipeline, for example, the prefetcher may generate a prefetch request containing the predicted virtual address according to the predicted virtual address, and send the predicted virtual address to the address translation pipeline The prefetch request of , to perform address translation on the predicted virtual address by the address translation pipeline.

In some other embodiments of the present disclosure, as shown in FIG. 5 , the information processing method may further include steps S520-S550.

Step S520: the address translation pipeline generates a second prefetch request according to the second predicted physical address, and sends the second prefetch request to the prefetch queue.

For example, the address translation pipeline translates the predicted virtual address into the second predicted physical address, generates the second prefetch request according to the second predicted physical address, and sends the second prefetch request to the prefetch queue.

Step S530: the prefetch queue sends the second prefetch request to the second level cache in response to the second prefetch request.

In response to the second prefetch request, the second-level cache determines whether the second storage information corresponding to the second predicted physical address has been cached in the second-level cache.

Step S540: In response to the fact that the second storage information corresponding to the second predicted physical address has been cached in the second-level cache, discard the second prefetch request.

Step S550: In response to the fact that the second storage information corresponding to the second predicted physical address is not cached in the second-level cache, the second-level cache fetches the second storage information corresponding to the second predicted physical address from the next-level cache or memory, and stores The second storage information is in the second level cache.

Steps S520 to S550 in FIG. 5 above will be described below in conjunction with FIG. 4B .

As shown in FIG. 4B, for example, when the prefetcher determines that the predicted virtual address and the historical virtual address are not in the same virtual address page, the prefetcher executes step S401, that is, sends the prefetcher containing the predicted virtual address to the address translation pipeline. Fetch requests, so that the address translation pipeline translates the predicted virtual address.

In response to receiving a prefetch request containing a predicted virtual address from the prefetcher, the address translation pipeline may execute step S402, translate the predicted virtual address to obtain a second predicted physical address, and generate a second predicted physical address according to the second predicted physical address. A prefetch request, and sending a second prefetch request to the prefetch queue.

Next, the prefetch queue executes step S470 in response to the second prefetch request. Step S470 may be that the prefetch queue sends a second prefetch request to the second-level cache.

In response to the second prefetch request, the second-level cache determines whether the second storage information corresponding to the second predicted physical address has been cached in the second-level cache. In response to the fact that the second storage information corresponding to the second predicted physical address has been cached in the second-level cache, the second prefetch request is discarded. In response to the fact that the second storage information corresponding to the second predicted physical address is not cached in the second-level cache, the second-level cache fetches the second storage information corresponding to the second predicted physical address from the next-level cache or memory, and stores the second storage information Information is stored in the second level cache. For example, step S540 or step S550 described above with reference to FIG. 5 may be executed, which will not be repeated here.

In some embodiments of the present disclosure, when there are multiple predicted virtual addresses and the multiple predicted virtual addresses are in the same virtual address page, in response to the predicted virtual address not being in the same virtual address page as the historical virtual address, Performing address translation on the predicted virtual address to obtain the second predicted physical address includes: in response to none of the multiple predicted virtual addresses being in the same virtual address page as the historical virtual address, performing the address translation on the multiple predicted virtual addresses performing address translation on the selected predicted virtual address to obtain a second predicted physical address, and determining other than the selected predicted virtual address among the plurality of predicted virtual addresses according to the second predicted physical address corresponding to the selected predicted virtual address A second predicted physical address corresponding to the predicted virtual address is predicted.

If the predicted virtual addresses corresponding to multiple consecutive prefetches are all in the same virtual address page, but not in the same page as any historical virtual address, then only the first prefetch in the multiple consecutive prefetches can be addressed. , and send the predicted physical address of the request to the prefetcher, so that the prefetch accessing the virtual address page does not need to perform address translation again.

For example, the prefetcher predicts that the predicted virtual addresses that the CPU core will read in the future include 0X0000 0008, 0X0000000B, and 0X0000 000D, and it can be determined that 0X0000 0008, 0X0000 000B, and 0X0000 000D are in the same virtual address page, then it can be read from 0X0000 0008 , 0X0000 000B and 0X0000 000D to select a predicted virtual address for address translation to obtain the second predicted physical address of the selected predicted virtual address. For example, the selected predicted virtual address is 0X0000 0008, and the address translation pipeline for 0X0000 0008 can be used to obtain the corresponding physical address of 0X0000 0008. Then calculate the physical addresses corresponding to 0X0000 000B and 0X0000 000D according to the physical address corresponding to 0X0000 0008. For example, an offset between the target predicted virtual address and the selected predicted virtual address may be calculated, and the sum of the offset and the selected predicted physical address may be used as the physical address corresponding to the target predicted virtual address. Take the target predicted virtual address as 0X0000 000B and the selected predicted virtual address as 0X00000008 as an example to illustrate the above calculation method. The physical address of 0X0000 000B is equal to the offset between 0X0000 000B and 0X0000 0008 plus the physical address corresponding to 0X0000 0008.

In some embodiments of the present disclosure, the selected predicted virtual address may be any one of the plurality of predicted virtual addresses. In some other embodiments of the present disclosure, the selected predicted virtual address is the predicted virtual address that is first accessed by the processor core among the multiple predicted virtual addresses predicted by the prefetcher, or the predicted virtual address among the multiple predicted virtual addresses, the prefetcher Fetcher first predicted predicted virtual address.

Fig. 6 shows a flowchart of another information processing method provided by at least one embodiment of the present disclosure.

As shown in FIG. 6 , the information processing method may further include steps S610 to S660 on the basis of the foregoing embodiments.

Step S610: In response to the fact that the target cache is the first-level cache, send a third prefetch request to the address translation pipeline, so that the third prefetch request reaches the address translation pipeline, and the third prefetch request includes the predicted virtual address.

For example, the prefetcher determines that the target cache is the first-level cache, and may send a third prefetch request to the address translation pipeline. The third prefetch request includes a predicted virtual address.

Step S620: The address translation pipeline translates the predicted virtual address into a third predicted physical address in response to the third prefetch request, and generates a fourth prefetch request according to the third predicted physical address.

The fourth prefetch request is a prefetch request including the third predicted physical address.

Step S630: Determine whether the second storage information corresponding to the third predicted physical address has been cached in the first-level cache.

For example, the address translation pipeline may determine whether the second storage information corresponding to the third predicted physical address has been cached in the first-level cache.

Step S640: Discard the fourth prefetch request in response to the fact that the second storage information corresponding to the third predicted physical address has been cached in the first-level cache.

If the second storage information corresponding to the third predicted physical address has been cached in the first-level cache, the address translation pipeline may directly discard the fourth prefetch request.

Step S650: In response to the fact that the second storage information corresponding to the third predicted physical address is not cached in the first level cache, send a fourth prefetch request to the address cache, so that the address cache sends the fourth prefetch request to the second level cache.

For example, if the second storage information corresponding to the third predicted physical address is not cached in the first-level cache, the address translation pipeline may send the fourth prefetch request to the MAB, so that the MAB sends the fourth prefetch request to the second cache.

Step S660: the second-level cache extracts the second storage information corresponding to the third predicted physical address in response to the fourth prefetch request from the address cache, and sends the extracted second storage information to the address cache, so that the address cache sends the first-level The cache sends the extracted second storage information.

For example, the second-level cache receives the fourth prefetch request from the MAB, extracts the second storage information corresponding to the predicted physical address from the next-level cache or itself, and returns the second storage information to the MAB, so that the MAB sends the second storage information to the first-level cache The extracted second stored information is sent.

The information processing method described in FIG. 6 will be further described below in conjunction with FIG. 4B. As shown in FIG. 4B , this embodiment may further include steps S401 to S406 on the basis of including the foregoing steps.

As shown in FIG. 4B , if the target cache is a first-level cache, the prefetcher may execute step S401. Step S401: Send the third prefetch request including the predicted virtual address to the address translation pipeline. For example, operation S610 described above with reference to FIG. 6 may be performed.

Step S403: The address translation pipeline translates the predicted virtual address into a third predicted physical address in response to the third prefetch request, and generates a fourth prefetch request according to the third predicted physical address.

The address translation pipeline also judges whether the second storage information corresponding to the third predicted physical address has been cached in the first-level cache. In response to the fact that the second storage information corresponding to the third predicted physical address has been cached in the first level cache, the fourth prefetch request is discarded. In response to the fact that the second storage information corresponding to the third predicted physical address is not cached in the first-level cache, a fourth prefetch request is sent to the MAB, so that the MAB sends the fourth prefetch request to the second-level cache. For example, operations S620˜S650 described above with reference to FIG. 6 may be performed.

Step S404: the MAB sends a fourth prefetch request to the second-level cache.

Step S405: the second-level cache extracts the second storage information corresponding to the third predicted physical address in response to the fourth prefetch request from the MAB, and sends the extracted second storage information to the MAB. For example, operation S660 described above with reference to FIG. 6 may be performed.

Step S406: the MAB sends the extracted second storage information to the first-level cache.

In some embodiments of the present disclosure, the prefetch queue and the address translation pipeline share the same interface of the address cache, thereby saving interface resources. Or, in some other embodiments of the present disclosure, the prefetch queue and the address translation pipeline respectively occupy different interfaces in the address cache. For example, a MAB interface exclusive to the prefetch queue may be added to the processor to reduce the prefetch delay.

Fig. 7 shows a schematic block diagram of an information processing apparatus 700 provided by at least one embodiment of the present disclosure.

For example, as shown in FIG. 7 , the information processing device 700 includes an acquisition unit 710 , a prediction unit 720 , a judgment unit 730 and an address determination unit 740 .

The acquiring unit 710 is configured to acquire read information of historical read requests. The history read request is sent by the processor core of the processor. The historical read request indicates that the processor core requests to read the first stored information at historical moments. The read information includes a historical virtual address and a historical physical address of the first stored information, and the historical physical address corresponds to the historical virtual address. The acquiring unit 710 may, for example, execute step S310 described in FIG. 3 , which will not be repeated here.

The predicting unit 720 is configured to predict, according to the historical virtual address, the predicted virtual address where the second storage information requested to be read by the processor core at a future moment is located. The second determination unit 720 may, for example, execute the step S320 described in FIG. 3 , which will not be repeated here.

The judging unit 730 is configured to judge whether the predicted virtual address and the historical virtual address are in the same virtual address page. The judging unit 730 may, for example, execute step S330 described in FIG. 3 .

The address determining unit 740 is configured to determine the first predicted physical address according to the historical virtual address, the historical physical address and the predicted virtual address in response to the predicted virtual address being in the same virtual address page as the historical virtual address. The first predicted physical address corresponds to the predicted virtual address. The address determining unit 740 may, for example, execute step S340 described in FIG. 3 , which will not be repeated here.

For example, the acquiring unit 710, the predicting unit 720, the judging unit 730, and the address determining unit 740 may be hardware, software, firmware or any feasible combination thereof. For example, the acquiring unit 710, the predicting unit 720, the judging unit 730, and the address determining unit 740 may be dedicated or general-purpose circuits, chips or devices, or a combination of processors and memories. Regarding the specific implementation form of each of the foregoing units, the embodiment of the present disclosure does not limit it.

It should be noted that, in the embodiments of the present disclosure, each unit of the information processing device 700 corresponds to each step of the aforementioned information processing method, and for the specific functions of the information processing device 700, reference may be made to the relevant description of the information processing method, here No longer. The components and structures of the information processing apparatus 700 shown in FIG. 7 are only exemplary, not limiting, and the information processing apparatus 700 may further include other components and structures as required.

At least one embodiment of the present disclosure further provides an electronic device, where the electronic device includes a processor, and the processor is configured to implement the above information processing method. The electronic device can at least partially avoid the time delay caused by address translation, thereby improving the effectiveness of prefetching. In addition, since normal instruction and data reading often need to share the address translation pipeline with prefetching, this information processing method not only reduces the address translation of prefetching, but also reduces the address reading delay of normal reading, and reduces the prefetch Get the power consumption required for address translation.

Fig. 8 is a schematic block diagram of an electronic device provided by some embodiments of the present disclosure. As shown in FIG. 8 , the electronic device 800 includes a processor 810 . When running, the processor 810 may execute one or more steps in the information processing method described above.

For example, processor 810 may be a central processing unit (CPU) or other form of processing unit having data processing capabilities and/or program execution capabilities. For example, the central processing unit (CPU) may be of X86 or ARM architecture or the like. The processor 810 may be a general-purpose processor or a special-purpose processor, and may control other components in the electronic device 800 to perform desired functions.

It should be noted that, in the embodiment of the present disclosure, for the specific functions and technical effects of the electronic device 800, reference may be made to the above description about the information processing method, which will not be repeated here.

Fig. 9 is a schematic block diagram of another electronic device provided by some embodiments of the present disclosure. The electronic device 900 is, for example, suitable for implementing the information processing method provided by the embodiment of the present disclosure. The electronic device 900 may be a terminal device or the like. It should be noted that the electronic device 900 shown in FIG. 9 is only an example, which does not impose any limitation on the functions and application scope of the embodiments of the present disclosure.

As shown in FIG. 9 , an electronic device 900 may include a processing device (such as a central processing unit) 910, which may be loaded into a random access memory (RAM) 930 according to a program stored in a read-only memory (ROM) 920 or loaded from a storage device 980. Various appropriate actions and processing are performed by the programs in the program. In the RAM 930, various programs and data necessary for the operation of the electronic device 900 are also stored. The processing device 910, the ROM 920, and the RAM 930 are connected to each other through a bus 940. An input/output (I/O) interface 950 is also connected to bus 940 .

In general, the following devices can be connected to the I/O interface 950: input devices 960 including, for example, a touch screen, touchpad, keyboard, mouse, camera, microphone, accelerometer, gyroscope, etc.; including, for example, a liquid crystal display (LCD), speakers, vibration an output device 970 such as a computer; a storage device 980 including, for example, a magnetic tape, a hard disk, etc.; and a communication device 990 . The communication means 990 may allow the electronic device 900 to perform wireless or wired communication with other electronic devices to exchange data. Although FIG. 9 shows electronic device 900 having various means, it should be understood that it is not required to implement or have all of the means shown, and electronic device 900 may alternatively implement or have more or fewer means.

For example, according to the embodiments of the present disclosure, the processing device 910 may execute the above information processing method, and may realize the functions defined in the information processing methods provided in the embodiments of the present disclosure.

The following points need to be explained:

(1) Embodiments of the present disclosure The drawings only relate to the structures involved in the embodiments of the present disclosure, and other structures may refer to common designs.

(2) In the case of no conflict, the embodiments of the present disclosure and the features in the embodiments can be combined with each other to obtain new embodiments.

The above description is only a specific implementation manner of the present disclosure, but the protection scope of the present disclosure is not limited thereto, and the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims (16)

1. An information processing method, comprising:

obtaining read information of a history read request, wherein the history read request is sent by a processor core of a processor, the history read request indicates that the processor core requests to read first storage information at a history moment, the read information comprises a history virtual address and a history physical address of the first storage information, and the history physical address corresponds to the history virtual address;

predicting a predicted virtual address where the second storage information which is requested to be read by the processor core at a future moment is located according to the historical virtual address;

Judging whether the predicted virtual address and the historical virtual address are in the same virtual address page or not;

and determining a first predicted physical address according to the historical virtual address, the historical physical address and the predicted virtual address in response to the predicted virtual address and the historical virtual address being in the same virtual address page, wherein the first predicted physical address corresponds to the predicted virtual address.

2. The method of claim 1, wherein determining the first predicted physical address from the historical virtual address, the historical physical address, and the predicted virtual address in response to the predicted virtual address being in the same virtual address page as the historical virtual address comprises:

and in response to the predicted virtual address and the historical virtual address being in the same virtual address page, taking a sum of an offset between the predicted virtual address and the historical physical address as the first predicted physical address.

3. The method of claim 1, wherein the processor comprises a multi-level cache including at least a first level cache and a second level cache, the first level cache being one of the multi-level caches that is in direct communication with the processor core and in direct communication with the processor core, the second level cache being one of the multi-level cache that is in direct communication with the first level cache and in communication with the processor core through the first level cache,

The method further comprises the steps of:

determining a target cache of the second storage information, wherein the target cache comprises the first-level cache or the second-level cache;

the determining whether the predicted virtual address and the historical virtual address are in the same virtual address page includes:

and in response to the target cache being the second-level cache, judging whether the predicted virtual address and the historical virtual address are in the same virtual address page.

4. The method of claim 3, wherein the processor further comprises a prefetcher, the method further comprising:

the prefetcher generates a first prefetch request according to the first predicted physical address, wherein the first prefetch request is used for requesting to store second storage information stored in the first predicted physical address to the second-level cache;

the prefetcher sends the first prefetch request to the second-level cache; and

and responding to the first prefetch request by the second-level cache, and caching the second storage information corresponding to the first predicted physical address to the second-level cache.

5. The method of claim 4, wherein the second level cache buffering the second stored information corresponding to the first predicted physical address to the second level cache in response to the first prefetch request comprises:

The second-level cache responds to the first prefetch request, and whether second storage information corresponding to the first predicted physical address is cached in the second-level cache is determined;

discarding the first prefetch request in response to the second level cache having cached second storage information corresponding to the first predicted physical address; and

and responding to that the second-level cache does not cache the second storage information corresponding to the first predicted physical address, extracting the second storage information corresponding to the first predicted physical address from the next-level cache or a memory by the second-level cache, and storing the second storage information in the second-level cache.

6. The method of claim 4, wherein the prefetcher sending the first prefetch request to the second level cache comprises:

the prefetcher sending the first prefetch request to a prefetch queue to store the first prefetch request through the prefetch queue; and

in response to the second-level cache having free space, the prefetch queue sends the first prefetch request to the second-level cache.

7. The method of claim 6, wherein the prefetcher sending the first prefetch request to the second level cache further comprises:

Discarding the first prefetch request or replacing other prefetch requests in the prefetch queue with the first prefetch request in response to the memory space of the prefetch queue being full.

8. The method of claim 7, wherein the processor further comprises an address translation pipeline, the method further comprising:

and in response to the predicted virtual address not being in the same virtual address page as the historical virtual address, obtaining a second predicted physical address by address translating the predicted virtual address through the address translation pipeline.

9. The method of claim 8, further comprising:

the address translation pipeline generates a second prefetch request according to the second predicted physical address and sends the second prefetch request to the prefetch queue;

the prefetch queue responds to the second prefetch request and sends the second prefetch request to the second-level cache;

the second-level cache responds to the second prefetch request, and whether second storage information corresponding to the second predicted physical address is cached in the second-level cache or not is determined;

discarding the second prefetch request in response to the second storage information corresponding to the second predicted physical address having been cached in the second-level cache;

And responding to the second storage information corresponding to the second predicted physical address which is not cached in the second-level cache, extracting the second storage information corresponding to the second predicted physical address from the next-level cache or a memory by the second-level cache, and storing the second storage information in the second-level cache.

10. The method of claim 8, wherein, in a case where the predicted virtual address is plural and the plural predicted virtual addresses are within the same virtual address page, obtaining the second predicted physical address by address translating the predicted virtual address by the address translation pipeline in response to the predicted virtual address not being within the same virtual address page as the historical virtual address comprises:

obtaining the second predicted physical address by address translating, by the address translation pipeline, the selected one of the plurality of predicted virtual addresses in response to none of the plurality of predicted virtual addresses being in the same virtual address page as the historical virtual address; and

and determining second predicted physical addresses corresponding to other predicted virtual addresses except the selected predicted virtual address in the plurality of predicted virtual addresses according to the second predicted physical addresses corresponding to the selected predicted virtual address.

11. The method of claim 10, wherein the selected predicted virtual address is a predicted virtual address of the plurality of predicted virtual addresses predicted by the prefetcher that is first accessed by the processor core.

12. The method of claim 8, wherein the prefetch queue and the address translation pipeline share a same interface of the address cache or the prefetch queue and the address translation pipeline occupy different interfaces in the address cache, respectively.

13. The method of claim 8, further comprising:

in response to the target cache being the first level cache, sending a third prefetch request to the address translation pipeline such that the third prefetch request arrives at the address translation pipeline, wherein the third prefetch request includes the predicted virtual address;

the address translation pipeline translates the predicted virtual address to a third predicted physical address in response to the third prefetch request and generates a fourth prefetch request based on the third predicted physical address;

determining whether second storage information corresponding to the third predicted physical address is cached in the first-level cache;

Discarding the fourth prefetch request in response to the second storage information corresponding to the third predicted physical address having been cached in the first level cache;

responding to second storage information corresponding to the third predicted physical address which is not cached in the first-level cache, and sending the fourth prefetch request to the address cache, so that the address cache sends the fourth prefetch request to the second-level cache; and

the second-level cache extracts second storage information corresponding to the third predicted physical address in response to the fourth prefetch request from the address cache, and sends the extracted second storage information to the address cache, so that the address cache sends the extracted second storage information to the first-level cache.

14. The method of any of claims 1-13, wherein determining whether the predicted virtual address and the historical virtual address are in the same virtual address page comprises:

determining the page size of a virtual address page where the historical virtual address is located; and

and judging whether the predicted virtual address and the historical virtual address are in the same virtual address page or not based on the page size of the virtual address page.

15. An information processing apparatus comprising:

an acquisition unit configured to acquire read information of a history read request, wherein the history read request is transmitted by a processor core of a processor, the history read request indicates that the processor core requests to read first stored information at a history time, the read information includes a history virtual address and a history physical address of the first stored information, the history physical address corresponds to the history virtual address;

the prediction unit is configured to predict a predicted virtual address where the second storage information which is requested to be read by the processor core at a future moment is located according to the historical virtual address;

a judging unit configured to judge whether the predicted virtual address and the history virtual address are in the same virtual address page; and

and an address determination unit configured to determine a first predicted physical address according to the historical virtual address, the historical physical address and the predicted virtual address in response to the predicted virtual address and the historical virtual address being in the same virtual address page, wherein the first predicted physical address corresponds to the predicted virtual address.

16. An electronic device comprising a processor, wherein the processor is configured to implement the information processing method of any of claims 1-14.

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