CN112310189B - Semiconductor device and method for manufacturing the same - Google Patents
Semiconductor device and method for manufacturing the same Download PDFInfo
- Publication number
- CN112310189B CN112310189B CN201910680538.4A CN201910680538A CN112310189B CN 112310189 B CN112310189 B CN 112310189B CN 201910680538 A CN201910680538 A CN 201910680538A CN 112310189 B CN112310189 B CN 112310189B
- Authority
- CN
- China
- Prior art keywords
- iii
- substrate
- compound layer
- semiconductor device
- source electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 87
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 9
- 238000000034 method Methods 0.000 title claims description 30
- 150000001875 compounds Chemical class 0.000 claims abstract description 88
- 239000000758 substrate Substances 0.000 claims abstract description 69
- 239000013078 crystal Substances 0.000 claims abstract description 23
- 239000012212 insulator Substances 0.000 claims description 6
- 239000000919 ceramic Substances 0.000 claims description 4
- 239000011521 glass Substances 0.000 claims description 4
- 239000010410 layer Substances 0.000 description 92
- 239000000463 material Substances 0.000 description 33
- 238000005229 chemical vapour deposition Methods 0.000 description 18
- 229910052751 metal Inorganic materials 0.000 description 14
- 239000002184 metal Substances 0.000 description 14
- 230000008569 process Effects 0.000 description 14
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 13
- 229910002601 GaN Inorganic materials 0.000 description 10
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 10
- 230000004888 barrier function Effects 0.000 description 10
- 239000002243 precursor Substances 0.000 description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 9
- 238000000231 atomic layer deposition Methods 0.000 description 9
- 239000004020 conductor Substances 0.000 description 9
- 229910052733 gallium Inorganic materials 0.000 description 9
- 229910052710 silicon Inorganic materials 0.000 description 9
- 239000010703 silicon Substances 0.000 description 9
- 239000002019 doping agent Substances 0.000 description 8
- 239000011162 core material Substances 0.000 description 7
- 238000002248 hydride vapour-phase epitaxy Methods 0.000 description 7
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 6
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 6
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 6
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 6
- 230000005533 two-dimensional electron gas Effects 0.000 description 6
- PIGFYZPCRLYGLF-UHFFFAOYSA-N Aluminum nitride Chemical compound [Al]#N PIGFYZPCRLYGLF-UHFFFAOYSA-N 0.000 description 5
- 239000012790 adhesive layer Substances 0.000 description 5
- 229910052782 aluminium Inorganic materials 0.000 description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 5
- 230000000052 comparative effect Effects 0.000 description 5
- 229910052738 indium Inorganic materials 0.000 description 5
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 5
- 238000001451 molecular beam epitaxy Methods 0.000 description 5
- 238000005240 physical vapour deposition Methods 0.000 description 5
- 239000000126 substance Substances 0.000 description 5
- YBRBMKDOPFTVDT-UHFFFAOYSA-N tert-butylamine Chemical compound CC(C)(C)N YBRBMKDOPFTVDT-UHFFFAOYSA-N 0.000 description 5
- RGGPNXQUMRMPRA-UHFFFAOYSA-N triethylgallium Chemical compound CC[Ga](CC)CC RGGPNXQUMRMPRA-UHFFFAOYSA-N 0.000 description 5
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 4
- 239000011651 chromium Substances 0.000 description 4
- 239000010949 copper Substances 0.000 description 4
- 239000010931 gold Substances 0.000 description 4
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 4
- QJGQUHMNIGDVPM-UHFFFAOYSA-N nitrogen group Chemical group [N] QJGQUHMNIGDVPM-UHFFFAOYSA-N 0.000 description 4
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 4
- 239000010936 titanium Substances 0.000 description 4
- XCZXGTMEAKBVPV-UHFFFAOYSA-N trimethylgallium Chemical compound C[Ga](C)C XCZXGTMEAKBVPV-UHFFFAOYSA-N 0.000 description 4
- 229910017083 AlN Inorganic materials 0.000 description 3
- -1 alGaN) Inorganic materials 0.000 description 3
- RNQKDQAVIXDKAG-UHFFFAOYSA-N aluminum gallium Chemical compound [Al].[Ga] RNQKDQAVIXDKAG-UHFFFAOYSA-N 0.000 description 3
- 238000005137 deposition process Methods 0.000 description 3
- 238000000059 patterning Methods 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 229910021529 ammonia Inorganic materials 0.000 description 2
- 239000011575 calcium Substances 0.000 description 2
- 239000000969 carrier Substances 0.000 description 2
- 229910010293 ceramic material Inorganic materials 0.000 description 2
- 229910052804 chromium Inorganic materials 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 229910052741 iridium Inorganic materials 0.000 description 2
- GKOZUEZYRPOHIO-UHFFFAOYSA-N iridium atom Chemical compound [Ir] GKOZUEZYRPOHIO-UHFFFAOYSA-N 0.000 description 2
- 239000011777 magnesium Substances 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 229910052763 palladium Inorganic materials 0.000 description 2
- HKOOXMFOFWEVGF-UHFFFAOYSA-N phenylhydrazine Chemical compound NNC1=CC=CC=C1 HKOOXMFOFWEVGF-UHFFFAOYSA-N 0.000 description 2
- 229940067157 phenylhydrazine Drugs 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 229910052697 platinum Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 238000001289 rapid thermal chemical vapour deposition Methods 0.000 description 2
- 229910052594 sapphire Inorganic materials 0.000 description 2
- 239000010980 sapphire Substances 0.000 description 2
- 229910021332 silicide Inorganic materials 0.000 description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- VOITXYVAKOUIBA-UHFFFAOYSA-N triethylaluminium Chemical compound CC[Al](CC)CC VOITXYVAKOUIBA-UHFFFAOYSA-N 0.000 description 2
- JLTRXTDYQLMHGR-UHFFFAOYSA-N trimethylaluminium Chemical compound C[Al](C)C JLTRXTDYQLMHGR-UHFFFAOYSA-N 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- RUDFQVOCFDJEEF-UHFFFAOYSA-N yttrium(III) oxide Inorganic materials [O-2].[O-2].[O-2].[Y+3].[Y+3] RUDFQVOCFDJEEF-UHFFFAOYSA-N 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OYPRJOBELJOOCE-UHFFFAOYSA-N Calcium Chemical compound [Ca] OYPRJOBELJOOCE-UHFFFAOYSA-N 0.000 description 1
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- FYYHWMGAXLPEAU-UHFFFAOYSA-N Magnesium Chemical compound [Mg] FYYHWMGAXLPEAU-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- AUCDRFABNLOFRE-UHFFFAOYSA-N alumane;indium Chemical compound [AlH3].[In] AUCDRFABNLOFRE-UHFFFAOYSA-N 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- AJGDITRVXRPLBY-UHFFFAOYSA-N aluminum indium Chemical compound [Al].[In] AJGDITRVXRPLBY-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 229910052788 barium Inorganic materials 0.000 description 1
- DSAJWYNOEDNPEQ-UHFFFAOYSA-N barium atom Chemical compound [Ba] DSAJWYNOEDNPEQ-UHFFFAOYSA-N 0.000 description 1
- 229910052790 beryllium Inorganic materials 0.000 description 1
- ATBAMAFKBVZNFJ-UHFFFAOYSA-N beryllium atom Chemical compound [Be] ATBAMAFKBVZNFJ-UHFFFAOYSA-N 0.000 description 1
- 239000011230 binding agent Substances 0.000 description 1
- 229910052797 bismuth Inorganic materials 0.000 description 1
- JCXGWMGPZLAOME-UHFFFAOYSA-N bismuth atom Chemical compound [Bi] JCXGWMGPZLAOME-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 229910052791 calcium Inorganic materials 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000002800 charge carrier Substances 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 239000002772 conduction electron Substances 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- AJNVQOSZGJRYEI-UHFFFAOYSA-N digallium;oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[Ga+3].[Ga+3] AJNVQOSZGJRYEI-UHFFFAOYSA-N 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- QZQVBEXLDFYHSR-UHFFFAOYSA-N gallium(III) oxide Inorganic materials O=[Ga]O[Ga]=O QZQVBEXLDFYHSR-UHFFFAOYSA-N 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 229910052749 magnesium Inorganic materials 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229910052705 radium Inorganic materials 0.000 description 1
- HCWPIIXVSYCSAN-UHFFFAOYSA-N radium atom Chemical compound [Ra] HCWPIIXVSYCSAN-UHFFFAOYSA-N 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 229910052712 strontium Inorganic materials 0.000 description 1
- CIOAGBVUUVVLOB-UHFFFAOYSA-N strontium atom Chemical compound [Sr] CIOAGBVUUVVLOB-UHFFFAOYSA-N 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- JBQYATWDVHIOAR-UHFFFAOYSA-N tellanylidenegermanium Chemical compound [Te]=[Ge] JBQYATWDVHIOAR-UHFFFAOYSA-N 0.000 description 1
- 239000011573 trace mineral Substances 0.000 description 1
- 235000013619 trace mineral Nutrition 0.000 description 1
- 238000000927 vapour-phase epitaxy Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
- H10D30/47—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/015—Manufacture or treatment of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions
Landscapes
- Junction Field-Effect Transistors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention provides a semiconductor device and a manufacturing method thereof, comprising a substrate and a first III-V compound layer, wherein the first III-V compound layer is arranged on the substrate. The first III-V compound layer includes a plurality of crystal lattices, and each crystal lattice has a prism face. The semiconductor device further includes a second III-V compound layer disposed on the first III-V compound layer. The semiconductor device includes a source electrode, a drain electrode, and a gate electrode disposed on the second III-V compound layer. The source electrode and the drain electrode define a channel region in the first III-V compound layer, and the channel region has a plurality of carrier channels therein. The normal direction of the prism face defines an m-axis, and each carrier channel is parallel to the m-axis. The semiconductor device can effectively reduce the on-resistance of the semiconductor device.
Description
Technical Field
The present invention relates to a semiconductor device, and more particularly, to a semiconductor device for a high electron mobility transistor (high electron mobility transistors, HEMT) device and a method of fabricating the same.
Background
In the semiconductor industry, gallium nitride (GaN) is often used to form various integrated circuit devices, such as High Electron Mobility Transistor (HEMT) devices, due to its characteristics. High electron mobility transistors, also known as heterojunction field effect transistors (heterostructure FETs, HFETs) or modulation-doped field effect transistors (MODFETs), are composed of semiconductor materials with different energy gaps (ENERGY GAP). A two-dimensional electron gas (two dimensional electron gas,2 DEG) layer is created adjacent to the formed interface of the different semiconductor materials. Due to the high electron mobility of the two-dimensional electron gas, the high electron mobility transistor can have the advantages of high breakdown voltage, high electron mobility, low input capacitance and the like, so that the transistor is suitable for being used on high-power devices.
However, while the conventional high electron mobility transistors generally meet the requirements, they are not satisfactory in every aspect, and further improvements are needed to enhance performance and have wider applications.
Disclosure of Invention
Embodiments of the present invention include a semiconductor device. The semiconductor device comprises a substrate and a first III-V compound layer, wherein the first III-V compound layer is arranged on the substrate. The first III-V compound layer includes a plurality of crystal lattices, and each crystal lattice has a prism face. The semiconductor device further includes a second III-V compound layer disposed on the first III-V compound layer. The semiconductor device includes a source electrode, a drain electrode, and a gate electrode disposed on the second III-V compound layer. The source electrode and the drain electrode define a channel region in the first III-V compound layer, and the channel region has a plurality of carrier channels therein. The normal direction of the prism face defines an m-axis, and each carrier channel is parallel to the m-axis.
Embodiments of the present invention include a semiconductor device. The semiconductor device comprises a substrate and a first III-V compound layer, wherein the first III-V compound layer is arranged on the substrate. The first III-V compound layer includes a plurality of crystal lattices and each crystal lattice has an m-plane. The semiconductor device further includes a second III-V compound layer disposed on the first III-V compound layer. The semiconductor device includes a source electrode, a drain electrode, and a gate electrode disposed on the second III-V compound layer. The source electrode and the drain electrode define a channel region in the first III-V compound layer, and the channel region has a plurality of carrier channels therein. Each carrier channel is parallel to the normal direction of the m-plane.
Embodiments of the present invention include a method of manufacturing a semiconductor device. The manufacturing method includes forming and providing a substrate. The method also includes forming a first III-V compound layer on the substrate. The first III-V compound layer includes a plurality of crystal lattices, and each crystal lattice has a prism face. The manufacturing method includes forming a second III-V compound layer on the first III-V compound layer. The method further includes forming a source electrode, a drain electrode, and a gate electrode on the second III-V compound layer. The source electrode and the drain electrode define a channel region in the first III-V compound layer, and the channel region has a plurality of carrier channels therein. The normal direction of the prism face defines an m-axis, and each carrier channel is parallel to the m-axis.
The semiconductor device of the present invention can effectively reduce the on-resistance of the semiconductor device by making each carrier channel in the channel region of the semiconductor device parallel to the m-axis.
Drawings
Embodiments of the present invention will be described in detail below with reference to the attached drawings. It should be noted that the various features are not drawn to scale and are merely illustrative. In fact, the dimensions of the device may be exaggerated or reduced to clearly illustrate the technical features of the embodiments of the present invention.
Fig. 1-4 are partial cross-sectional views illustrating various stages of a process for forming the semiconductor device of fig. 4, in accordance with some embodiments of the present invention.
FIG. 5A is a schematic top view of a portion of a substrate and a first III-V compound layer.
Fig. 5B shows an enlarged schematic top view of a single lattice.
Fig. 6 shows a schematic perspective view of a single lattice.
Fig. 7 is a schematic top view of a portion of a semiconductor device according to an embodiment of the invention.
Reference numerals:
1-semiconductor device
10-Substrate
20-A first III-V compound layer
21-Lattice
21 A-a plane
21 M-m plane
30-A second III-V compound layer
30T-top surface
41-Source electrode
41S-side edge
43-Drain electrode
43S-side edge
45-Gate electrode
47-Channel region
A-a' to section line
A-a axis
M-m axis
Detailed Description
The following summary provides many different embodiments, or examples, for implementing different features of the disclosure. The following summary describes specific examples of various components and arrangements thereof to simplify the description. Of course, these specific examples are not intended to be limiting. For example, if embodiments of the present invention describe a first feature formed on or over a second feature, embodiments that may include the first feature being in direct contact with the second feature, embodiments that may include additional features formed between the first feature and the second feature, such that the first feature and the second feature may not be in direct contact.
It is to be understood that additional operational steps may be performed before, during, or after the methods, and that in other embodiments of the methods, some of the operational steps may be replaced or omitted.
Further, spatially relative terms, such as "below," "lower," "above," "upper," "higher," and the like, may be used herein to facilitate a description of a relationship between one device(s) or feature(s) and another device(s) or feature(s) in the drawings, including different orientations of the device in use or operation, and orientations depicted in the drawings. When the device is turned to a different orientation (rotated 90 degrees or other orientations), the spatially relative descriptors used herein interpreted in terms of the turned orientation.
In the specification, the terms "about", "approximately" and "approximately" generally mean within 20%, or within 10%, or within 5%, or within 3%, or within 2%, or within 1%, or within 0.5% of a given value or range. Where a given quantity is about, i.e., where "about", and "approximately" are not specifically recited, the meaning of "about", and "approximately" may be implied.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be appreciated that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present invention and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
The different embodiments of the invention below may repeat use of the same reference numerals and/or indicia. These repetition are for the purpose of simplicity and clarity and do not in itself dictate a particular relationship between the various embodiments and/or configurations discussed.
The on-resistance (R on) is an important factor affecting the power consumption of the semiconductor device, and its resistance value is proportional to the power consumption of the semiconductor device. The embodiment of the invention provides a semiconductor device and a manufacturing method thereof, which are particularly suitable for a High Electron Mobility Transistor (HEMT) device. In the semiconductor device according to the embodiment of the invention, the on-resistance of the semiconductor device can be effectively reduced by arranging the carrier (CHARGE CARRIER) channel (or the source electrode and the drain electrode) of the semiconductor device in a specific direction with respect to the lattice of the III-V compound layer (for example, gallium nitride (GaN)). The following description will be made with reference to the embodiments shown in the drawings.
Fig. 1-4 are partial cross-sectional views illustrating various stages of a process for forming the semiconductor device 1 shown in fig. 4, in accordance with some embodiments of the present invention. It is noted that some of the devices may be omitted from fig. 1-4 for clarity of illustration of features of embodiments of the present invention.
Referring to fig. 1, a substrate 10 is provided. In some embodiments, the substrate 10 may be a semiconductor substrate, such as a silicon substrate, a silicon germanium substrate, a gallium arsenide substrate, or similar semiconductor substrate. In some embodiments, the substrate 10 may be a semiconductor over insulator substrate, such as a silicon on insulator (silicon on insulator, SOI) substrate. In some embodiments, the substrate 10 may be a glass substrate or a ceramic substrate, such as a silicon carbide (SiC) substrate, an aluminum nitride (aluminium nitride AlN) substrate, or a Sapphire (Sapphire) substrate. However, the embodiments of the present invention are not limited thereto.
In some embodiments, the substrate 10 is a QST substrate. Herein, the QST substrate refers to a substrate manufactured in U.S. Qromis Technology, inc. For example, the QST substrate may include a core, a barrier layer, a bonding layer, and a monocrystalline layer SINGLE CRYSTALLINE LAYER. In some embodiments, the barrier layer may encapsulate the core, the bonding layer may be disposed over the barrier layer, and the monocrystalline layer may be disposed over the bonding layer, although embodiments of the invention are not limited thereto.
In some embodiments, the core material may include polycrystalline ceramic material, such as polycrystalline aluminum nitride (aluminium nitride, alN), polycrystalline gallium nitride (GaN), polycrystalline gallium aluminum nitride (aluminium gallium nitride, alGaN), polycrystalline silicon carbide (SiC), polycrystalline zinc oxide (ZnO), polycrystalline gallium trioxide (gallium (III) trioxide, ga 2O3), other suitable materials, or combinations thereof, but the embodiments are not limited thereto. In some embodiments, the polycrystalline ceramic material may include a binder material such as yttria (i.e., ytria).
In some embodiments, the material of the barrier layer may be an amorphous material, such as silicon nitride, silicon carbonitride (silicon carbonitride, siCN), silicon oxynitride (silicon oxynitride, siON), aluminum nitride (AlN), silicon carbide (SiC), other suitable materials, or combinations thereof, but the embodiments of the present invention are not limited thereto. In some embodiments, the barrier layer may be formed by a Low Pressure Chemical Vapor Deposition (LPCVD) process, but the invention is not limited thereto. In some embodiments, the barrier layer may be one or more layers comprising one or more materials laminated in a composite manner, but embodiments of the invention are not limited thereto.
In some embodiments, the barrier layer may be used to prevent diffusion and/or release of constituents in the core (e.g., yttria, oxygen, metal impurities, other trace elements, etc.) into the environment of the semiconductor processing chamber. In a semiconductor processing chamber, a QST substrate may be epitaxially grown, for example, at a high temperature (e.g., 1,000 ℃).
In some embodiments, the material of the bonding layer may include silicon oxide, silicon nitride, silicon oxynitride, other suitable materials, or a combination of the foregoing. In some embodiments, the bonding layer may be formed on (part of) the top surface of the barrier layer by Chemical Vapor Deposition (CVD), atomic layer deposition (atomic layer deposition, ALD), or spin-on coating. For example, the chemical vapor deposition method may be Low Pressure Chemical Vapor Deposition (LPCVD), low temperature chemical vapor deposition (low temperature chemical vapor deposition, LTCVD), rapid Thermal Chemical Vapor Deposition (RTCVD), or ion-enhanced chemical vapor deposition (PLASMA ENHANCED CHEMICAL vapor deposition, PECVD).
In some embodiments, the material of the monocrystalline layer may include silicon (Si), aluminum nitride (AlN), gallium nitride (GaN), aluminum gallium nitride (AlGaN), silicon carbide (SiC), other suitable materials, or combinations thereof, but the embodiment of the invention is not limited thereto. The monocrystalline layer may be a single-layer or multi-layer structure. In some embodiments, the single crystal layer may be formed by an epitaxial growth process, such as metal organic chemical vapor deposition (metal organic chemical vapor deposition, MOCVD), hydride vapor phase epitaxy (hydride vapor phase epitaxy, HVPE), molecular beam epitaxy (molecular beam epitaxy, MBE), other suitable methods, or combinations thereof, but the embodiments are not limited thereto.
In some embodiments, the substrate 10 may further include a plurality of adhesion layers (adhesion layers) and a conductive layer. The adhesive layer and the conductive layer may be disposed between the core and the barrier layer. For example, the adhesive layer may be disposed between the core and the conductive layer, and the adhesive layer may be disposed between the conductive layer and the barrier layer, but the embodiment of the invention is not limited thereto.
In some embodiments, the material of the adhesive layer may include tetraethyl orthosilicate (TETRAETHYL ORTHOSILIATE, TEOS), silicon oxide (Si xOy), other suitable materials, or combinations thereof, but the embodiment of the invention is not limited thereto. In some embodiments, the adhesive layer may be formed around the core by Chemical Vapor Deposition (CVD), atomic Layer Deposition (ALD), or spin-on coating.
In some embodiments, the conductive layer may comprise a doped (e.g., boron doped) highly conductive material. In some embodiments, the doping concentration may be between 1x10 19cm-3 and 1x10 20cm-3 to provide high conductivity. Other dopants of different doping concentrations (e.g., phosphorus, arsenic, bismuth, etc. having doping concentrations between 1x10 16cm-3 and 5x10 18cm-3) may also be used to provide N-type or P-type semiconductor materials suitable for use in the conductive layer, but the present embodiments are not limited thereto.
For a detailed structure of the QST substrate, reference is made to U.S. patent application No. 15/621,335 filed on 13 th 6 th 2017 and U.S. patent application No. 15/621,335 filed on 13 th 6 th 2017, which are not repeated here. However, the embodiment of the invention is not limited thereto.
Referring to fig. 2, a first III-V compound layer 20 is formed on a substrate 10. In some embodiments, the material of the first III-V compound layer 20 may include one or more III-V compound semiconductor materials, such as a III-nitride. In some embodiments, the material of the first III-V compound layer 20 may include gallium nitride (GaN), aluminum gallium nitride (AlGaN), indium gallium nitride (indium gallium nitride, inGaN), indium gallium aluminum nitride (indium gallium aluminium nitride, inGaAlN), similar materials, or combinations of the foregoing. In some embodiments, the thickness of the first III-V compound layer 20 may be between 0.01 μm and 10 μm. In some embodiments, the first III-V compound layer 20 may have dopants, such as n-type dopants or p-type dopants. The first III-V compound layer 20 may be formed by an epitaxial growth process, such as Metal Organic Chemical Vapor Deposition (MOCVD), hydride Vapor Phase Epitaxy (HVPE), molecular Beam Epitaxy (MBE), other suitable methods, or a combination thereof. For example, the first III-V compound layer 20 may be epitaxially grown by Metal Organic Chemical Vapor Deposition (MOCVD) using a gallium-containing precursor and a nitrogen-containing precursor. The gallium-containing precursor may include Trimethylgallium (TMG), triethylgallium (triethylgallium, TEG), or other suitable chemicals, and the nitrogen-containing precursor may include ammonia (NH 3), tert-butylamine (tertiarybutylamine, TBAm), phenylhydrazine, or other suitable chemicals. However, the embodiment of the invention is not limited thereto.
Referring to fig. 3, a second III-V compound layer 30 is formed on the first III-V compound layer 20. In some embodiments, the material of the second III-V compound layer 30 may include one or more III-V compound semiconductors, such as group III nitrides. In some embodiments, the material of the second III-V compound layer 30 may include aluminum gallium nitride (AlGaN), aluminum indium nitride (aluminium indium nitride, alInN), indium gallium aluminum nitride (InGaAlN), similar materials, or combinations of the foregoing. In some embodiments, the thickness of the second III-V compound layer 30 may be between 1nm and 500 nm. In some embodiments, the second III-V compound layer 30 may have dopants, such as n-type dopants or p-type dopants. The second III-V compound layer 30 may be formed by an epitaxial growth process, such as Metal Organic Chemical Vapor Deposition (MOCVD), hydride Vapor Phase Epitaxy (HVPE), molecular Beam Epitaxy (MBE), other suitable methods, or a combination of the foregoing. For example, the second III-V compound layer 30 may be epitaxially grown by metal organic vapor phase epitaxy (MOCVD) using aluminum-containing precursors, gallium-containing precursors, and nitrogen-containing precursors. The aluminum-containing precursor comprises trimethylaluminum (trimethylaluminum, TMA), triethylaluminum (triethylaluminum, TEA), or other suitable chemical, the gallium-containing precursor comprises Trimethylgallium (TMG), triethylgallium (TEG), or other suitable chemical, and the nitrogen-containing precursor comprises ammonia (NH 3), tert-butylamine (TBAm), phenylhydrazine, or other suitable chemical. However, the embodiment of the invention is not limited thereto.
Referring to fig. 4, a source electrode 41, a drain electrode 43 and a gate electrode 45 are formed on the second III-V compound layer 30 to form the semiconductor device 1. In the embodiment of the present invention, the source electrode 41, the drain electrode 43 and the gate electrode 45 may be arranged in a specific manner, which will be described in detail later with reference to the drawings.
In some embodiments, the material of the source electrode 41 may comprise a conductive material, such as a metal, a metal silicide, a semiconductor material, other suitable materials, or a combination of the foregoing materials. The metal may be gold (Au), nickel (Ni), platinum (Pt), palladium (Pd), iridium (Ir), titanium (Ti), chromium (Cr), tungsten (W), aluminum (Al), copper (Cu), combinations of the foregoing, alloys of the foregoing, or multilayers of the foregoing. The semiconductor material may be polysilicon or poly-germanium. However, the embodiment of the invention is not limited thereto. In some embodiments, the material of the drain electrode 43 may be the same as or similar to that of the source electrode 41, and will not be described in detail herein.
The step of forming the source electrode 41 and the drain electrode 43 may include depositing a conductive material over the second III-V compound layer 30, and performing a patterning process on the conductive material to form the source electrode 41 and the drain electrode 43 on the top surface 30T of the second III-V compound layer 30. Deposition processes for forming the conductive material may include Atomic Layer Deposition (ALD), chemical Vapor Deposition (CVD), physical vapor deposition (physical vapor deposition, PVD) (e.g., sputtering), other suitable processes, or combinations of the foregoing. Special attention is paid to this. Although fig. 4 shows the source electrode 41 and the drain electrode 43 formed on the top surface 30T of the second III-V compound layer 30, the embodiment of the invention is not limited thereto. In some embodiments, a portion of the source electrode 41 and a portion of the drain electrode 43 may also be formed in the second III-V compound layer 30, or may be connected to the first III-V compound layer 20, which may be adjusted according to practical requirements.
In some embodiments, the material of gate electrode 45 may comprise a conductive material, such as a metal, a metal silicide, a semiconductor material, other suitable materials, or a combination of the foregoing. The metal may be gold (Au), nickel (Ni), platinum (Pt), palladium (Pd), iridium (Ir), titanium (Ti), chromium (Cr), tungsten (W), aluminum (Al), copper (Cu), combinations of the foregoing, alloys of the foregoing, or multilayers of the foregoing. The semiconductor material may be polysilicon or poly-germanium. However, the embodiment of the invention is not limited thereto.
The step of forming the gate electrode 45 may include depositing a conductive material over the second III-V compound layer 30 and performing a patterning process on the conductive material to form the gate electrode 45 over the top surface 30T of the second III-V compound layer 30. Deposition processes for forming the conductive material may include Atomic Layer Deposition (ALD), chemical Vapor Deposition (CVD), physical Vapor Deposition (PVD) (e.g., sputtering), other suitable processes, or combinations of the foregoing.
In some embodiments, the semiconductor device 1 may further include a doped compound semiconductor layer (not shown), which may be formed between the second III-V compound layer 30 and the gate electrode 45. In some embodiments, the doped compound semiconductor layer may include a p-type doped III-V compound, such as p-type doped gallium nitride. The p-doped gallium nitride may Be doped with at least one of magnesium (Mg), calcium (Ca), zinc (Zn), beryllium (Be), and carbon (C), and may Be doped with other dopants (e.g., selected from the group consisting of strontium (Sr), barium (Ba), and radium (Ra)), but the embodiment of the invention is not limited thereto. In some embodiments, the doped compound semiconductor layer may be formed by Metal Organic Chemical Vapor Deposition (MOCVD) or other suitable deposition processes, photolithographic patterning processes, and etching processes. In some embodiments, the thickness of the doped compound semiconductor layer may be between about 1nm and about 100nm, but the embodiment of the invention is not limited thereto.
Referring to fig. 4, the energy band difference (band gap discontinuity) and the piezoelectric effect (piezo-ELECTRIC EFFECT) between the first and second III-V compound layers 20 and 30 generate a carrier channel having high mobile conduction electrons near the interface between the first and second III-V compound layers 20 and 30, referred to as two-dimensional electron gas (two-dimensional electron gas, 2-DEG), as shown by the dotted line of fig. 4. The semiconductor device 1 shown in fig. 4 may be a high electron mobility transistor (high electron mobility transistors, HEMT) that uses two-dimensional electron gas (2 DEG) as a conductive carrier.
Fig. 5A shows a schematic top view of a portion of the substrate 10 and the first III-V compound layer 20. In fig. 5A, the first group III-V compound layer 20 is presented in an arrangement of a plurality of crystal lattices 21, but the size of each crystal lattice 21 shown in fig. 5A is merely illustrative, and the actual size of the crystal lattice 21 with respect to the substrate 10 is not as shown in fig. 5A. In the embodiment shown in fig. 5A, the material of the first III-V compound layer 20 is gallium nitride (GaN), and the lattice 21 of gallium nitride belongs to a hexagonal system (hexagonal CRYSTAL SYSTEM). Fig. 5B shows an enlarged schematic top view of the single lattice 21. Fig. 6 shows a schematic perspective view of a single crystal lattice 21. Fig. 7 is a schematic top view of a portion of a semiconductor device 1 according to an embodiment of the invention.
It is noted that some of the devices may be omitted from fig. 5A-7 for clarity of illustration of features of embodiments of the present invention. For example, fig. 7 only shows the source electrode 41, the drain electrode 43, the gate electrode 45, and the channel region 47 defined by the source electrode 41 and the drain electrode 43 of the semiconductor device 1. In addition, fig. 4 may be, for example, a cross-sectional view taken along line A-A' in fig. 7, but the embodiment of the invention is not limited thereto.
Referring to fig. 5A, 5B and 6, the crystal lattice 21 has a prism face (PRISM PLANE). In the present invention, the prism surface refers to a rectangular plane of the hexagonal column side of the lattice 21 of the hexagonal system, i.e., an m-plane 21m of the lattice 21, which is understood by those skilled in the art to which the present invention pertains. The prism face (m-plane 21 m) belongs to the plane family {1-100}, for example, the prism face may be represented as a plane (10-10), but the embodiment of the invention is not limited thereto. In other embodiments, the prism face may also be represented as a plane (-1010), a plane (1-100), a plane (-1100), a plane (01-10), or a plane (0-110).
As shown in fig. 5A and 5B, the normal direction of the prism face may define an m-axis (i.e., reference m in fig. 5A and 5B). For example, when the prism face is planar (10-10), the m-axis is [10-10], when the prism face is planar (-1010), the m-axis is [ -1010], when the prism face is planar (1-100), the m-axis is [1-100], when the prism face is planar (-1100), the m-axis is [ -1100], when the prism face is planar (01-10), the m-axis is [01-10], when the prism face is planar (0-110), the m-axis is [0-110].
Referring to fig. 5A and 7 together, the source electrode 41 and the drain electrode 43 may define a channel region 47 in the first III-V compound layer 20, and the channel region 47 may have a plurality of carrier channels therein. In an embodiment of the invention, each carrier channel is parallel to the m-axis. In other words, in embodiments of the present invention, each carrier channel is parallel to the normal direction of the m-plane of the lattice.
In some embodiments, the extending directions of the source electrode 41 and the drain electrode 43 may be perpendicular to the m-axis (normal direction perpendicular to the m-plane), i.e., the source electrode 41 and the drain electrode 43 extend along the a-axis (reference numeral a) direction shown in fig. 5A and 7. In some embodiments, the source electrode 41 and the drain electrode 43 are separated from each other along the direction of the m-axis (the normal direction of the m-plane). In more detail, as shown in fig. 7, in some embodiments, the source electrode 41 and the drain electrode 43 are disposed opposite to and in parallel with each other, a side wall of the source electrode 41 facing the drain electrode 43 is projected as a side 41S on the substrate 10, the side 41S being perpendicular to the m-axis (perpendicular to the normal direction of the m-plane), or a side wall of the drain electrode 43 facing the source electrode 41 is projected as a side 43S on the substrate 10, the side 43S being perpendicular to the m-axis (perpendicular to the normal direction of the m-plane).
In the embodiment of the present invention, carriers (electrons or holes) moving in the channel region 47 defined by the source electrode 41 and the drain electrode 43 may have a higher carrier mobility than the conventional semiconductor device, which may have a favorable effect on the on-resistance (R on) of the semiconductor device 1.
However, it should be noted that the arrangement of the source electrode 41, the drain electrode 43, and the gate electrode 45 in the present invention is not limited to the arrangement shown in fig. 7. As long as each carrier channel in the channel region 47 is parallel to the m-axis, carriers moving in the channel region 47 defined by the source electrode 41 and the drain electrode 43 can be made to have a higher carrier mobility.
Table one shows the performance (performance) comparison results of the semiconductor device 1 according to the embodiment of the present invention and the semiconductor device according to the comparative example. The structure of the semiconductor device 1 of the embodiment of the present invention may refer to fig. 4 to 7, and each carrier channel in the channel region 47 of the semiconductor device 1 of the embodiment of the present invention is parallel to the m-axis (e.g., [10-10 ]). The semiconductor device of the comparative example has a similar structure to the semiconductor device 1 of the embodiment of the present invention, except that each carrier channel in the channel region of the semiconductor device of the comparative example is parallel to the a-axis (i.e., the normal direction of the a-plane 21a of the crystal lattice 21, for example, [11-20 ]) (refer to fig. 5A, 5B).
List one
| Performance of | Examples | Comparative example |
| Ron(mΩ) | 20.5 | 115 |
| Area (mm 2) | 10.38 | 5.18 |
| Ron,sp(mΩ) | 2.13 | 5.96 |
In table one, R on is the on-resistance and R on,sp is the characteristic on-resistance. The characteristic on-resistance R on,sp is defined as the on-resistance distributed per square unit. As shown in table one, the characteristic on-resistance R on,sp of the semiconductor device 1 of the example was reduced by 64% as compared with the characteristic on-resistance R on,sp of the semiconductor device 1 of the comparative example. That is, by disposing each carrier channel in the channel region 47 of the semiconductor device 1 in a specific direction with respect to the crystal lattice 21 of the first III-V compound layer 20 (GaN), the on-resistance of the semiconductor device 1 can be effectively reduced.
In summary, in the semiconductor device according to the embodiment of the present invention, the on-resistance of the semiconductor device can be effectively reduced by making each carrier channel in the channel region of the semiconductor device parallel to the m-axis (i.e., the normal direction of the prism face of the lattice forming the first III-V compound layer).
The foregoing has outlined features of the many embodiments so that those skilled in the art may better understand the embodiments of the invention from all the aspects. Those skilled in the art will appreciate that other processes and structures can be readily utilized as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments presented herein. Those skilled in the art will also realize that such equivalent constructions do not depart from the spirit and scope of the embodiments of the invention. Various changes, substitutions, or alterations can be made to the embodiments of the invention without departing from the spirit and scope of the embodiments of the invention, and therefore, the scope of the invention is defined by the appended claims. In addition, while the invention has been described above in terms of several preferred embodiments, it is not intended to limit the invention, and not all advantages have been described in detail herein.
Each of the claims may be presented in terms of a separate embodiment, and the scope of the invention includes every claim and every embodiment of the invention in combination with one another.
Claims (18)
1. A semiconductor device, comprising:
A substrate;
a first III-V compound layer disposed on the substrate, the first III-V compound layer including a plurality of crystal lattices, each crystal lattice having a prism face;
A second III-V compound layer disposed on the first III-V compound layer, and
A source electrode, a drain electrode and a gate electrode disposed on the second III-V compound layer, the source electrode and the drain electrode defining a channel region in the first III-V compound layer, the channel region having a plurality of carrier channels therein;
Wherein the normal direction of the prism face defines an m-axis, and each carrier channel extends along a single direction parallel to the m-axis.
2. The semiconductor device of claim 1, wherein the substrate is a semiconductor substrate, a semiconductor-on-insulator substrate, a glass substrate, or a ceramic substrate.
3. The semiconductor device of claim 1, wherein the substrate is a QST substrate.
4. The semiconductor device according to claim 1, wherein the m-axis is one of [10-10], [ -1010], [1-100], [ -1100], [01-10], and [0-110 ].
5. The semiconductor device of claim 1, wherein the source electrode and the drain electrode are opposite to each other, and a projection of a sidewall of the source electrode facing the drain electrode on the substrate is perpendicular to the m-axis.
6. The semiconductor device of claim 1, wherein the source electrode and the drain electrode are separated from each other along the direction of the m-axis.
7. A semiconductor device, comprising:
A substrate;
A first III-V compound layer disposed on the substrate, the first III-V compound layer including a plurality of crystal lattices, each crystal lattice having an m-plane;
A second III-V compound layer disposed on the first III-V compound layer, and
A source electrode, a drain electrode and a gate electrode disposed on the second III-V compound layer, the source electrode and the drain electrode defining a channel region in the first III-V compound layer, the channel region having a plurality of carrier channels therein;
Wherein each carrier channel extends in a single direction parallel to the normal direction of the m-plane.
8. The semiconductor device of claim 7, wherein the substrate is a semiconductor substrate, a semiconductor-on-insulator substrate, a glass substrate, or a ceramic substrate.
9. The semiconductor device of claim 7, wherein the substrate is a QST substrate.
10. The semiconductor device according to claim 7, wherein the m-plane is one of a plane (10-10), a plane (-1010), a plane (1-100), a plane (-1100), a plane (01-10), and a plane (0-110).
11. The semiconductor device according to claim 7, wherein the source electrode and the drain electrode are opposite to each other, and a projection of a sidewall of the source electrode facing the drain electrode on the substrate is perpendicular to a normal direction of the m-plane.
12. The semiconductor device according to claim 7, wherein the source electrode and the drain electrode are separated from each other along a normal direction of the m-plane.
13. A method for manufacturing a semiconductor device, comprising:
forming and providing a substrate;
forming a first III-V compound layer on the substrate, wherein the first III-V compound layer comprises a plurality of crystal lattices, and each crystal lattice has a prism surface;
Forming a second III-V compound layer on the first III-V compound layer, and
Forming a source electrode, a drain electrode and a gate electrode on the second III-V compound layer, wherein the source electrode and the drain electrode define a channel region in the first III-V compound layer, the channel region having a plurality of carrier channels therein;
Wherein the normal direction of the prism face defines an m-axis, and each carrier channel extends along a single direction parallel to the m-axis.
14. The method of claim 13, wherein the substrate is a semiconductor substrate, a semiconductor-on-insulator substrate, a glass substrate, or a ceramic substrate.
15. The method of claim 13, wherein the substrate is a QST substrate.
16. The method of claim 13, wherein the m-axis is one of [10-10], [ -1010], [1-100], [ -1100], [01-10] and [0-110 ].
17. The method of claim 13, wherein the source electrode and the drain electrode are opposite to each other, and a projection of a sidewall of the source electrode facing the drain electrode on the substrate is perpendicular to the m-axis.
18. The method of claim 13, wherein the source electrode and the drain electrode are separated from each other along the direction of the m-axis.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910680538.4A CN112310189B (en) | 2019-07-26 | 2019-07-26 | Semiconductor device and method for manufacturing the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910680538.4A CN112310189B (en) | 2019-07-26 | 2019-07-26 | Semiconductor device and method for manufacturing the same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN112310189A CN112310189A (en) | 2021-02-02 |
| CN112310189B true CN112310189B (en) | 2024-12-17 |
Family
ID=74329656
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910680538.4A Active CN112310189B (en) | 2019-07-26 | 2019-07-26 | Semiconductor device and method for manufacturing the same |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112310189B (en) |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4154558B2 (en) * | 2000-09-01 | 2008-09-24 | 日本電気株式会社 | Semiconductor device |
| JP5208463B2 (en) * | 2007-08-09 | 2013-06-12 | ローム株式会社 | Nitride semiconductor device and method for manufacturing nitride semiconductor device |
| JP2009218290A (en) * | 2008-03-07 | 2009-09-24 | Rohm Co Ltd | Fieldeffect transistor |
| US9129889B2 (en) * | 2013-03-15 | 2015-09-08 | Semiconductor Components Industries, Llc | High electron mobility semiconductor device and method therefor |
-
2019
- 2019-07-26 CN CN201910680538.4A patent/CN112310189B/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN112310189A (en) | 2021-02-02 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP4525894B2 (en) | Semiconductor device forming plate-like substrate, manufacturing method thereof, and semiconductor device using the same | |
| US9343542B2 (en) | Method for fabricating enhancement mode transistor | |
| JP5292716B2 (en) | Compound semiconductor device | |
| US8410525B2 (en) | Compound semiconductor substrate and device therewith | |
| US8878245B2 (en) | Transistors and method for making ohmic contact to transistors | |
| TW200414313A (en) | Semiconductor device and the manufacturing method thereof | |
| JPWO2005015642A1 (en) | Semiconductor device and manufacturing method thereof | |
| US12176430B2 (en) | Semiconductor structure and semiconductor device | |
| US20060220039A1 (en) | Semiconductor device, method of manufacturing the same, and substrate for manufacturing the same | |
| JP2005509274A (en) | III-nitride high electron mobility transistor (HEMT) with barrier / spacer layer | |
| JP2008166469A (en) | Nitride semiconductor device and manufacturing method thereof | |
| US20240030331A1 (en) | Semiconductor device and method for manufacturing the same | |
| TW201303967A (en) | Compound semiconductor device and method of manufacturing same | |
| JP2010225979A (en) | GaN-based field effect transistor | |
| JP2007158143A (en) | Heterojunction field effect transistor | |
| CN109285777A (en) | Method for forming epitaxial substrate with N-polar gallium nitride | |
| WO2012008027A1 (en) | Compound semiconductor device and process for production thereof | |
| JP7074282B2 (en) | High electron mobility transistor | |
| WO2023019436A1 (en) | Semiconductor device and method for manufacturing the same | |
| JP5509544B2 (en) | Semiconductor device and manufacturing method thereof | |
| US20150053991A1 (en) | Transistor having an ohmic contact by gradient layer and method of making the same | |
| CN112310189B (en) | Semiconductor device and method for manufacturing the same | |
| TWI798728B (en) | Semiconductor structures and manufacturing methods thereof | |
| TWI768222B (en) | Semiconductor device and manufacturing method of the same | |
| US11251264B2 (en) | Semiconductor device and manufacturing method of the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |