CN112305411B

CN112305411B - Functional test circuit and test method of I2S interface

Info

Publication number: CN112305411B
Application number: CN202011318103.4A
Authority: CN
Inventors: 王莉莉; 何再生
Original assignee: Zhuhai Amicro Semiconductor Co Ltd
Current assignee: Zhuhai Amicro Semiconductor Co Ltd
Priority date: 2020-11-23
Filing date: 2020-11-23
Publication date: 2025-02-14
Anticipated expiration: 2040-11-23
Also published as: CN112305411A

Abstract

The invention discloses a functional test circuit and a test method of an I2S interface, wherein the test circuit connects an I2SO INTF module and an I2S protocol signal interface of an I2SIN INTF module in a chip, and the signal interface comprises a bit clock signal interface, a left channel and right channel selection signal interface and an input/output signal interface. Meanwhile, a data selector is arranged between the I2SO INTF module and the I2SIN INTF module and is used for controlling the chip to enter a self-test mode or a normal mode. The testing method is simple and quick, can ensure correct functions, has short period and high accuracy, does not need an external verification board, and saves verification resources.

Description

Function test circuit and test method of I2S interface

Technical Field

The invention relates to the field of audio chip function test, in particular to a function test circuit and a test method of an I2S interface.

Background

The I2S (Inter-IC Sound) protocol is a bus standard established by philips for transmitting audio data between digital audio devices, and is mainly used for transmitting audio data between ICs, such as audio codec and DSP or DIGITAL FILTER. In general, whether the I2S interface circuit is designed correctly or not is verified by an FPGA external audio daughter board verification or testchip external chip verification mode so as to ensure that the design can be normally applied, but the method needs additional verification resources and has a long verification period.

Disclosure of Invention

In order to solve the problems, the invention provides a functional test circuit and a test method of an I2S interface, which greatly improve the simplicity and the test efficiency of the test method of the I2S interface. The specific technical scheme of the invention is as follows:

a functional test circuit of an I2S interface, the circuit comprising a PDMA module, an I2SO AFIFO module, an I2SIN AFIFO module, an I2SO INTF module, an I2SIN INTF module, a data selector, a signal switch, and two memories MEM1, MEM2, wherein the PDMA module is connected to the I2SO AFIFO module, the I2SIN AFIFO module, the MEM1 memory, and the MEM2 memory for transferring data of the MEM1 memory to the I2SO AFIFO module and transferring data of the I2SIN AFIFO module to the MEM2 memory; the I2SO AFIFO module is also connected with the I2SO INTF module, the I2SIN AFIFO module is also connected with the I2SIN INTF module, the I2SO AFIFO module and the I2SIN AFIFO module belong to asynchronous FIFOs and are used for data caching and asynchronous processing of an APB bus clock and a chip working clock, the I2SO INTF module is used for data parallel-serial conversion processing, the I2SIN INTF module is used for data serial-parallel conversion processing, the data selector is arranged between the I2SO INTF module and the I2SIN INTF module and is used for controlling the chip to enter a self-test mode or a normal mode, and the signal switch is connected with the data selector and is used for controlling the data selector to receive output data of the I2SO INTF module or external input data to switch the working mode of the chip. The test circuit completes signal connection of the I2SO INTF module and the I2SIN INTF module in the chip, designs a data selector and completes internal self-test of the I2S interface circuit by matching with a software program, and has the advantages of simple and quick test mode, capability of ensuring correct functions, short period, high accuracy, no need of an external verification board and verification resource saving.

Further, the I2S protocol signal interfaces of the I2SO INTF module and the I2SIN INTF module are connected in the chip, and the signal interfaces comprise a bit clock signal interface, a left channel and right channel selection signal interface and an input/output signal interface. The I2SO INTF module and the I2SIN INTF module are connected to enable signals to form a test loop inside the chip so as to simply and quickly complete the test of the I2S interface circuit.

Further, the signal switch is a register of the chip, and the data selector can switch the working mode of the chip through the configuration information of the register. The register of the chip is used as a signal switch, so that the circuit design is simplified, and the use mode of the chip is conveniently controlled to be switched.

Further, the data selector is provided with 4 interfaces, wherein the data input interface of the data selector is respectively connected with the I2SO INTF module and the external equipment, the data output interface is connected with the I2SIN INTF module, and the data selection switch interface is connected with the signal switch. The design of the data selector facilitates the chip to switch between the self-test mode and the normal mode.

Further, the I2SO AFIFO module includes a WDATA register, configured to check whether data enters the I2SO AFIFO module, where an address of the WDATA register is a fixed address of the buffered data, and is used as a target address of the PDMA module for writing the data.

Further, the I2SIN AFIFO module includes an RDATA register, which is used for checking whether there is data read out from the I2SIN AFIFO module, where an address of the RDATA register is a fixed address of the cache data, and is used as a source address of the PDMA module read out data.

A function test method of an I2S interface comprises the following steps of S1, transmitting configuration information of a signal switch to a data selector by a chip, judging the working mode of the chip, receiving external input data by the chip to process and finish output if the chip is in a normal mode, entering the step S2 if the chip is in a self-test mode, S2, transmitting parallel data in a MEM1 memory to an I2SO AFIFO module to buffer by a PDMA module, S3, transmitting data buffered in the I2SO AFIFO module to an I2SO INTF module to convert the data buffered in the I2SO AFIFO module to serial data, S4, transmitting the serial data in the I2SO INTF module to an I2SIN INTF module to convert the serial data into parallel data, S5, transmitting the parallel data to the I2SIN AFIFO module to buffer by the chip, transmitting the data to the MEM2 memory by the PDAM module, comparing the data in the 1 memory and the MEM2 memory if the data are the same, outputting PASS information, and outputting ERROR information if the data are different. The invention completes the signal connection of the I2SO INTF module and the I2SIN INTF module in the chip, designs a data selector and completes the internal self-test of the I2S interface circuit by matching with a software program, and the test mode is simple and quick, can ensure correct function, has short period and high accuracy, does not need an external verification board, and saves verification resources.

Further, in the step S1, the method for judging the working mode of the chip is to compare the configuration information input by the user with the preset information stored in the data selector in advance to obtain the working mode of the chip.

Further, in the steps S2 and S5, the PDMA module transfers the parallel data in the MEM1 memory to the I2SO AFIFO module and transfers the parallel data in the I2SIN AFIFO module to the MEM2 memory through the APB bus. The APB bus provides a low-power interface, reduces the complexity of the interface and saves the time required for testing.

Further, in the steps S3 and S4, the mutual conversion of the serial data and the parallel data is performed under a clock signal of the I2S protocol, the clock signal including a bit clock signal and left and right channel selection signals.

Further, the step S4 specifically includes the steps of S41, the chip carrying out I2S protocol docking of the I2SO INTF module and the I2SIN INTF module through the bit clock signal and the left and right channel selection signals, S42, the chip sending data to the I2SIN INTF module through the output signal interface of the I2SO INTF module, S43, the chip receiving data through the input signal interface of the I2SIN INTF module, S44, the chip carrying out serial-parallel conversion processing on the data in the I2SIN INTF module through the bit clock signal and the left and right channel selection signals.

Drawings

Fig. 1 is a schematic diagram of a functional test circuit of an I2S interface according to an embodiment of the invention.

Fig. 2 is a flowchart of a functional testing method of an I2S interface according to an embodiment of the present invention.

Detailed Description

The following describes the technical solution in the embodiment of the present invention in detail with reference to the drawings in the embodiment of the present invention. It should be understood that the following detailed description is merely illustrative of the invention, and is not intended to limit the invention.

In the following description, specific details are given to provide a thorough understanding of the embodiments. However, it will be understood by those of ordinary skill in the art that the embodiments may be practiced without these specific details. For example, circuits may be shown in block diagrams in order not to obscure the embodiments in unnecessary detail. In other instances, well-known circuits, structures and techniques may not be shown in detail in order not to obscure the embodiments.

As shown in fig. 1, a functional test circuit of an I2S Interface includes a PDMA module (Programmable Direct Memory Access, a programmable direct Memory access module) that can transfer data inside a system, an I2SO AFIFO module (Asynchronous First Input First Output, an asynchronous FIFO Memory of an I2S protocol output port) for caching data, an I2SIN AFIFO module (an asynchronous FIFO Memory of an I2S protocol input port) for caching data, an I2SO INTF module (an Interface, an I2S protocol output Interface module) for parallel-serial conversion processing of data, an I2SIN INTF module (an I2S protocol input Interface module) for serial-parallel conversion processing of data, a data selector for switching an operation mode of a chip, a signal switch for controlling the data selector to switch an operation mode of a chip, and two memories MEM1 (Memory 1) and MEM2 (Memory 2) for storing data before and after conversion for comparison. The PDMA module is connected with the I2SO AFIFO module, the I2SIN AFIFO module, the MEM1 memory and the MEM2 memory, and is used for transmitting data of the MEM1 memory to the I2SO AFIFO module and transmitting data of the I2SIN AFIFO module to the MEM2 memory, the I2SO AFIFO module is also connected with the I2SO INTF module, the I2SIN AFIFO module is also connected with the I2SIN INTF module, the I2SO AFIFO module and the I2SIN AFIFO module belong to an asynchronous FIFO and are used for data buffering and asynchronous processing of an APB bus clock and a chip working clock, the data selector is arranged between the I2SO INTF module and the I2SIN INTF module and is used for controlling the chip to enter a self-test mode or a normal mode, and the signal switch is connected with the data selector and is used for controlling the data selector to receive output data of the I2SO INTF module or external input data to switch the working mode of the chip. The test circuit completes signal connection of the I2SO INTF module and the I2SIN INTF module in the chip, designs a data selector and completes internal self-test of the I2S interface circuit by matching with a software program, and has the advantages of simple and quick test mode, capability of ensuring correct functions, short period, high accuracy, no need of an external verification board and verification resource saving.

As one implementation mode, the I2S protocol signal interfaces of the I2SO INTF module and the I2SIN INTF module are connected inside a chip, and the signal interfaces include a bit clock signal interface, a left channel and right channel selection signal interface and an input and output signal interface. The I2SO INTF module and the I2SIN INTF module are connected inside the chip, so that an internal test loop can be formed, and the test of the I2S interface circuit can be simply and quickly completed. A data selector is disposed between the I2SO INTF module and the I2SIN INTF module to implement data communication between the I2SO INTF module and the I2SIN INTF module. The data selector is provided with 4 interfaces, wherein the data input interface of the data selector is respectively connected with the I2SO INTF module and external equipment, the data output interface is connected with the I2SIN INTF module, and the data selection switch interface is connected with the signal switch. The signal switch is a register of the chip, and the data selector can switch the working mode of the chip through the configuration information of the register. For example, when the signal switch is set to 1, the chip enters a self-test mode, and signals flow from the I2SO INTF module to the I2SIN INTF module through the data selector, so that loop test inside the chip is completed. In the normal mode, the I2SIN INTF module is connected with an analog-to-digital converter ADC and a microphone to finish the input of external audio signals, and the I2SO INTF module is connected with a digital-to-analog converter DAC and a power amplifier to finish the output of audio signals. Through the mode of the external verification daughter board, the I2S interface circuit design can be tested. Or the I2S protocol signal interfaces of the I2SO INTF module and the I2SIN INTF module are connected and tested in a jumper connection mode. However, this requires a tester to manually look up the signal interface of the I2S protocol, and the test is set up at stage testchip after the design has been completed, with a very long period.

As one implementation manner, the I2SO AFIFO module includes a WDATA register, which is used to check whether there is data entering the I2SO AFIFO module, where the address of the WDATA register is a fixed address of the cached data, and is used as a target address of the PDMA module writing the data. The I2SIN AFIFO module comprises an RDATA register for checking whether data are read out from the I2SIN AFIFO module, wherein the address of the RDATA register is a fixed address for caching the data and is used as a source address for reading the data by the PDMA module.

As shown in FIG. 2, the method for testing the function of the I2S interface comprises the following steps of S1, transmitting configuration information of a signal switch to a data selector by a chip and judging the working mode of the chip, if the chip is in a normal mode, receiving external input data by the chip and processing the external input data to finish output, if the chip is in a self-test mode, entering the step S2, transmitting parallel data in a MEM1 memory to an I2SO AFIFO module to be cached by the chip through a PDMA module, S3, transmitting the data cached in the I2SO AFIFO module to the I2SO INTF module to be converted into serial data by the chip, S4, transmitting the serial data in the I2SO INTF module to the I2SIN INTF module to be converted into parallel data by the chip, transmitting the parallel data to the MEM2 SINAIFO module to be cached by the chip, and then transmitting the parallel data to the MEM2 through the PDMA module, and comparing the data in the MEM1 memory and the MEM2 memory by the chip, if the parallel data are identical, outputting PASS information and outputting ERR information if the data are different. The invention completes the signal connection of the I2SO INTF module and the I2SIN INTF module in the chip, designs a data selector and completes the internal self-test of the I2S interface circuit by matching with a software program, and the test mode is simple and quick, can ensure correct function, has short period and high accuracy, does not need an external verification board, and saves verification resources. In order to enable the chip to switch between the self-test mode and the normal mode, a data selector and a signal switch are arranged between the I2SO INTF module and the I2SIN INTF module, and the chip reads configuration information input by a user to switch the working mode. If the signal switch is set to 1, the method described in this embodiment is used to perform self-test of the I2S interface, and if the signal switch is set to 0, the chip can normally receive an external signal and output the signal to the outside. In the normal mode, the chip can be externally connected with a test sub-board for testing, such as an FPGA (field programmable gate array) externally connected with an audio sub-board or an audio codec chip, and the method belongs to the prior art and is not repeated here.

As one embodiment, in the steps S3 and S4, the mutual conversion of the serial data and the parallel data is performed under a clock signal of the I2S protocol, the clock signal including a bit clock signal and a left-right channel selection signal. The step S4 specifically comprises the steps of S41, S42, S43, S44, wherein the chip performs I2SO INTF and I2SIN INTF I2S protocol butt joint through a bit clock signal and a left and right channel selection signal, the chip sends data to the I2SIN INTF module through an output signal interface of the I2SO INTF module, the chip receives data through an input signal interface of the I2SIN INTF module, and the chip performs serial-parallel conversion processing on the data in the I2SIN INTF module through the bit clock signal and the left and right channel selection signal. The serial-parallel conversion method is various, a register, a Dual-port RAM, a Dual RAM, SRAM, SDRAM, FIFO and the like can be selected according to the sequence and the quantity requirement of data, and a shift register design can be adopted for a design with a relatively small quantity. The serial-to-parallel conversion of the present embodiment is implemented on the basis of a shift register, and the input serial data is "assembled" into new parallel data in a form of a group every 24 bits. Specifically, the input bit stream is fed into the shift register bit by bit, and then the serial-parallel converter reads the data at the output end of the shift register once every 24 clock cycles and outputs the data in a parallel 24-bit form.

As one embodiment, in the steps S2 and S5, the PDMA module transfers the parallel data in the MEM1 memory to the I2SO AFIFO module and transfers the parallel data in the I2SIN AFIFO module to the MEM2 memory through the APB bus. The APB bus provides a low-power interface, reduces the complexity of the interface and saves the time required for testing. The PDMA module needs to transfer the data in the MEM1 memory to the I2SO AFIFO module. Thus for a PDMA module the source address (MEM 1 memory) can be set arbitrarily by the software, but the destination address must be fixed, i.e. the I2SO AFIFO module needs to go out a register. Two uses are used, namely, software is used for checking the value of the register in real time to see whether data enter an I2SO AFIFO module during test, and the value is used as a target address of write-in data of a PDMA module to transmit the data in the MEM1 memory to a register address corresponding to the write-in data in the I2SO AFIFO module (for example, 0x400B_8024 is the I2SO AFIFO WDATA register address). The hardware design circuitry of the chip then transmits the data in the I2SO AFIFO module to the I2SO INTF module in real time. Similarly, the I2SIN AFIFO module also requires a register for storing the read data of the I2SIN AFIFO module. Two functions are used, namely, the software is used for checking the value of the register in real time to see whether data are read out from the I2SIN AFIFO module during test, and the data in the source address (such as 0x400B_8024 is the address of the I2SIN AFIFO RDATA register) are transmitted to the address space corresponding to the MEM2 memory opened by the software as the source address of the data read out by the PDMA module.

In the embodiments provided in the present invention, it should be understood that the disclosed system, apparatus and method may be implemented in other manners. For example, the apparatus embodiments described above are merely illustrative, e.g., the division of the units is merely a logical function division, and there may be additional divisions when actually implemented, e.g., multiple units or components may be combined or integrated into another system, or some features may be omitted or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or units, which may be in electrical, mechanical or other form. The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

It should be noted that the above embodiments are merely for illustrating the technical solution of the present invention and not for limiting the same, and although the present invention has been described in detail with reference to the above embodiments, it should be understood by those skilled in the art that the technical solution described in the above embodiments may be modified or some or all of the technical features may be equivalently replaced, and these modifications or substitutions do not make the essence of the corresponding technical solution deviate from the scope of the technical solution of the embodiments of the present invention.

Claims

1. A functional test circuit of an I2S interface is characterized by comprising a PDMA module, an I2SO AFIFO module, an I2SIN AFIFO module, an I2SO INTF module, an I2SIN INTF module, a data selector, a signal switch and two memories MEM1 and MEM2, wherein,

The PDMA module is connected with the I2SO AFIFO module, the I2SIN AFIFO module, the MEM1 memory and the MEM2 memory and is used for transmitting data of the MEM1 memory to the I2SO AFIFO module and transmitting data of the I2SIN AFIFO module to the MEM2 memory;

the I2SO AFIFO module is also connected with the I2SO INTF module, and the I2SIN AFIFO module is also connected with the I2SIN INTF module, wherein the I2SO AFIFO module and the I2SIN AFIFO module belong to asynchronous FIFO and are used for data caching and asynchronous processing of an APB bus clock and a chip working clock;

the I2SO INTF module is used for parallel-serial conversion processing of data, and the I2SIN INTF module is used for serial-parallel conversion processing of data;

The data selector is arranged between the I2SO INTF module and the I2SIN INTF module and is used for controlling the chip to enter a self-test mode or a normal mode;

the signal switch is connected with the data selector and is used for controlling the data selector to receive output data of the I2SO INTF module or receive external input data so as to switch the working mode of the chip.

2. The I2S interface function test circuit according to claim 1, wherein the I2S protocol signal interfaces of the I2SO INTF module and the I2SIN INTF module are connected inside a chip, and the signal interfaces include a bit clock signal interface, a left and right channel selection signal interface, and an input and output signal interface.

3. The I2S interface function test circuit of claim 1, wherein the signal switch is a register of the chip, and the data selector can switch the operation mode of the chip according to the configuration information of the register.

4. The I2S interface function test circuit according to claim 1, wherein the data selector has 4 interfaces, wherein the data input interface of the data selector is connected to the I2SO INTF module and the external device, the data output interface is connected to the I2SIN INTF module, and the data selection switch interface is connected to the signal switch.

5. The functional test circuit of claim 1, wherein the I2SO AFIFO module includes a WDATA register for checking whether any data enters the I2SO AFIFO module, and an address of the WDATA register is a fixed address of the buffered data, and is used as a target address of the PDMA module for writing the data.

6. The functional test circuit of claim 1, wherein the I2SIN AFIFO module includes an RDATA register for checking whether data is read from the I2SIN AFIFO module, and an address of the RDATA register is a fixed address of the buffered data, and is used as a source address of the PDMA module read data.

7. A method for testing functions of an I2S interface, the method comprising the steps of:

s1, transmitting configuration information of a signal switch to a data selector by a chip and judging the working mode of the chip, if the chip is in a normal mode, receiving external input data by the chip for processing and completing output, and if the chip is in a self-test mode, entering a step S2;

s2, the chip sends parallel data in the MEM1 memory to an I2SO AFIFO module for caching through a PDMA module;

s3, the chip sends the data cached in the I2SO AFIFO module to the I2SO INTF module to be converted into serial data;

s4, the chip sends serial data in the I2SO INTF module to the I2SIN INTF module and converts the serial data into parallel data;

s5, the chip sends the parallel data to an I2SIN AFIFO module for caching, and then sends the parallel data to a MEM2 memory through a PDAM module;

S6, the chip compares the data in the MEM1 memory and the MEM2 memory, if the data are the same, the PASS information is output, and if the data are different, the ERROR information is output.

8. The method for testing the I2S interface according to claim 7, wherein in the step S1, the method for determining the operation mode of the chip is to compare the configuration information input by the user with the preset information stored in the data selector in advance to obtain the operation mode of the chip.

9. The method according to claim 7, wherein in the steps S2 and S5, the PDMA module transfers the parallel data in the MEM1 memory to the I2SO AFIFO module and transfers the parallel data in the I2SIN AFIFO module to the MEM2 memory via the APB bus.

10. The method according to claim 7, wherein the mutual conversion of serial data and parallel data in steps S3 and S4 is performed under a clock signal of the I2S protocol, the clock signal including a bit clock signal and a left-right channel selection signal.

11. The method for testing the function of the I2S interface according to claim 7, wherein the step S4 specifically includes the steps of:

S41, the chip carries out I2S protocol butt joint of the I2SO INTF module and the I2SIN INTF module through the bit clock signal and the left and right channel selection signals;

S42, the chip sends data to the I2SIN INTF module through an output signal interface of the I2SO INTF module;

S43, the chip receives data through an input signal interface of the I2SIN INTF module;

S44, the chip performs serial-parallel conversion processing on the data in the I2SIN INTF module through the bit clock signal and the left and right channel selection signals.