CN112018037A - Method for manufacturing semiconductor device - Google Patents

Abstract

The invention provides a method for preparing a semiconductor device, which includes providing a semiconductor substrate, on which a gate electrode, a source electrode and a drain electrode are formed, then forming an interlayer dielectric layer on the semiconductor substrate, and etching the interlayer dielectric layer The layer forms a contact hole, wherein the contact hole connecting the drain electrode is strip-shaped, continuously exposing at least part of the drain electrode, and the contact hole connecting the gate electrode and the source electrode is point-shaped, intermittently exposing at least part of the gate electrode and the source electrode, Then, ions are implanted obliquely into the interlayer dielectric layer to ensure that ions in at least one direction are implanted into the drain through the contact hole to form an ion implantation region. In the present invention, ion implantation is performed through the contact hole in the interlayer dielectric layer to realize ESD protection. Compared with the prior art, a yellow light is made on the drain electrode to define the ion implantation region before the interlayer dielectric layer, and the present invention reduces one step of mask. The process saves the cost of the process, and is simple and easy to implement.

Description

Preparation method of semiconductor device

technical field

The present invention relates to the technical field of semiconductor manufacturing, in particular to a method for preparing a semiconductor device.

Background technique

As semiconductor device technology continues to move into sub-micron, deep sub-micron, the reliability of ESD (Electrostatic Discharge) protection devices becomes more and more important. For MOS devices used as ESD protection, in order to achieve the purpose of internal circuit protection, the breakdown voltage of MOS devices used as ESD protection is often required to be slightly lower than the protected device, and the series resistance of the drain region is higher than that of the protected device. In order to achieve this goal, the method of increasing ion implantation (ESD implant) in the drain region is often used to reduce the breakdown voltage of the ESD device. However, increasing the ion implantation in the drain region requires an additional mask, thus increasing the manufacturing cost.

SUMMARY OF THE INVENTION

The purpose of the present invention is to provide a preparation method of a semiconductor device, which can realize ESD protection by ion implantation through the contact hole in the interlayer dielectric layer, reduce the mask process, save the process cost, and is simple and easy to implement.

The present invention provides a preparation method of a semiconductor device, comprising:

A semiconductor substrate is provided, a gate electrode is formed on the semiconductor substrate, and a source electrode and a drain electrode are formed in the semiconductor substrate on both sides of the gate electrode;

forming an interlayer dielectric layer on the semiconductor substrate;

The interlayer dielectric layer is etched to form contact holes connecting the gate electrode, the source electrode and the drain electrode respectively, wherein the contact hole connecting the drain electrode is strip-shaped and continuously exposes at least part of all the contact holes. the drain electrode, the contact hole connecting the gate electrode and the source electrode is point-shaped, and intermittently exposes at least part of the gate electrode and the source electrode; and

Ions are implanted obliquely into the interlayer dielectric layer from multiple directions to ensure that ions in at least one direction are implanted into the drain through the contact hole to form an ion implantation region.

Optionally, the shape of the contact hole connecting the drain electrode is a rectangle, the contact hole connecting the gate electrode and the source electrode is square, and the side length of the square is less than or equal to the wide side of the rectangle. side length.

Optionally, ions are implanted obliquely into the contact hole from four directions, so as to ensure that ions are implanted in at least two directions into the drain, and no ions are implanted into the gate due to the thickness of the interlayer dielectric layer. or the source.

Optionally, the ion implantation has different tilt angles in different directions.

Optionally, a plurality of gates are formed on the semiconductor substrate, and the ion implantation region is located at the center of the drain between adjacent gates.

Optionally, the ions include at least one of boron fluoride ions, boron ions or indium ions.

Optionally, the implantation dose of the ions is 1.0E13 atom/cm ² to 1.0E15 atom/cm ² , and the implantation energy of the ions is 40 kev to 100 kev.

Optionally, after the ion implantation, the method further includes filling the contact hole with a conductive material to form a conductive connector.

In summary, the present invention provides a method for fabricating a semiconductor device, including providing a semiconductor substrate on which a gate electrode, a source electrode and a drain electrode are formed, and then forming an interlayer dielectric layer on the semiconductor substrate , and etch the interlayer dielectric layer to form a contact hole, wherein the contact hole connecting the drain electrode is strip-shaped, continuously exposing at least part of the drain electrode, and connecting the contact between the gate electrode and the source electrode The hole is in the shape of a point, and at least part of the gate electrode and the source electrode is exposed intermittently, and then ions are implanted obliquely into the interlayer dielectric layer from multiple directions, so as to ensure that ions in at least one direction pass through the contact hole Implanted into the drain to form an ion implantation region. In the present invention, ion implantation is performed through the contact hole in the interlayer dielectric layer to realize ESD protection, and according to the thickness of the interlayer dielectric layer, the size of the contact hole is controlled, and the inclination angle of the ion implantation is adjusted, so that the ions only enter the drain electrode Compared with the prior art, a yellow light is made on the drain to define the ion implantation region before the interlayer dielectric layer, the present invention reduces one step of mask process, saves the process cost, and is simple and easy Row.

Description of drawings

FIG. 1 is a flowchart of a method for fabricating a semiconductor device according to an embodiment of the present invention;

2-FIG. 3B are schematic structural diagrams corresponding to each step in a method for fabricating a semiconductor device according to an embodiment of the present invention, wherein FIG. 3A is a top view of the semiconductor device when ions are implanted obliquely into the interlayer dielectric layer from multiple directions (the layers are omitted). Figure 2 and Figure 3B are schematic cross-sectional views of Figure 3A along the AA' direction in different steps;

Among them, the reference numerals are:

100-semiconductor substrate; 100a-well; 100b-isolation structure; 111-gate oxide layer; 112-gate; 113-spacer; 101-source; 102-drain; 103-interlayer dielectric layer; 104- Contact hole; 105 - ion implantation area; 106 - metal pad.

Detailed ways

The fabrication method of the semiconductor device of the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer from the following description and accompanying drawings. However, it should be noted that the concept of the technical solution of the present invention can be implemented in various forms, and is not limited to the specific implementation described here. example. The accompanying drawings are all in a very simplified form and use inaccurate scales, and are only used to facilitate and clearly assist the purpose of illustrating the embodiments of the present invention.

The terms "first," "second," etc. in the specification are used to distinguish between similar elements, and are not necessarily used to describe a particular order or temporal order. It is to be understood that the terms so used are interchangeable under appropriate circumstances, eg, to enable the embodiments of the invention described herein to operate in other sequences than described or illustrated herein. Similarly, if a method described herein includes a series of steps, the order of the steps presented herein is not necessarily the only order in which the steps may be performed, and some of the steps described may be omitted and/or some not described herein Additional steps can be added to this method. If the components in a certain drawing are the same as the components in other drawings, although these components can be easily identified in all the drawings, in order to make the description of the drawings clearer, this specification will not refer to all the same components. Numbers are attached to each figure.

FIG. 1 is a flowchart of a method for fabricating a semiconductor device provided by this embodiment. As shown in FIG. 1 , the method for fabricating a semiconductor device provided by this embodiment includes:

S01: providing a semiconductor substrate, a gate electrode is formed on the semiconductor substrate, and a source electrode and a drain electrode are formed in the semiconductor substrate on both sides of the gate electrode;

S02: forming an interlayer dielectric layer on the semiconductor substrate;

S03: Etch the interlayer dielectric layer to form contact holes connecting the gate electrode, the source electrode and the drain electrode respectively, wherein the contact hole connecting the drain electrode is strip-shaped, continuously exposing at least a part of the drain electrode, the contact hole connecting the gate electrode and the source electrode is point-shaped, and intermittently exposes at least part of the gate electrode and the source electrode; and,

S04 : implanting ions obliquely into the interlayer dielectric layer from multiple directions to ensure that ions in at least one direction are implanted into the drain through the contact hole to form an ion implantation region.

2-FIG. 3B are schematic structural diagrams corresponding to each step in a method for fabricating a semiconductor device according to an embodiment of the present invention, wherein FIG. 3A is a top view of the semiconductor device when ions are implanted obliquely into the interlayer dielectric layer from multiple directions (the layers are omitted). Figure 2 and Figure 3B are schematic cross-sectional views of Figure 3A along the AA' direction in different steps, respectively. The method for fabricating the semiconductor device provided in this embodiment will be described in detail below with reference to FIG. 1 and FIG. 2 to FIG. 3B .

First, referring to FIG. 2 , step S01 is performed to provide a semiconductor substrate 100 , a gate electrode 112 is formed on the semiconductor substrate 100 , and a source electrode 101 is formed in the semiconductor substrate on both sides of the gate electrode 112 and drain 102.

The semiconductor substrate 100 may be at least one of the following materials: silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon germanium-on-insulator (S SiGeOI), silicon-on-insulator Silicon germanium (SiGeOI) and germanium on insulator (GeOI), etc. In this embodiment, the semiconductor substrate is a P-type substrate,

A well 100 a and an isolation structure (STI) 100 b are formed in the substrate 100 , and the semiconductor substrate 200 selected in this embodiment is a P-type semiconductor substrate (P-Substrate), in which the P-type semiconductor substrate is A P-well (PW) is formed. The semiconductor device provided in this embodiment is an NMOS transistor, a gate oxide layer 111 is further formed between the gate 112 and the semiconductor substrate 100 , a sidewall 113 is also formed on the sidewall of the gate 112 , and the gate oxide layer 113 is formed. 111 , the gate 112 and the sidewall spacers 113 constitute a gate structure. Specifically, the gate oxide material layer and the gate material layer may be deposited by, but not limited to, chemical vapor deposition; then, the gate electrode 112 and the gate oxide layer 111 may be etched by but not limited to a plasma dry etching process; then , may also include: forming sidewalls 113 on the sidewalls of the gate 112, and the structure of the sidewalls 113 may be an ON structure or an ONO structure. Optionally, the gate 112 is formed by selective etching. deposited polysilicon.

Next, source and drain regions are implanted in the P well to form a source electrode 101 and a drain electrode 102, and the conductivity type of the source electrode 101 and the drain electrode 102 is opposite to that of the well 100a. Specifically, using the gate structure as a mask, N-type ions, such as arsenic ions, are implanted to form an N+ diffusion region, forming the source electrode 101 and the drain electrode 102, and the drain electrode 101 and the source electrode 102 are spaced apart Wherein, the gate electrode 112 is disposed between the drain electrode 101 and the source electrode 102 . Of course, in the actual fabrication process, in order to effectively prevent the short channel effect and reduce the hot electron effect of the channel in the source-drain region, before the source electrode 101 and the drain electrode 102 are formed, the source electrode 101 and the drain electrode 102 are formed. The drain region of the drain region is first lightly doped (LDD), which is a technical means commonly used by those of ordinary skill in the art, and details are not described here.

Next, referring to FIG. 3A and FIG. 3B , step S02 and step S03 are performed, an interlayer dielectric layer 103 is formed on the semiconductor substrate 100 , the interlayer dielectric layer 103 is etched, and the gate is formed to be connected to the gate. The contact hole 104 of the electrode 112, the source electrode 101 and the drain electrode 102, wherein the contact hole 104 connecting the drain electrode 102 is strip-shaped, continuously exposing at least part of the drain electrode 102, and connecting the drain electrode 102. The contact holes 104 of the gate electrode 112 and the source electrode 101 are in a point shape, and at least part of the gate electrode 112 and the source electrode 101 are intermittently exposed.

First, an interlayer dielectric layer 103 is formed on the semiconductor substrate 100 . The material of the interlayer dielectric layer 103 includes but is not limited to SiO ₂ (silicon oxide), Si ₃ N ₄ (silicon nitride), BPSG (borophosphosilicate glass), PSG (phosphosilicate glass) and other low dielectric constants (Dielectric constant less than 3) insulating material. Optionally, the interlayer dielectric layer 103 is a SiO ₂ layer fabricated by a high aspect ratio deposition process. The high aspect ratio deposition process has good filling ability, so that the interlayer dielectric layer fabricated by the high aspect ratio deposition process has good adhesion between the surrounding devices, thereby further improving the isolation performance of the interlayer dielectric layer.

Next, a photoresist is coated on the interlayer dielectric layer 103, a contact hole pattern is formed on the interlayer dielectric layer 103 through exposure and development, and then the photoresist layer with the contact hole pattern is used as a mask for etching The interlayer dielectric layer 103 forms a contact hole 104 connecting the gate electrode 112 , the source electrode 101 and the drain electrode 102 . The shape of the contact hole 104 that communicates with the drain electrode 102 is different from the shape of the contact hole 104 that communicates with the gate electrode 112 and the source electrode 101 , for example, the contact hole that communicates with the drain electrode 102 The shape of the hole 104 is a rectangle, and the contact hole 104 connecting the gate electrode 112 and the source electrode 101 is a square shape. The side length of the square is less than or equal to the broad side length of the rectangle. In other embodiments of the present invention, the shape of the contact hole 104 that communicates with the drain electrode 102 and the shape of the contact hole 104 that communicates with the gate electrode 112 and the source electrode 101 may also be other different shapes to ensure that When ions are implanted into the contact hole in four directions, at least one direction of ions is implanted into the drain electrode 102, and no ions are implanted into the gate electrode 112 or the source electrode due to the thickness of the interlayer dielectric layer 103. 101, that is, ion implantation is performed by means of the contact hole 104, and multi-directional oblique implantation is adopted, and the interlayer dielectric layer 103 is used as a barrier layer by using the different shape of the contact hole, so that ions cannot be implanted into the gate 112 through the contact hole. and the source 101.

A plurality of gate electrodes 112 are formed on the semiconductor substrate 100 , and the contact hole 104 communicating with the drain electrodes 102 is located at the center of the drain electrodes 102 between adjacent gate electrodes 112 . In this embodiment, the number of the contact holes 104 connecting the drain electrodes 102 between adjacent gates 112 is one, and the number of the contact holes connecting the source electrodes on both sides of the adjacent gates for multiple. It should be noted that the photoresist layer with the contact hole pattern can be removed after the contact hole 104 is formed, or it can be retained, and then removed after the ion implantation is completed, so that the photoresist layer also acts as a mask for the ion implantation effect.

Next, referring to FIG. 3A and FIG. 3B , step S04 is performed, and ions are implanted obliquely into the interlayer dielectric layer 103 from multiple directions, so as to ensure that ions in at least one direction are implanted into the drain through the contact hole 104 The electrode 101 is formed to form an ion implantation region 105 , and no ions are implanted into the gate electrode 112 or the source electrode 101 due to the barrier of the thickness of the interlayer dielectric layer 103 . For example, ions can be implanted obliquely into the interlayer dielectric layer 103 from multiple directions by means of blanket implantation, that is, the ion implantation is performed on the interlayer dielectric layer 103 without using a mask. The implanted ions are at least one of boron fluoride ions, boron ions or indium ions, the implantation dose of the ions is 1.0E13atom/cm ² ～1.0E15atom/cm ² , and the implantation energy of the ions is 40kev～100kev . In this embodiment, the ions are implanted at an oblique angle. Specifically, since the shape of the contact hole 104 connecting the drain electrode 102 is a rectangle, the contact hole 104 connecting the gate electrode 112 and the source electrode 101 are all rectangular in shape. It is a square, and the side length of the square is less than or equal to the side length of the broad side of the rectangle, so this embodiment is inclined from four directions (a direction, b direction, c direction and d direction) to the contact hole 104 Implanted ions, that is, ions in at least two of the four directions (a direction and c direction) are implanted into the drain electrode 102 through the contact hole 104, and no ions are implanted into the gate due to the barrier of the thickness of the interlayer dielectric layer 103 112 or source 102. The inclination angle of the ion implantation in the four directions may be the same, and may also have different inclination angles in different implantation directions. The thickness of the interlayer dielectric layer 103 is adjusted, and the energy and dose of ion implantation are adjusted so that the ions are implanted into the drain 102 at the center of the two adjacent gate electrodes 112 to form an ion implantation region 105 in the region below the drain electrodes 102 .

In the present application, the number of the contact holes 104 between the adjacent gates 112 that communicate with the drain 102 is one, and the number of the contact holes that communicate with the source on both sides of the adjacent gates 112 There are multiple ion implantation regions 105 , that is, the ion implantation region 105 implanted on the drain electrode 102 between the adjacent gate electrodes 1120 through the contact hole 104 is a complete long strip, and the contact holes 104 connecting the source electrodes are distributed in a point shape. at source 101 . And by controlling the size of the contact hole, the window of the ion implantation can be adjusted, so that the ions only enter the drain region without being implanted into other regions.

In this embodiment, after the contact hole is formed in the interlayer dielectric layer, ions are implanted into the drain through the contact hole in the interlayer dielectric layer, and according to the shape and size of the contact hole connecting the drain, the source and the gate, from Ions are implanted obliquely into the interlayer dielectric layer in multiple directions, so as to ensure that ions in at least one direction are implanted into the drain electrode through the contact hole, and no ions are implanted into the gate electrode or the gate electrode due to the barrier of the thickness of the interlayer dielectric layer. source. Compared with the prior art, a yellow light is made on the drain to define the ion implantation area before the interlayer dielectric layer. In the present application, the ion implantation is realized through the contact hole in the interlayer dielectric layer, which reduces one step of mask process and saves the process. cost and simplicity.

In this embodiment, the preparation method of the semiconductor device further includes, after ion implantation, filling the contact hole 104 with a conductive material to form a conductive connector (conductive plug), and then depositing a conductive material on the interlayer dielectric layer metal, forming a metal pad 106 that connects the conductive connections.

In summary, the present invention provides a method for fabricating a semiconductor device, including providing a semiconductor substrate on which a gate electrode, a source electrode and a drain electrode are formed, and then forming an interlayer dielectric layer on the semiconductor substrate , and etch the interlayer dielectric layer to form a contact hole, wherein the contact hole connecting the drain electrode is strip-shaped, continuously exposing at least part of the drain electrode, and connecting the contact between the gate electrode and the source electrode The hole is in the shape of a point, and at least part of the gate electrode and the source electrode is exposed intermittently, and then ions are implanted obliquely into the interlayer dielectric layer from multiple directions, so as to ensure that ions in at least one direction are implanted through the contact hole An ion implantation region is formed into the drain. In the present invention, ion implantation is performed through the contact hole in the interlayer dielectric layer to realize ESD protection, and according to the thickness of the interlayer dielectric layer, the size of the contact hole is controlled, and the inclination angle of the ion implantation is adjusted, so that the ions only enter the drain electrode Compared with the prior art, a yellow light is made on the drain to define the ion implantation region before the interlayer dielectric layer, the present invention reduces one step of mask process, saves the process cost, and is simple and easy Row.

The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes and modifications made by those of ordinary skill in the field of the present invention based on the above disclosure all belong to the protection scope of the claims.

Claims (8)

1. A method of manufacturing a semiconductor device, comprising:

providing a semiconductor substrate, wherein a grid electrode is formed on the semiconductor substrate, and a source electrode and a drain electrode are formed in the semiconductor substrate on two sides of the grid electrode;

forming an interlayer dielectric layer on the semiconductor substrate;

etching the interlayer dielectric layer to respectively form contact holes communicated with the grid electrode, the source electrode and the drain electrode, wherein the contact holes communicated with the drain electrode are strip-shaped, at least part of the drain electrode is continuously exposed, the contact holes communicated with the grid electrode and the source electrode are point-shaped, and at least part of the grid electrode and the source electrode are discontinuously exposed; and

and injecting ions obliquely into the interlayer dielectric layer from multiple directions to ensure that ions in at least one direction are injected into the drain electrode through the contact hole to form an ion injection region.

2. The method according to claim 1, wherein a contact hole for connecting the drain electrode is rectangular, contact holes for connecting the gate electrode and the source electrode are square, and a side length of the square is less than or equal to a side length of a wide side of the rectangle.

3. The method of claim 2, wherein ions are implanted obliquely from four directions into the contact hole to ensure that ions are implanted into the drain in at least two directions and no ions are implanted into the gate or the source due to the blocking of an interlayer dielectric layer.

4. The method of manufacturing a semiconductor device according to claim 1, wherein the ion implantation has different tilt angles in different directions.

5. The method according to claim 1, wherein a plurality of gates are formed over the semiconductor substrate, and wherein the ion implantation region is located at a midpoint of the drain between adjacent gates.

6. The method for manufacturing a semiconductor device according to claim 1, wherein the ions include at least one of boron fluoride ions, boron ions, or indium ions.

7. The method for manufacturing a semiconductor device according to claim 6, wherein the ion implantation dose is 1.0E13 atoms/cm²～1.0E15 atoms/cm²The implantation energy of the ions is 40 to 100 kev.

8. The method as claimed in claim 1, further comprising filling a conductive material in the contact hole after the ion implantation to form a conductive connection member.

Images