CN111933745A - A kind of preparation method of black silicon passivation contact cell based on reactive ion etching - Google Patents

Abstract

The invention relates to a preparation method of a black silicon passivation contact battery based on reactive ion etching. The method includes: performing reactive ion etching treatment on the front surface of the n-type single crystal silicon substrate after texturing, so as to form nano-scale hole structures on the micron-level pyramid structure; cleaning the n-type single crystal silicon substrate to remove reactive ions The residues generated in the etching process and the damaged layer formed by ion bombardment are subjected to hole expansion treatment on the nanoscale hole structure; and the n-type single crystal silicon substrate is subjected to post-treatment. The preparation method of the present invention does not introduce metal ions, does not require high subsequent cleaning processes, and can obtain a nano-scale hole structure with a custom size, the process is simple, the stability is reliable, and it is suitable for mass production.

Description

A kind of preparation method of black silicon passivation contact cell based on reactive ion etching

technical field

The invention relates to the technical field of solar cells, in particular to a preparation method of a black silicon passivation contact cell based on reactive ion etching.

Background technique

In crystalline silicon solar cells, optical, electrical and resistive losses are the main factors limiting the efficiency of solar cells. Among the existing commercial crystalline silicon solar cells, polycrystalline solar cells are textured with acid to form a worm-like hole structure, and the surface reflectivity after textured is 16%-20%; The surface of the battery adopts alkali texturing technology to form a pyramid structure, which can obtain a lower surface reflectivity than conventional polycrystalline batteries, and the reflectivity after texturing is 11%-13%. Due to the promotion of diamond wire cutting of polycrystalline silicon wafers, the surface reflectivity after the conventional acid texturing process is higher, and it is accompanied by obvious appearance defects such as line marks, which seriously affects the efficiency of polycrystalline cells. Black silicon technology can perfectly solve this problem. .

At present, some domestic manufacturers have applied the black silicon technology to the production of polycrystalline cells. This technology can reduce the surface reflectivity and increase the short-circuit current of the battery, thereby improving the battery efficiency. However, the application of black silicon technology in monocrystalline cells is rarely reported. Superimposing black silicon technology in single crystal cells can further reduce the reflectivity of the cell surface, increase the short-circuit current, and thus improve the cell efficiency; in addition, the surface reflectivity of black silicon single crystal cells is very low at all angles, while conventional single crystal cells are only suitable for The light reflectivity of normal incidence is low, and the black silicon TOPCon cell can meet the needs of Tesla watts.

At present, the commonly used black silicon technologies are as follows: 1) laser etching method, 2) vapor phase etching method, and 3) metal catalyzed chemical etching method. Among them, the laser etching method and the vapor phase etching method are rarely used in industrialization due to the high cost of equipment, and are generally used in laboratory research.

The metal-catalyzed chemical etching method is widely used in the polycrystalline battery industry. It mainly uses the catalytic ability of metals to etch the silicon surface by using a mixed solution of AgNO ₃ /H ₂ O ₂ or a mixed solution of CuSO ₄ /HF. The principle is: after the metal ions in the solution diffuse to the surface of the silicon wafer, the absorbed electrons from the silicon wafer are reduced to metal element and adsorbed on the surface of the silicon wafer, and at the same time, the silicon under the metal element is oxidized to silicon oxide. Then, a nanoscale hole structure is formed on the surface of the silicon wafer. This preparation method will introduce metal ions, which will have higher requirements for subsequent cleaning; and, in this preparation method, the size of the nano-scale hole structure formed is related to the size of the introduced metal particles, and a custom-sized hole structure cannot be obtained.

SUMMARY OF THE INVENTION

The purpose of the present invention is to overcome the deficiencies of the prior art, and to provide a preparation method of a black silicon passivation contact cell based on reactive ion etching.

A preparation method of a black silicon passivation contact cell based on reactive ion etching of the present invention comprises the following steps:

(1), perform reactive ion etching on the front surface of the n-type single crystal silicon substrate after texturing, so as to form a nano-scale hole structure on the micron-scale pyramid structure;

(2), cleaning the n-type single crystal silicon substrate processed in step (1) to remove the residues produced in the reactive ion etching process and the damaged layer formed by ion bombardment, and to expand the nano-scale hole structure deal with;

(3), performing post-processing on the n-type single crystal silicon substrate processed in step (2).

The preparation method of a black silicon passivation contact cell based on reactive ion etching provided by the present invention also includes the following subsidiary technical solutions:

Wherein, in step (1),

The gas for reactive ion etching is a mixed gas of SF ₄ , CL ₂ and O ₂ , and the power of reactive ion etching is 100-600w; wherein, the volume ratio of SF ₄ , CL ₂ and O ₂ is 1:1:2- 1:1:4.

Wherein, in step (1),

The inner diameter of the nanoscale hole structure is 50-300 nm, and the depth is 50-300 nm.

Wherein, in step (2),

The n-type single crystal silicon substrate treated in step (1) is cleaned with a mixed solution of BOE, H ₂ O ₂ and H ₂ O. The cleaning temperature is 20-25° C. and the cleaning time is 30-3000 s.

In step (2),

In the mixed solution of BOE, H ₂ O ₂ and H ₂ O, the volume ratio of BOE, H ₂ O ₂ and H ₂ O is 1:2:5.

Wherein, in step (3), the post-processing of the n-type single crystal silicon substrate processed in step (2) includes:

(3.1) Doping the n-type single crystal silicon substrate processed in step (2) with boron to form a front p+ emitter and a back p+ emitter;

(3.2), the backside of the n-type single crystal silicon substrate is etched with an acidic solution to remove the p+ emitter on the backside, and a flat morphology is formed on the backside of the n-type single crystal silicon substrate;

(3.3), prepare the backside tunneling oxide layer and the backside doped polysilicon layer on the backside of the n-type single crystal silicon substrate;

(3.4), prepare a front passivation anti-reflection film on the front of the n-type single crystal silicon substrate, and prepare a back passivation anti-reflection film on the back of the n-type single crystal silicon substrate;

(3.5) Prepare front "H" type grid lines on the front side of the n-type single crystal silicon substrate, and prepare back "H" type grid lines on the back side of the n-type single crystal silicon substrate.

Wherein, in step (3.1),

The n-type single crystal silicon substrate treated in step (2) is doped with boron by means of boron diffusion, the boron source for boron diffusion is boron tribromide, the diffusion temperature is 950-1100°C, and the diffusion resistance is 70-150Ω /sq.

Wherein, in step (3.2),

A mixed solution of HF/HNO ₃ /H ₂ SO ₄ is used to etch the back of the n-type single crystal silicon substrate. After the etching is completed, the weight of the n-type single crystal silicon substrate is reduced by 0.4-0.8 g; among them, HF, HNO ₃ and H The volume ratio of _2SO4 is ₃ :7:1.

Wherein, in step (3.3),

The thickness of the back surface tunnel oxide layer is 0.5-1.5 nm, and the thickness of the back surface doped polysilicon layer is 60-300 nm.

Wherein, in step (3.4),

The front passivation anti-reflection film is a laminated film of aluminum oxide and silicon nitride, and the back passivation anti-reflection film is a single-layer film of silicon nitride.

Wherein, in step (3.5),

The front "H" type grid line includes a front main grid and a front sub grid; 4-12 front main grids are arranged at equal intervals, with a width of 100-800 μm and a height of 10-40 μm; the back sub-grids, etc. The spacing is set to 90 to 120, the width is 20 to 60 μm, and the height is 10 to 40 μm;

The backside "H" type grid line includes a backside busbar and a backside subgrid; 4-12 backside busbars are arranged at equal intervals, with a width of 100-800 μm and a height of 10-40 μm; the backside subgrids, etc. The pitch is set to 90 to 120, the width is 20 to 60 μm, and the height is 10 to 40 μm.

Wherein, before step (1), the method also includes:

(1)', pre-cleaning the n-type single crystal silicon substrate, removing the mechanical damage layer, and performing alkali texturing treatment to form a pyramid structure, and the thickness of the pyramid structure near one end of the n-type single crystal silicon substrate is 2-5um.

The implementation of the present invention includes the following technical effects:

Compared with the conventional passivation contact cell, the black silicon passivation contact cell of the present invention has good absorption of light in all directions, and is not affected by the incident angle of the light. Furthermore, the present invention aims at increasing the electrical loss due to the large specific surface area of the black silicon technology, and makes up for the electrical loss by adjusting the cleaning process after the reactive ion etching of the black silicon, thereby ensuring that the open circuit voltage remains flat. Finally, the preparation method of the present invention does not introduce metal ions, which does not have high requirements on the subsequent cleaning process, and can obtain a nano-scale hole structure with a custom size. The process is simple, the stability is reliable, and it is suitable for mass production.

Description of drawings

Fig. 1 is a schematic cross-sectional view of the battery structure after step (1)' of a method for preparing a black silicon passivation contact battery based on reactive ion etching according to an embodiment of the present invention.

2 is a schematic cross-sectional view of the battery structure after step (1) of a method for preparing a black silicon passivation contact battery based on reactive ion etching according to an embodiment of the present invention.

3 is a schematic cross-sectional view of the cell structure after step (3.1) of a method for preparing a black silicon passivation contact cell based on reactive ion etching according to an embodiment of the present invention.

4 is a schematic cross-sectional view of the cell structure after step (3.2) of a method for preparing a black silicon passivation contact cell based on reactive ion etching according to an embodiment of the present invention.

5 is a schematic cross-sectional view of the cell structure after step (3.3) of a method for preparing a black silicon passivation contact cell based on reactive ion etching according to an embodiment of the present invention.

6 is a schematic cross-sectional view of the cell structure after step (3.4) of a method for preparing a black silicon passivation contact cell based on reactive ion etching according to an embodiment of the present invention.

7 is a schematic cross-sectional view of the cell structure after step (3.5) of a method for preparing a black silicon passivation contact cell based on reactive ion etching according to an embodiment of the present invention.

In the figure, 1-N-type crystal n-type single crystal silicon substrate, 2-pyramid structure, 3-nano-scale hole structure, 4-p+ emitter, 5-flat morphology, 6-backside tunneling oxide layer, 7-backside Doped polysilicon layer, 8 - front passivation anti-reflection film, 9 - back passivation anti-reflection film, 10 - front "H" type grid line, 11 - back side "H" type grid line.

Detailed ways

The present invention will be described in detail below with reference to examples.

The specific embodiment is only an explanation of the present invention, not a limitation of the present invention. Those skilled in the art can make modifications without creative contribution to the present embodiment as required after reading this specification, but only within the scope of the claims of the present invention are protected inside.

A preparation method of a black silicon passivation contact cell based on reactive ion etching of the present invention comprises the following steps:

(1), perform reactive ion etching on the front surface of the n-type single crystal silicon substrate after texturing, so as to form a nano-scale hole structure on the micron-scale pyramid structure;

(2), cleaning the n-type single crystal silicon substrate processed in step (1) to remove the residues produced in the reactive ion etching process and the damaged layer formed by ion bombardment, and to expand the nano-scale hole structure deal with;

(3), performing post-processing on the n-type single crystal silicon substrate processed in step (2).

The invention creatively combines the reactive ion etching black silicon technology with the single crystal TOPCon battery technology, reduces the surface reflectivity of the battery, increases the short-circuit current of the battery, and thus improves the current efficiency. Moreover, compared with the conventional passivation contact cell, the black silicon passivation contact cell in the present invention has good absorption of light in all directions, and is not affected by the incident angle of the light. Furthermore, the present invention aims at increasing the electrical loss due to the large specific surface area of the black silicon technology, and makes up for the electrical loss by adjusting the cleaning process after the reactive ion etching of the black silicon, thereby ensuring that the open circuit voltage remains flat. Finally, the preparation method of the present invention does not introduce metal ions, which does not have high requirements on the subsequent cleaning process, and can obtain a nano-scale hole structure with a custom size. The process is simple, the stability is reliable, and it is suitable for mass production.

In one embodiment, in step (1),

The gas for reactive ion etching is a mixed gas of SF ₄ , CL ₂ and O ₂ , and the power of reactive ion etching is 100-600w; wherein, the volume ratio of SF ₄ , CL ₂ and O ₂ is 1:1:2- 1:1:4.

The inner diameter of the nanoscale hole structure is 50-300 nm, and the depth is 50-300 nm.

In one embodiment, in step (2),

The n-type single crystal silicon substrate treated in step (1) is cleaned with a mixed solution of BOE, H ₂ O ₂ and H ₂ O. The cleaning temperature is 20-25° C. and the cleaning time is 30-3000 s.

In the mixed solution of BOE, H ₂ O ₂ and H ₂ O, the volume ratio of BOE, H ₂ O ₂ and H ₂ O is 1:2:5.

It should be noted that BOE in this embodiment is the abbreviation of the mixed solution of ammonium fluoride and hydrofluoric acid.

In one embodiment, in step (3), the post-processing of the n-type single crystal silicon substrate processed in step (2) includes:

(3.1) Doping the n-type single crystal silicon substrate processed in step (2) with boron to form a front p+ emitter and a back p+ emitter;

(3.2), the backside of the n-type single crystal silicon substrate is etched with an acidic solution to remove the p+ emitter on the backside, and a flat morphology is formed on the backside of the n-type single crystal silicon substrate;

(3.3), prepare the backside tunneling oxide layer and the backside doped polysilicon layer on the backside of the n-type single crystal silicon substrate;

(3.4), prepare a front passivation anti-reflection film on the front of the n-type single crystal silicon substrate, and prepare a back passivation anti-reflection film on the back of the n-type single crystal silicon substrate;

(3.5), prepare the front "H" type grid line on the front side of the n-type single crystal silicon substrate, and prepare the back "H" type grid line on the back side of the n-type single crystal silicon substrate;

In one embodiment, in step (3.1),

The n-type single crystal silicon substrate treated in step (2) is doped with boron by means of boron diffusion, the boron source for boron diffusion is boron tribromide, the diffusion temperature is 950-1100°C, and the diffusion resistance is 70-150Ω /sq.

In one embodiment, in step (3.2),

A mixed solution of HF/HNO ₃ /H ₂ SO ₄ is used to etch the back surface of the n-type single crystal silicon substrate. After the etching is completed, the weight of the n-type single crystal silicon substrate is reduced by 0.4-0.8 g.

In one embodiment, in step (3.3),

The thickness of the back surface tunnel oxide layer is 0.5-1.5 nm, and the thickness of the back surface doped polysilicon layer is 60-300 nm.

In one embodiment, in step (3.4),

The front passivation anti-reflection film is a laminated film of aluminum oxide and silicon nitride, and the back passivation anti-reflection film is a single-layer film of silicon nitride.

In one embodiment, in step (3.5),

The front "H" type grid line includes a front main grid and a front sub grid; 4-12 front main grids are arranged at equal intervals, with a width of 100-800 μm and a height of 10-40 μm; the back sub-grids, etc. The spacing is set to 90 to 120, the width is 20 to 60 μm, and the height is 10 to 40 μm;

The backside "H" type grid line includes a backside busbar and a backside subgrid; 4-12 backside busbars are arranged at equal intervals, with a width of 100-800 μm and a height of 10-40 μm; the backside subgrids, etc. The pitch is set to 90 to 120, the width is 20 to 60 μm, and the height is 10 to 40 μm.

Optionally, before step (1), the method further includes:

(1)', pre-cleaning the n-type single crystal silicon substrate, removing the mechanical damage layer, and performing alkali texturing treatment to form a pyramid structure, and the thickness of the pyramid structure near one end of the n-type single crystal silicon substrate is 2-5um.

Specifically, the reactive ion etching method of the present invention is a plasma etching technology, which comprehensively utilizes the chemical etching ability of the plasma and the ion kinetic energy of the plasma, and is a synergistic process of the chemical process and the physical process. It uses glow discharge to decompose and ionize gas molecules to generate ionic reactants that can undergo chemical reactions to react with silicon wafers to generate volatile products. The whole process includes the plasma generation by glow discharge, the formation of DC bias, the diffusion and forced convection of reactants, and the processes of absorption, reaction and desorption of reactants on the silicon wafer. It uses a mixed gas of SF ₄ /CL ₂ /O ₂ . The reaction process is mainly divided into the following steps:

1) SF ₄ and Cl ₂ form F ^- and Cl ^- through glow discharge;

2) F ^- and Cl ^- etch silicon to form _Six O _y F _z and _Six O _y Cl _z ;

3) Some ions such as SF _x will sputter the bottom of the etched pit to remove _Six O _y F _z and _{Six O y Cl z} .

Among them, SF ₄ plasma F ^- plays an isotropic role, and Cl ₂ plasma Cl ^- plays an anisotropic role. The atomic density ratio of F/Cl is controlled by adjusting the gas flow ratio of SF ₄ /Cl ₂ , and finally different nanostructures are formed by etching. Compared with the metal-catalyzed chemical etching method, the reactive ion etching (RIE) method of the present invention can control the size of the nanostructures more precisely.

The preparation method of the invention will be described in detail below with specific examples.

Example 1

Step (1)', selecting an N-type crystal n-type single crystal silicon substrate 1, pre-cleaning the N-type crystal n-type single crystal silicon substrate 1, removing the mechanical damage layer, and performing an alkali texturing treatment to form a pyramid structure 2, As shown in Figure 1. Among them, the resistivity of the n-type n-type single crystal silicon substrate 1 is 0.3 Ω·cm, the thickness is 100 μm, and the size of the pyramid structure 2 is 2 μm. The battery structure after this step is completed is shown in FIG. 1 .

In step (1), reactive ion etching is performed on the front surface of the n-type monocrystalline silicon substrate after texturing, so as to form a uniformly distributed nano-scale hole structure 3 on the micron-scale pyramid structure 2; The gas for etching is a mixture of SF ₄ , CL ₂ and O ₂ , the power of reactive ion etching is 100w, the inner diameter of the formed hole is 50nm, the depth is 50nm, and the volume ratio of SF ₄ , CL ₂ and O ₂ is 1 :1:2. The battery structure after this step is completed is shown in FIG. 2 .

Step (2), using the mixed solution of BOE, H ₂ O ₂ and H ₂ O to carry out hole expansion cleaning treatment on the n-type single crystal silicon substrate after the reactive ion etching process, so as to remove the residues generated during the reactive ion etching process The damaged layer formed by the bombardment of objects and ions, and the nano-scale hole structure 3 is subjected to hole expansion treatment.

In step (3.1), double-sided boron diffusion is performed on the n-type single crystal silicon substrate after hole expansion to form a front p+ emitter 4 and a rear p+ emitter 4 . Among them, the boron source for boron diffusion is boron paste, the diffusion temperature is 950°C, and the diffusion square resistance is 70Ω/sq. The battery structure after this step is completed is shown in FIG. 3 .

Step (3.2), using the mixed solution of HF/HNO ₃ /H ₂ SO ₄ to etch the back surface of the n-type single crystal silicon substrate to remove the p+ emitter 4 on the back side, and to form a flat topography on the back surface of the n-type single crystal silicon substrate 5; wherein, the volume ratio of HF, HNO ₃ and H ₂ SO ₄ is 3:7:1. The battery structure after this step is completed is shown in FIG. 4 .

Step (3.3), depositing a backside tunneling oxide layer 6 and a backside doped polysilicon layer 7 on the backside of the N-type n-type single crystal silicon substrate 1; wherein, the thickness of the tunneling oxide layer is 0.5 nm, and the thickness of the doped polysilicon layer is 0.5 nm. is 60nm. The battery structure after this step is completed is shown in FIG. 5 .

Step (3.4), depositing a front passivation anti-reflection film 8 on the front of the n-type n-type single crystal silicon substrate 1 using ALD technology, and depositing a backside passivation anti-reflection film 9 on the back side of the n-type single crystal silicon substrate using ALD technology; Among them, the front passivation anti-reflection film 8 is a laminated passivation anti-reflection film of aluminum oxide and silicon nitride, and the back passivation anti-reflection film 9 is a silicon nitride single-layer film. The battery structure after this step is completed is shown in FIG. 6 .

In step (3.5), the front "H" type grid lines 10 are screen-printed on the front side of the n-type single crystal silicon substrate, and sintered, and the back "H" type grid lines 11 are screen printed on the back side of the n-type single crystal silicon substrate. and sintering, the front "H" type grid line 10 is a p+ metal electrode, and the back "H" type grid line 11 is an n+ metal electrode; wherein, the front "H" type grid line includes a front main grid and a front sub grid; so 4 front main grids are arranged at equal intervals, with a width of 100 μm and a height of 10 μm; 90 secondary grids on the back are arranged at equal intervals, with a width of 20 μm and a height of 10 μm; the backside “H” type grid lines include the backside Main grids and rear subgrids; 4 rear main grids are arranged at equal intervals, with a width of 100 μm and a height of 10 μm; 90 rear secondary grids are arranged at equal intervals, with a width of 20 μm and a height of 10 μm. The battery structure after this step is completed is shown in FIG. 7 .

Example 2

Step (1)', selecting an N-type crystal n-type single crystal silicon substrate 1, pre-cleaning the N-type crystal n-type single crystal silicon substrate 1, removing the mechanical damage layer, and performing an alkali texturing treatment to form a pyramid structure 2, As shown in Figure 1. Among them, the resistivity of the n-type n-type single crystal silicon substrate 1 is 1.5 Ω·cm, the thickness is 200 μm, and the size of the pyramid structure 2 is 3 μm. The battery structure after this step is completed is shown in FIG. 1 .

In step (1), reactive ion etching is performed on the front surface of the n-type monocrystalline silicon substrate after texturing, so as to form a uniformly distributed nano-scale hole structure 3 on the micron-scale pyramid structure 2; The gas for etching is a mixture of SF ₄ , CL ₂ and O ₂ , the power of reactive ion etching is 300w, the inner diameter of the formed hole is 100 nm, the depth is 100 nm, and the volume ratio of SF ₄ , CL ₂ and O ₂ is 1 :1:3. The battery structure after this step is completed is shown in FIG. 2 .

Step (2), using the mixed solution of BOE, H ₂ O ₂ and H ₂ O to carry out hole expansion cleaning treatment on the n-type single crystal silicon substrate after the reactive ion etching process, so as to remove the residues generated during the reactive ion etching process The damaged layer formed by the bombardment of objects and ions, and the nano-scale hole structure 3 is subjected to hole expansion treatment.

In step (3.1), double-sided boron diffusion is performed on the n-type single crystal silicon substrate after hole expansion to form a front p+ emitter 4 and a rear p+ emitter. Among them, the boron source of boron diffusion is boron tribromide, the diffusion temperature is 1000°C, and the diffusion square resistance is 100Ω/sq. The battery structure after this step is completed is shown in FIG. 3 .

Step (3.2), using the mixed solution of HF/HNO ₃ /H ₂ SO ₄ to etch the back surface of the n-type single crystal silicon substrate to remove the p+ emitter 4 on the back side, and to form a flat topography on the back surface of the n-type single crystal silicon substrate 5; wherein, the volume ratio of HF, HNO ₃ and H ₂ SO ₄ is 3:7:1. The battery structure after this step is completed is shown in FIG. 4 .

Step (3.3), depositing a backside tunneling oxide layer 6 and a backside doped polysilicon layer 7 on the backside of the N-type n-type single crystal silicon substrate 1; wherein, the thickness of the tunnel oxide layer is 1 nm, and the thickness of the doped polysilicon layer is 100nm. The battery structure after this step is completed is shown in FIG. 5 .

In step (3.4), a front-side passivation anti-reflection film 8 is deposited on the front of the n-type n-type single crystal silicon substrate 1 by ALD technology, and the backside of the n-type single crystal silicon substrate is deposited by ALD technology The backside passivation antireflection film 9; wherein, the frontside passivation antireflection film 8 is a laminated passivation antireflection film of aluminum oxide and silicon nitride, and the backside passivation antireflection film 9 is a silicon nitride single-layer film. The battery structure after this step is completed is shown in FIG. 6 .

In step (3.5), the front "H" type grid lines 10 are screen-printed on the front side of the n-type single crystal silicon substrate, and sintered, and the back "H" type grid lines 11 are screen printed on the back side of the n-type single crystal silicon substrate. and sintering, the front "H" type grid line 10 is a p+ metal electrode, and the back "H" type grid line 11 is an n+ metal electrode; wherein, the front "H" type grid line includes a front main grid and a front sub grid; so 8 front main grids are arranged at equal intervals, with a width of 500 μm and a height of 25 μm; 110 secondary grids on the back are arranged at equal intervals, with a width of 40 μm and a height of 30 μm; the backside “H” type grid lines include the backside Main grids and rear subgrids; 8 rear main grids are arranged at equal intervals, with a width of 500 μm and a height of 25 μm; 110 rear secondary grids are arranged at equal intervals, with a width of 40 μm and a height of 30 μm. The battery structure after this step is completed is shown in FIG. 7 .

Example 3

Step (1)', selecting an N-type crystal n-type single crystal silicon substrate 1, pre-cleaning the N-type crystal n-type single crystal silicon substrate 1, removing the mechanical damage layer, and performing alkali texturing treatment to form a pyramid structure 2, As shown in Figure 1. The resistivity of the n-type n-type single crystal silicon substrate 1 is 2.1 Ω·cm, the thickness is 300 μm, and the size of the pyramid structure 2 is 5 μm. The battery structure after this step is completed is shown in FIG. 1 .

In step (1), reactive ion etching is performed on the front surface of the n-type monocrystalline silicon substrate after texturing, so as to form a uniformly distributed nano-scale hole structure 3 on the micron-scale pyramid structure 2; The etching gas is a mixed gas of SF ₄ , CL ₂ and O ₂ , the power of reactive ion etching is 600w, the inner diameter of the formed hole is 300 nm, the depth is 300 nm, and the volume ratio of SF ₄ , CL ₂ and O ₂ is 1 :1:4. The battery structure after this step is completed is shown in FIG. 2 .

Step (2), using the mixed solution of BOE, H ₂ O ₂ and H ₂ O to carry out hole expansion cleaning treatment on the n-type single crystal silicon substrate after the reactive ion etching process, so as to remove the residues generated during the reactive ion etching process The damaged layer formed by the bombardment of objects and ions, and the nano-scale hole structure 3 is subjected to hole expansion treatment.

In step (3.1), double-sided boron diffusion is performed on the n-type single crystal silicon substrate after hole expansion to form a front p+ emitter 4 and a rear p+ emitter. Among them, the boron source of boron diffusion is boron, the diffusion temperature is 950-1100 ℃, and the diffusion square resistance is 70-150Ω/sq. The battery structure after this step is completed is shown in FIG. 3 .

Step (3.2), using the mixed solution of HF/HNO ₃ /H ₂ SO ₄ to etch the back surface of the n-type single crystal silicon substrate to remove the p+ emitter 4 on the back side, and to form a flat topography on the back surface of the n-type single crystal silicon substrate 5; wherein, the volume ratio of HF, HNO ₃ and H ₂ SO ₄ is 3:7:1. The battery structure after this step is completed is shown in FIG. 4 .

In step (3.3), a backside tunneling oxide layer 6 and a backside doped polysilicon layer 7 are deposited on the backside of the N-type n-type single crystal silicon substrate 1; wherein, the thickness of the tunneling oxide layer is -1.5nm, and the thickness of the doped polysilicon layer is The thickness is 300nm. The battery structure after this step is completed is shown in FIG. 5 .

In step (3.4), a front-side passivation anti-reflection film 8 is deposited on the front of the n-type n-type single crystal silicon substrate 1 by ALD technology, and the backside of the n-type single crystal silicon substrate is deposited by ALD technology The backside passivation antireflection film 9; wherein, the frontside passivation antireflection film 8 is a laminated passivation antireflection film of aluminum oxide and silicon nitride, and the backside passivation antireflection film 9 is a silicon nitride single-layer film. The battery structure after this step is completed is shown in FIG. 6 .

In step (3.5), the front "H" type grid lines 10 are screen-printed on the front side of the n-type single crystal silicon substrate, and sintered, and the back "H" type grid lines 11 are screen printed on the back side of the n-type single crystal silicon substrate. and sintering, the front "H" type grid line 10 is a p+ metal electrode, and the back "H" type grid line 11 is an n+ metal electrode; wherein, the front "H" type grid line includes a front main grid and a front sub grid; so 12 of the front main grids are arranged at equal intervals, with a width of 800 μm and a height of 40 μm; 120 of the rear secondary grids are arranged at equal intervals, with a width of 60 μm and a height of 40 μm; the “H” type grid lines on the back side include the backside Main grid and rear sub-grids; 12 rear main grids are arranged at equal intervals, with a width of 800 μm and a height of 40 μm; The battery structure after this step is completed is shown in FIG. 7 .

Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, not to limit the protection scope of the present invention. Although the present invention has been described in detail with reference to the preferred embodiments, those of ordinary skill in the art should understand that , the technical solutions of the present invention may be modified or equivalently replaced without departing from the spirit and scope of the technical solutions of the present invention.

Claims (10)

1. a preparation method of a black silicon passivation contact cell based on reactive ion etching, is characterized in that: comprise the following steps: (1), perform reactive ion etching on the front surface of the n-type single crystal silicon substrate after texturing, so as to form a nano-scale hole structure on the micron-scale pyramid structure; (2), cleaning the n-type single crystal silicon substrate processed in step (1) to remove the residues produced in the reactive ion etching process and the damaged layer formed by ion bombardment, and to expand the nano-scale hole structure deal with; (3), performing post-processing on the n-type single crystal silicon substrate processed in step (2). 2. preparation method according to claim 1, is characterized in that, in step (1), The gas for reactive ion etching is a mixed gas of SF ₄ , CL ₂ and O ₂ , and the power of reactive ion etching is 100-600w; wherein, the volume ratio of SF ₄ , CL ₂ and O ₂ is 1:1:2- 1:1:4. 3. preparation method according to claim 1, is characterized in that, in step (1), The inner diameter of the nanoscale hole structure is 50-300 nm, and the depth is 50-300 nm. 4. preparation method according to any one of claim 1-3, is characterized in that, in step (2), The n-type single crystal silicon substrate treated in step (1) is cleaned with a mixed solution of BOE, H ₂ O ₂ and H ₂ O. The cleaning temperature is 20-25° C. and the cleaning time is 30-3000 s. 5. preparation method according to claim 3, is characterized in that, in step (2), In the mixed solution of BOE, H ₂ O ₂ and H ₂ O, the volume ratio of BOE, H ₂ O ₂ and H ₂ O is 1:2:5. 6. The preparation method according to any one of claims 1-3, wherein in step (3), the post-processing of the n-type single crystal silicon substrate processed in step (2) comprises: (3.1) Doping the n-type single crystal silicon substrate processed in step (2) with boron to form a front p+ emitter and a back p+ emitter; (3.2), the backside of the n-type single crystal silicon substrate is etched with an acidic solution to remove the p+ emitter on the backside, and a flat morphology is formed on the backside of the n-type single crystal silicon substrate; (3.3), prepare the backside tunneling oxide layer and the backside doped polysilicon layer on the backside of the n-type single crystal silicon substrate; (3.4), prepare a front passivation anti-reflection film on the front of the n-type single crystal silicon substrate, and prepare a back passivation anti-reflection film on the back of the n-type single crystal silicon substrate; (3.5) Prepare front "H" type grid lines on the front side of the n-type single crystal silicon substrate, and prepare back "H" type grid lines on the back side of the n-type single crystal silicon substrate. 7. preparation method according to claim 6, is characterized in that, in step (3.1), The n-type single crystal silicon substrate treated in step (2) is doped with boron by means of boron diffusion, the boron source for boron diffusion is boron tribromide or boron paste, the diffusion temperature is 950-1100°C, and the diffusion resistance is 70～150Ω/sq. 8. preparation method according to claim 6, is characterized in that, in step (3.2), A mixed solution of HF/HNO ₃ /H ₂ SO ₄ is used to etch the back of the n-type single crystal silicon substrate. After the etching is completed, the weight of the n-type single crystal silicon substrate is reduced by 0.4-0.8 g; among them, HF, HNO ₃ and H The volume ratio of _2SO4 is ₃ :7:1. 9. preparation method according to claim 6, is characterized in that, in step (3.5), The front "H" type grid line includes a front main grid and a front sub grid; 4-12 front main grids are arranged at equal intervals, with a width of 100-800 μm and a height of 10-40 μm; the back sub-grids, etc. The spacing is set to 90 to 120, the width is 20 to 60 μm, and the height is 10 to 40 μm; The backside "H" type grid line includes a backside busbar and a backside subgrid; 4-12 backside busbars are arranged at equal intervals, with a width of 100-800 μm and a height of 10-40 μm; the backside subgrids, etc. The pitch is set to 90 to 120, the width is 20 to 60 μm, and the height is 10 to 40 μm. 10. The preparation method according to any one of claims 1-3, characterized in that, before step (1), the method further comprises: (1)', pre-cleaning the n-type single crystal silicon substrate, removing the mechanical damage layer, and performing alkali texturing treatment to form a pyramid structure, and the thickness of the pyramid structure near one end of the n-type single crystal silicon substrate is 2-5um.

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