CN111852397A - An induction heating device for packing - Google Patents
An induction heating device for packing Download PDFInfo
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- CN111852397A CN111852397A CN202010907487.7A CN202010907487A CN111852397A CN 111852397 A CN111852397 A CN 111852397A CN 202010907487 A CN202010907487 A CN 202010907487A CN 111852397 A CN111852397 A CN 111852397A
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- 238000010438 heat treatment Methods 0.000 title claims abstract description 23
- 238000012856 packing Methods 0.000 title claims abstract description 13
- 230000006698 induction Effects 0.000 title claims description 7
- 238000012544 monitoring process Methods 0.000 claims abstract description 21
- 230000008054 signal transmission Effects 0.000 claims abstract description 14
- 238000000605 extraction Methods 0.000 claims abstract description 5
- 239000003129 oil well Substances 0.000 claims abstract description 3
- 239000003990 capacitor Substances 0.000 claims description 220
- 239000013078 crystal Substances 0.000 claims description 8
- 238000004804 winding Methods 0.000 claims description 7
- 239000003921 oil Substances 0.000 abstract description 15
- 230000000694 effects Effects 0.000 abstract description 8
- 238000005086 pumping Methods 0.000 abstract description 7
- 239000010779 crude oil Substances 0.000 abstract description 5
- 238000000034 method Methods 0.000 abstract description 5
- 238000004519 manufacturing process Methods 0.000 abstract description 3
- 230000002035 prolonged effect Effects 0.000 abstract description 2
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- 230000002457 bidirectional effect Effects 0.000 description 13
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- 238000010408 sweeping Methods 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- 238000004018 waxing Methods 0.000 description 1
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- E—FIXED CONSTRUCTIONS
- E21—EARTH OR ROCK DRILLING; MINING
- E21B—EARTH OR ROCK DRILLING; OBTAINING OIL, GAS, WATER, SOLUBLE OR MELTABLE MATERIALS OR A SLURRY OF MINERALS FROM WELLS
- E21B36/00—Heating, cooling or insulating arrangements for boreholes or wells, e.g. for use in permafrost zones
- E21B36/04—Heating, cooling or insulating arrangements for boreholes or wells, e.g. for use in permafrost zones using electrical heaters
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- E—FIXED CONSTRUCTIONS
- E21—EARTH OR ROCK DRILLING; MINING
- E21B—EARTH OR ROCK DRILLING; OBTAINING OIL, GAS, WATER, SOLUBLE OR MELTABLE MATERIALS OR A SLURRY OF MINERALS FROM WELLS
- E21B33/00—Sealing or packing boreholes or wells
- E21B33/02—Surface sealing or packing
- E21B33/03—Well heads; Setting-up thereof
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Abstract
Description
技术领域technical field
本发明属于采油工程的设备保护处理技术的电源电路技术领域，具体涉及一种用于抽油机采油过程中一种保护装置。The invention belongs to the technical field of the power supply circuit of the equipment protection processing technology of the oil extraction project, and particularly relates to a protection device used in the oil extraction process of the oil pumping unit.
背景技术Background technique
我国油田主要分布在高寒冷地区，最低地区零下45度，年平均温度在10度以下，低温环境下原油易凝结，尤其在冬天，对裸露在外面的盘根底部结冻，影响采油输出，原油易结蜡，对于盘根这种结构尚无法进行化蜡，抽油杆与套管之间的损伤较大或卡杆，带来影响产量的不良影响。针对这种问题提出一种加热装置，使原油不结蜡，降低了抽油杆与套管之间的磨损，延长抽油杆的使用寿命，使用这种装置不仅降低热量耗损，同时减少抽油杆与抽油管之间阻力，提高抽油机效率，降低功耗。my country's oil fields are mainly distributed in high and cold areas, the lowest area is
发明内容SUMMARY OF THE INVENTION
针对现有的原有技术存在上述不足，本发明提供一种使用效果好的加热电源装置。本发明一种用于油田盘根加热电源，属于油井采油过程中的一种保护装置。其特征在于，其装置主要包括，电源电路和加热体两大部分，加热体由抽油杆（１）、油管（２）、高频线（３）按照（４）方向缠绕、绕在固定高温外壳（５）上、接线之间的连接由大功率快接高温插头（９）相连、磁力线方向按（６）方向分布，电流方向按照（７）和（８）方向，构成整个的加热体。Aiming at the above-mentioned shortcomings of the existing prior art, the present invention provides a heating power supply device with good use effect. The invention relates to a heating power source for oil field packing, which belongs to a protection device in the process of oil extraction of oil wells. It is characterized in that the device mainly includes two parts: a power supply circuit and a heating body. The connection between the wiring on the shell (5) is connected by a high-power quick-connect high-temperature plug (9), the direction of the magnetic force line is distributed in the direction of (6), and the direction of the current is in the direction of (7) and (8) to form the entire heating body.
其装置主要包括，电源电路、高频线、固定高温外壳、大功率快接高温插头，以上各种单元连接起来和其它辅助设备盘根加热装置。采油井在工作过程中，尤其在冬天，对裸露在外面的盘根内部产生热能，使原油不结蜡，降低了抽油杆与套管之间的磨损，延长抽油杆的使用寿命，使用这种装置不仅降低热量耗损，同时减少抽油杆与抽油管之间阻力，提高抽油机效率，降低功耗。The device mainly includes a power circuit, a high-frequency line, a fixed high-temperature casing, a high-power quick-connect high-temperature plug, and the above various units are connected together with other auxiliary equipment packing heating devices. During the working process of the oil production well, especially in winter, heat energy is generated inside the exposed packing, so that the crude oil does not form wax, the wear between the sucker rod and the casing is reduced, and the service life of the sucker rod is prolonged. This device not only reduces heat loss, but also reduces the resistance between the sucker rod and the sucker pipe, improves the efficiency of the pumping unit, and reduces the power consumption.
本发明就是针对上述问题，提供一种使用效果好的感应加热电源电路。为实现上述目的，本发明采用如下技术方案，本发明包括主处理器、FPGA、功率主电路、电流采集部分、RS485总线第一监听部分、RS485总线第二监听部分和驱动电路，其特征在于驱动电路的控制信号输入端口与主处理器的控制信号输出端口相连，驱动电路的信号传输端口与FPGA的信号传输端口相连，驱动电路的控制信号输出端口与功率主电路的控制信号输入端口相连；The present invention is aimed at the above problems, and provides an induction heating power supply circuit with good use effect. In order to achieve the above-mentioned purpose, the present invention adopts the following technical scheme. The present invention comprises a main processor, an FPGA, a power main circuit, a current acquisition part, a first monitoring part of the RS485 bus, a second monitoring part of the RS485 bus and a driving circuit. The control signal input port of the circuit is connected with the control signal output port of the main processor, the signal transmission port of the drive circuit is connected with the signal transmission port of the FPGA, and the control signal output port of the drive circuit is connected with the control signal input port of the power main circuit;
电流采集部分的信号传输端口与FPGA的信号传输端口相连；The signal transmission port of the current acquisition part is connected with the signal transmission port of the FPGA;
RS485总线第一监听部分的信号输入端口与驱动电路的信号输出端口相连；The signal input port of the first monitoring part of the RS485 bus is connected with the signal output port of the drive circuit;
RS485总线第二监听部分的信号输入端口与驱动电路的信号输出端口相连；The signal input port of the second monitoring part of the RS485 bus is connected with the signal output port of the drive circuit;
功率主电路的电能输入端接单相市电。The power input terminal of the main power circuit is connected to the single-phase commercial power.
作为一种优选方案，本发明所述主处理器采用STM32H743IIT6 ARM处理器U5，U5的158、148、135、126、113、102、90、71、61、22、14脚接地，U5的172、159、149、136、127、114、103、91、82、72、62、49、36、23、15接+3.3V；As a preferred solution, the main processor of the present invention adopts STM32H743IIT6 ARM processor U5,
MPM-20-12芯片U55的1脚接UU9.8共模电感L5的2脚，L5的1脚分别与变阻器R299一端、保险丝F1一端相连，F1另一端接L，R299另一端分别与N、L5的3脚相连，L5的4脚接U55的2脚，U55的3脚分别与电容C203一端、电容C204正极、+12V相连，C203另一端分别与U55的4脚、C204负极、GND相连；
电阻R2一端接U5_BOOT0，R2另一端接GND；One end of resistor R2 is connected to U5_BOOT0, and the other end of R2 is connected to GND;
SP3485芯片U60的1脚接U5_PA3，U60的2、3脚接U5_PA1，U60的4脚接U5_PA2，U60的5～8脚分别与GND、A、B、+3.3V对应相连，电阻R290分别与B、GND相连，电阻R291分别与A、+3.3V相连；
SP3485芯片U64的1脚接U5_PA10，U64的2、3脚接U5_PA8，U64的4脚接U5_PA92，U64的5、6、7、8脚分别与GND、A、B、+3.3V对应相连，电阻R292分别与B、GND相连，电阻R293分别与A、+3.3V相连；
SP3485芯片U63的1脚接U5_PA10，U63的2、3脚接U5_PA8，U63的4脚接U5_PA9，U63的5、6、7、8脚分别与GND、A、B、+3.3V对应相连，电阻R294分别与B、GND相连，电阻R295分别与A、+3.3V相连；
电容C85、C69～C82并联接在+3.3V、GND之间；Capacitors C85, C69~C82 are connected in parallel between +3.3V and GND;
+3.3V通过电阻R24分别与RESET、电容C84一端、开关SW1一端相连，C84另一端分别与GND、SW1另一端相连；+3.3V is connected to RESET, one end of capacitor C84 and one end of switch SW1 through resistor R24 respectively, and the other end of C84 is connected to GND and the other end of SW1 respectively;
SD8942/A6166芯片U19的1脚通过电容C19分别与U19的6脚、电感L3一端相连，L3另一端分别与+5V、电阻R206一端相连，R206另一端分别与电阻R205一端、U19的3脚相连，R205另一端分别与GND、U19的2脚相连，U19的4脚通过电阻R204分别与U19的5脚、+12V、电容C22一端、电容C23一端、电容C24一端相连，C22另一端分别与C23另一端、C24另一端、GND相连；
4脚接插件P3的1脚接GND，P3的3脚分别与U5_JTMS、电阻R19一端相连，R19另一端接+3.3V，P3的2脚分别与U5_JTCK、电阻R22一端相连，R22另一端接GND，P3的1脚接GND；The 1-pin of the 4-pin connector P3 is connected to GND, the 3-pin of P3 is connected to one end of U5_JTMS and resistor R19, the other end of R19 is connected to +3.3V, the 2-pin of P3 is connected to U5_JTCK and one end of resistor R22, and the other end of R22 is connected to GND ,
晶振Y1的4脚接GND，Y1的1脚分别与U5_OSC_OUT、电容C67一端相连，C67另一端分别与GND、Y1的2脚、电容C68一端相连，C68另一端分别与Y1的3脚、U5_OSC_IN相连；The 4th pin of the crystal oscillator Y1 is connected to GND, the 1st pin of Y1 is connected to U5_OSC_OUT and one end of the capacitor C67, the other end of C67 is connected to GND, the 2nd pin of Y1, and the other end of the capacitor C68, and the other end of C68 is connected to the 3rd pin of Y1 and U5_OSC_IN respectively. ;
晶振Y2的一端分别与电容C66一端、U5_OSC32_IN相连，C66另一端分别与GND、电容C83一端相连，C83另一端分别与Y2的另一端、U5_OSC32_OUT相连。One end of crystal oscillator Y2 is connected to one end of capacitor C66 and U5_OSC32_IN respectively, the other end of C66 is connected to GND and one end of capacitor C83 respectively, and the other end of C83 is connected to the other end of Y2 and U5_OSC32_OUT respectively.
作为另一种优选方案，本发明U5的171脚通过电阻R5分别与U5的37脚、电容C43一端、C44一端、GND相连，C43另一端分别与U5的39脚、C44另一端、电阻R4一端相连，R4另一端接+3.3V；As another preferred solution, in the present invention,
U5的125脚通过电容C41分别与GND、电容C39一端相连，C39另一端接U5的81脚；
U5的38脚分别与+3.3V、电容C40一端相连，C40另一端接GND；
U5的6脚分别与+3.3V、电容C36一端相连，C36另一端分别与GND、电阻R8一端相连，R8另一端接U5的48脚；
U5的166脚接U5_BOOT0；U5 pin 166 is connected to U5_BOOT0;
U5的31脚接RESET。
作为另一种优选方案，本发明所述FPGA采用EP4CE10F17C8芯片U22的H7～10、J7～10、B2、B15、C5、C12、D7、D10、E4、E13脚接GND，U22的G4、G13、K4、K13、M4、M13、N7、N10、P5、P12、R2、R15、E2、H16、H15脚接GND；As another preferred solution, the FPGA of the present invention uses the H7~10, J7~10, B2, B15, C5, C12, D7, D10, E4, E13 pins of the EP4CE10F17C8 chip U22 to connect to GND, and the G4, G13, K4, K13, M4, M13, N7, N10, P5, P12, R2, R15, E2, H16, H15 pins are connected to GND;
HT7550-1芯片VR1的Vin脚分别与电容C31、C32、C53、+5V相连，C31另一端分别与GND、C32另一端、C53另一端、VR1的GND脚、电容C33～38一端、电容C42一端、电容C45～49一端相连，电容C33另一端分别与VR1的Vout脚、C34～38另一端、电容C42另一端、电容C45～49另一端、+3.3V相连；The Vin pin of HT7550-1 chip VR1 is connected to capacitors C31, C32, C53, +5V respectively, the other end of C31 is connected to GND, the other end of C32, the other end of C53, the GND pin of VR1, one end of capacitors C33~38, and one end of capacitor C42 , One end of capacitor C45~49 is connected, the other end of capacitor C33 is connected to Vout pin of VR1, the other end of C34~38, the other end of capacitor C42, the other end of capacitor C45~49, +3.3V;
HT7550-1芯片VR2的Vin脚分别与电容C50一端、电容C51一端、电容C55一端、+3.3V相连，C50另一端分别与GND、电容C51另一端、电容C55另一端、VR2的GND脚、电容C52负极、电容C56一端相连，C52正极分别与VR2的Vout脚、C56另一端、+1.2V相连；The Vin pin of HT7550-1 chip VR2 is connected to one end of capacitor C50, one end of capacitor C51, one end of capacitor C55, and +3.3V respectively. The negative electrode of C52 and one end of capacitor C56 are connected, and the positive electrode of C52 is connected to the Vout pin of VR2, the other end of C56, and +1.2V respectively;
HT7550-1芯片VR3的Vin脚分别与电容C61～63一端、+5V相连，C61～63另一端分别与GND、VR3的GND脚、电容C65负极、电容C86一端、电容C88一端、电容C89一端、电容C93一端相连，C65正极分别与VR3的Vout脚、电容C86另一端、电容C88另一端、电容C89另一端、电容C93另一端、+2.5V相连；The Vin pin of HT7550-1 chip VR3 is connected to one end of capacitors C61~63 and +5V respectively, the other end of C61~63 is respectively connected to GND, the GND pin of VR3, the negative electrode of capacitor C65, one end of capacitor C86, one end of capacitor C88, one end of capacitor C89, One end of capacitor C93 is connected, and the positive electrode of C65 is connected to the Vout pin of VR3, the other end of capacitor C86, the other end of capacitor C88, the other end of capacitor C89, the other end of capacitor C93, and +2.5V;
SP3485芯片U65的1脚接B4，U65的2、3脚接D5，U65的4脚接D6；U65的5、6、7、8脚分别与GND、A、B、+3.3V对应相连，电阻R275分别与B、GND相连，电阻R2765分别与A、+3.3V相连。The 1 pin of U65 of SP3485 chip is connected to B4, the 2 and 3 pins of U65 are connected to D5, and the 4 pin of U65 is connected to D6; R275 is connected to B and GND respectively, and resistor R2765 is connected to A and +3.3V respectively.
作为另一种优选方案，本发明U22的L5脚接+2.5V，U22的N4脚接+1.2V，U22的F12脚接+2.5V，U22的D13脚接+1.2V，U22的E12、M5脚接GND；As another preferred solution, the L5 pin of U22 is connected to +2.5V, the N4 pin of U22 is connected to +1.2V, the F12 pin of U22 is connected to +2.5V, the D13 pin of U22 is connected to +1.2V, the E12 and M5 of U22 The pin is connected to GND;
U22的H4脚通过电阻R121分别与+2.5V、电阻R131一端、U22的H12脚相连，U22的H3脚通过电阻R128接GND，R131另一端接U22的J5脚；The H4 pin of U22 is connected to +2.5V, one end of the resistor R131, and the H12 pin of U22 through the resistor R121 respectively. The H3 pin of U22 is connected to GND through the resistor R128, and the other end of R131 is connected to the J5 pin of U22;
U22的H13脚分别与U22的G12脚、GND、电阻R241一端相连，R241另一端接U22的J3脚；The H13 pin of U22 is connected to the G12 pin, GND, and one end of the resistor R241 of U22 respectively, and the other end of R241 is connected to the J3 pin of U22;
U22的H14脚通过电阻R252接+3.3V，U22的H5脚通过电阻R253接+3.3V，U22的F4脚通过电阻R254接+3.3V；Pin H14 of U22 is connected to +3.3V through resistor R252, pin H5 of U22 is connected to +3.3V through resistor R253, and pin F4 of U22 is connected to +3.3V through resistor R254;
JTAG-10-FPGA接口JTAG1的2、10脚接GND，JTAG1的4脚接+2.5V；JTAG-10-FPGA
U22的E3、G3、K3、M3、P4、P7、T1、P10、P13、T16、K14、M14、E14、G14、A16、C10、C13、A1、C4、C7脚接+3.3V，U22的G6～G10、H6、H11、K7脚接+1.2V；U22's E3, G3, K3, M3, P4, P7, T1, P10, P13, T16, K14, M14, E14, G14, A16, C10, C13, A1, C4, C7 pins are connected to +3.3V, U22's G6 ～G10, H6, H11, K7 pins are connected to +1.2V;
晶振XTAL1的2脚接GND，XTAL1的3脚接CLK_1，XTAL1的4脚接+3.3V；The 2-pin of the crystal oscillator XTAL1 is connected to GND, the 3-pin of XTAL1 is connected to CLK_1, and the 4-pin of XTAL1 is connected to +3.3V;
M25P16芯片U30的6、5、2、8脚分别与EPCS_CLK、EPCS_ASDO、EPCS_DATA0、+3.3V对应相连，U30的4脚接GND，U30的3、7脚接+3.3V，U30的1脚接EPCS_CS。
作为另一种优选方案，本发明所述功率主电路包括空气开关K1，K1一端与市电相连，K1另一端与变压器T1原边相连，T1第一副边一端分别与二极管D1阴极、IGBT Q2的漏极、Q2_D相连，D1的阳极分别与IGBT Q1的源极、Q1_S相连，Q1的门极接Q1_B，Q1的漏极分别与Q1_D、二极管D2阴极、共模电感L2的1脚相连，D2阳极分别与Q2的源极、Q2_S相连，Q2的门极接Q2_B，L2的3脚接T1第一副边另一端；As another preferred solution, the power main circuit of the present invention includes an air switch K1, one end of K1 is connected to the mains, the other end of K1 is connected to the primary side of the transformer T1, and one end of the first secondary side of T1 is respectively connected to the cathode of the diode D1 and the IGBT Q2 The drain of IGBT is connected to Q2_D, the anode of D1 is connected to the source of IGBT Q1 and Q1_S respectively, the gate of Q1 is connected to Q1_B, the drain of Q1 is connected to Q1_D, the cathode of diode D2, and the 1 pin of common mode inductor L2 respectively, D2 The anode is connected to the source of Q2 and Q2_S respectively, the gate of Q2 is connected to Q2_B, and the 3-pin of L2 is connected to the other end of the first secondary side of T1;
L2的2脚分别与二极管D5阳极、二极管D7阴极相连，D5阴极分别与二极管D6阴极、电感L1一端相连，L1另一端分别与电容C6一端、NPN三极管Q3集电极相连，Q3基极接Q3_B，Q3发射极分别与Q3_S、电容C1～C4一端、IGBT Q4漏极、IGBT Q5漏极相连，C1～C4另一端分别与电容C9～C12一端、Q4源极、Q4_S、IGBT Q6漏极、主变压器T2原边一端相连，T2原边另一端分别与电容C7一端、电容C8一端、电容C13一端、电容C14一端、电容C5一端相连，电容C7另一端、电容C8另一端、电容C13另一端、电容C14另一端、电容C5另一端分别与Q5_S、Q5源极、IGBTQ7漏极相连，Q7源极分别与PGND、Q6源极、电容C9～C12另一端、C6另一端、D7阳极、二极管D8阳极相连，D8阴极分别与L2的4脚、D6阳极相连；
T2第一副边一端分别与电容C110～C115一端相连，C110～C115另一端接二脚接插件P8的1脚，P8的2脚通过电流互感器T3原边接T2第一副边另一端。One end of the first secondary side of T2 is respectively connected to one end of capacitors C110~C115, the other end of C110~C115 is connected to the 1st pin of the two-pin connector P8, and the 2nd pin of P8 is connected to the other end of the first secondary side of T2 through the primary side of the current transformer T3.
作为另一种优选方案，本发明所述电流采集部分包括可调基准源控制电路、线性驱动电路、电压基准阵列和电压比较器阵列，可调基准源控制电路的输出端口与电压基准阵列的输入端口相连，电压基准阵列的输出端分别与电压比较器阵列的输入端、FPGA相连，线性驱动电路的输出端口与电压比较器阵列的输入端相连。As another preferred solution, the current acquisition part of the present invention includes an adjustable reference source control circuit, a linear drive circuit, a voltage reference array and a voltage comparator array, the output port of the adjustable reference source control circuit and the input of the voltage reference array The ports are connected, the output ends of the voltage reference array are respectively connected with the input end of the voltage comparator array and the FPGA, and the output port of the linear drive circuit is connected with the input end of the voltage comparator array.
作为另一种优选方案，本发明所述可调基准源控制电路包括AD/DC_POW芯片U44，U44的1脚接市电L，U44的2脚接市电N，U44的3脚分别与+15VA、电容C126一端、电容C127正极、电阻R307一端、NPN三极管Q17集电极相连，R307另一端分别与Q17基极、光耦OP3输出端集电极相连，光耦OP3输出端发射极分别与电容C126另一端、电容C127负极、U44的4脚、电阻R309一端、GND相连；Q17发射极通过电阻R308分别与电阻R309另一端、VRE_1相连；As another preferred solution, the adjustable reference source control circuit of the present invention includes an AD/DC_POW chip U44.
OP3输入端阳极分别与电阻R305一端、电阻R306一端相连，R305另一端分别与电容C123正极、电容C122一端、+15VA相连，C122另一端分别与GND、C123负极、TL431芯片U46的2脚、X9C103芯片U45的3脚、U45的4脚、电容C124一端、电容C125一端相连；C124、C125另一端接U45的8脚、+3.3V，U45的7、2、1脚分别与J12、J14、J15对应相连；U45的5脚分别与U46的1脚、R306另一端相连，U46的3脚接OP3输入端阴极。The anode of OP3 input terminal is connected to one end of resistor R305 and one end of resistor R306 respectively. The other end of R305 is connected to the positive pole of capacitor C123, one end of capacitor C122 and +15VA respectively.
作为另一种优选方案，本发明所述电压基准阵列包括电阻R10，R10一端接VRE_1，R10另一端依次通过电阻、R15～R17、R25、R30～R32、R37、R42～R44、R49、R54～R56、R61、R66、R67、R68、R73、R78～80、R85、R90～92、R97、R102～104、R109、R110、R115、R116、R122、R123、R129、R130、R136、R137、R142、R143、R148、R149、R154、R155、R160、R161、R166、R167、R172、R173、R178、R179、R184、R185、R190、R191、R196、R197、R202、R203接X9C103芯片U18的5脚，U18的3脚分别与GND、V、RE_1、U18的4脚、电容C20一端、电容C21一端相连，C20另一端分别与+3.3V、U18的8脚、C21另一端相连，U18的7、2、1分别与L6、K6、J6对应相连。As another preferred solution, the voltage reference array of the present invention includes a resistor R10, one end of R10 is connected to VRE_1, and the other end of R10 passes through the resistor, R15~R17, R25, R30~R32, R37, R42~R44, R49, R54~ R56, R61, R66, R67, R68, R73, R78～80, R85, R90～92, R97, R102～104, R109, R110, R115, R116, R122, R123, R129, R130, R136, R137, R142, R143, R148, R149, R154, R155, R160, R161, R166, R167, R172, R173, R178, R179, R184, R185, R190, R191, R196, R197, R202, R203 connect to pin 5 of X9C103 chip U18, U18 The 3-pin of GND, V, RE_1,
作为另一种优选方案，本发明所述电压比较器阵列包括MAX9140芯片U1、U2、U3、U4、U5、U6、U7、U8、U9、U10、U11、U12、U13、U14、U15、U16、U17，U1～U17的4脚分别与电容C17正极、电容C18一端、+5V相连，U1～U17的11脚分别与电容C17负极、电容C18另一端、GND相连；As another preferred solution, the voltage comparator array of the present invention includes MAX9140 chips U1, U2, U3, U4, U5, U6, U7, U8, U9, U10, U11, U12, U13, U14, U15, U16, U17, U1~U17 pins 4 are respectively connected to the positive pole of capacitor C17, one end of capacitor C18, +5V, and 11 pins of U1~U17 are respectively connected to the negative pole of capacitor C17, the other end of capacitor C18, and GND;
U1～U17的3、5、12、10脚接ADC0，U1～U17的9脚分别与V15、V30～V16对应连接，U1～U17的13脚分别与V31、V14～V0对应连接，U1～U17的6脚分别与V47～V32对应连接，U1～U17的2脚分别与V 63～V 48对应连接；
U1～U17的8脚分别通过1K电阻与K2、F3、D2、D1、G5、F2、F1、G2、G1、G16、G15、F13、F16、F15、B16、F14对应连接，K2、F3、D2、D1、G5、F2、F1、G2、G1、G16、G15、F13、F16、F15、B16、F14分别通过2K电阻接GND；The 8 pins of U1~U17 are respectively connected with K2, F3, D2, D1, G5, F2, F1, G2, G1, G16, G15, F13, F16, F15, B16, F14 through 1K resistors, K2, F3, D2 , D1, G5, F2, F1, G2, G1, G16, G15, F13, F16, F15, B16, F14 are respectively connected to GND through 2K resistors;
U1～U17的14脚分别通过1K电阻与C2、K1、L2、L1、L3、N2、N1、K5、L4、R1、P2、P1、D4、E5、F5、B1对应连接，C2、K1、L2、L1、L3、N2、N1、K5、L4、R1、P2、P1、D4、E5、F5、B1分别通过2K电阻接GND；The 14 pins of U1~U17 are respectively connected with C2, K1, L2, L1, L3, N2, N1, K5, L4, R1, P2, P1, D4, E5, F5, B1 through 1K resistors, C2, K1, L2 , L1, L3, N2, N1, K5, L4, R1, P2, P1, D4, E5, F5, B1 are respectively connected to GND through 2K resistors;
U1～U17的7脚分别通过1K电阻与D16、D15、G11、C16、C15、R9、T9、K9、L9、M9、N9、R10、T10、R11、T11、R12对应连接，D16、D15、G11、C16、C15、R9、T9、K9、L9、M9、N9、R10、T10、R11、T11、R12分别通过2K电阻接GND；The 7 pins of U1~U17 are respectively connected with D16, D15, G11, C16, C15, R9, T9, K9, L9, M9, N9, R10, T10, R11, T11, R12 through 1K resistors, D16, D15, G11 , C16, C15, R9, T9, K9, L9, M9, N9, R10, T10, R11, T11, R12 are connected to GND through 2K resistors respectively;
U1～U17的1脚分别通过1K电阻与T12、K10、L10、P9、P11、R13、T13、M10、N11、T14、T15、R14、P14、L11、M11、N12对应连接，T12、K10、L10、P9、P11、R13、T13、M10、N11、T14、T15、R14、P14、L11、M11、N12分别通过2K电阻接GND。
作为另一种优选方案，本发明线性驱动电路包括MOSFET-N管Q21，Q21的漏极分别与ADC0、稳压管ZD2阴极、二极管D9阴极相连，Q21源极分别与GND、ZD2阴极、电容C16一端、电流互感器T3副边一端相连，T3副边另一端分别与电容C15一端、D9阳极相连，C15另一端分别与C16另一端、FG相连；As another preferred solution, the linear drive circuit of the present invention includes a MOSFET-N tube Q21, the drain of Q21 is respectively connected to ADC0, the cathode of Zener tube ZD2, and the cathode of diode D9, and the source of Q21 is respectively connected to GND, the cathode of ZD2, and the cathode of capacitor C16. One end is connected to one end of the secondary side of the current transformer T3, the other end of the secondary side of T3 is connected to one end of the capacitor C15 and the anode of D9, and the other end of C15 is connected to the other end of C16 and FG respectively;
+15VA分别与电容C121一端、电容C120正极、电阻R304一端相连，R304另一端分别与电阻R303一端、光耦OP2输入端阳极相连，光耦OP2输入端阴极接TL431芯片U43的3脚，U43的2脚分别与GND、电容C121另一端、电容C120负极、X9C103芯片U42的3脚、U42的4脚、电容C99一端、电容C98一端相连，U43的1脚分别与电阻R303另一端、U42的5脚相连，U42的1、2、7脚分别与J13、J2、J1对应相连，U42的8脚分别与电容C99另一端、电容C98另一端相连；+15VA is connected to one end of capacitor C121, the positive electrode of capacitor C120, and one end of resistor R304 respectively. The other end of R304 is connected to one end of resistor R303 and the anode of the input end of optocoupler OP2. The cathode of the input end of optocoupler OP2 is connected to pin 3 of U43 of the TL431 chip, and the
L接AD/DC_POW芯片U41的1脚，U41的2脚接N，U41的3脚分别与+15VA、电容C97一端、电容C96正极、电阻R302一端、NPN三极管Q16集电极相连，R302另一端分别与Q16基极、OP2输出端集电极相连，OP2输出端发射极分别与U41的4脚、C97另一端、C96负极、电阻R300一端、GND相连，R300另一端分别与Q21_G、电阻R301一端相连，电阻R301另一端接Q16的发射极。L is connected to pin 1 of AD/DC_POW chip U41,
作为另一种优选方案，本发明驱动电路包括KP103芯片U21、 U28、 U36、 U38，U21的4脚接+15V、U21的5脚接GND、U21的2脚分别与电阻R214一端、电容C26一端相连，C26另一端分别与R214另一端、+15V相连，U21的3脚接S8050三极管Q9集电极相连，Q9基极分别与电阻R222一端、电阻R223一端相连，R222另一端接A3，R223另一端分别与GND、Q9发射极相连；U21的13脚通过电阻R224接光耦U26输入端阴极，U26输入端阳极接U21的18脚，U26输出端发射极接A8，U26输出端集电极接+3.3V，U21的17脚分别与电阻R213一端、双向稳压二极管ZD4一端、Q4_S相连，U21的16、15脚接电阻R212一端，R212另一端分别与R213另一端、ZD4另一端、Q4_B相连，U21的12脚通过稳压二极管接二极管D11阳极，D11阴极接Q3_S；As another preferred solution, the drive circuit of the present invention includes KP103 chips U21, U28, U36, and U38.
U28的4脚接+15V、U28的5脚接GND、U28的2脚分别与电阻R233一端、电容C57一端相连，C57另一端分别与R233另一端、+15V相连，U28的3脚接S8050三极管Q12集电极相连，Q12基极分别与电阻R238一端、电阻R239一端相连，R238另一端接B3，R239另一端分别与GND、Q12发射极相连；U28的13脚通过电阻R240接光耦U32输入端阴极，U32输入端阳极接U28的18脚，U32输出端发射极接B8，U32输出端集电极接+3.3V，U28的17脚分别与电阻R232一端、双向稳压二极管ZD6一端、Q5_S相连，U28的16、15脚接电阻R230一端，R230另一端分别与R232另一端、ZD6另一端、Q5_B相连，U28的12脚通过稳压二极管接二极管D13阳极，D13阴极接Q3_S；
U36的4脚接+15V、U36的5脚接GND、U36的2脚分别与电阻R246一端、电容C64一端相连，C64另一端分别与R246另一端、+15V相连，U36的3脚接S8050三极管Q13集电极相连，Q13基极分别与电阻R248一端、电阻R247一端相连，R247另一端接C3，R248另一端分别与GND、Q13发射极相连；U36的13脚通过电阻R249接光耦U37输入端阴极，U37输入端阳极接U36的18脚，U37输出端发射极接C8，U37输出端集电极接+3.3V，U36的17脚分别与电阻R245一端、双向稳压二极管ZD7一端、PGND相连，U36的16、15脚接电阻R244一端，R244另一端分别与R245另一端、ZD7另一端、Q6_B相连，U36的12脚通过稳压二极管接二极管D14阳极，D14阴极接Q4_S；
U38的4脚接+15V、U38的5脚接GND、U38的2脚分别与电阻R261一端、电容C87一端相连，C87另一端分别与R261另一端、+15V相连，U38的3脚接S8050三极管Q14集电极相连，Q14基极分别与电阻R265一端、电阻R266一端相连，R265另一端接D3，R266另一端分别与GND、Q14发射极相连；U38的13脚通过电阻R267接光耦U40输入端阴极，U40输入端阳极接U38的18脚，U40输出端发射极接D8，U40输出端集电极接+3.3V，U38的17脚分别与电阻R260一端、双向稳压二极管ZD8一端、PGND相连，U38的16、15脚接电阻R259一端，R259另一端分别与R260另一端、ZD8另一端、Q7_B相连，U38的12脚通过稳压二极管接二极管D15阳极，D15阴极接Q5_S。
作为另一种优选方案，本发明所述驱动电路包括KP103芯片U20、U27，U20的4脚接+15V、U20的5脚接GND、U20的2脚分别与电阻R211一端、电容C25一端相连，C25另一端分别与R211另一端、+15V相连，U20的3脚接S8050三极管Q8集电极相连，Q8基极分别与电阻R217一端、电阻R218一端相连，R217另一端接U33_PA6，R218另一端分别与GND、Q8发射极相连；U20的13脚通过电阻R219接光耦U25输入端阴极，U25输入端阳极接U20的18脚，U25输出端发射极接U33_PA7，U25输出端集电极接+3.3V，U20的17脚分别与电阻R210一端、双向稳压二极管ZD3一端、Q2_S相连，U20的16、15脚接电阻R209一端，R209另一端分别与R210另一端、ZD3另一端、Q2_B相连，U20的12脚通过稳压二极管接二极管D10阳极，D10阴极接Q2_D；As another preferred solution, the drive circuit of the present invention includes KP103 chips U20 and U27. The 4th pin of U20 is connected to +15V, the 5th pin of U20 is connected to GND, and the 2nd pin of U20 is respectively connected to one end of the resistor R211 and one end of the capacitor C25. The other end of C25 is connected to the other end of R211 and +15V respectively, the 3-pin of U20 is connected to the collector of S8050 transistor Q8, the base of Q8 is connected to one end of resistor R217 and one end of resistor R218 respectively, the other end of R217 is connected to U33_PA6, the other end of R218 is connected to GND and Q8 emitter are connected; pin 13 of U20 is connected to the cathode of the optocoupler U25 input through resistor R219, the anode of U25 input is connected to pin 18 of U20, the emitter of U25 output is connected to U33_PA7, the collector of U25 output is connected to +3.3V,
U27的4脚接+15V、U27的5脚接GND、U27的2脚分别与电阻R229一端、电容C54一端相连，C54另一端分别与R229另一端、+15V相连，U27的3脚接S8050三极管Q11集电极相连，Q11基极分别与电阻R234一端、电阻R235一端相连，R234另一端接U33_PA4，R235另一端分别与GND、Q11发射极相连；U27的13脚通过电阻R236接光耦U31输入端阴极，U31输入端阳极接U27的18脚，U31输出端发射极接U33_PA5，U31输出端集电极接+3.3V，U27的17脚分别与电阻R228一端、双向稳压二极管ZD5一端、Q1_S相连，U27的16、15脚接电阻R225一端，R225另一端分别与R228另一端、ZD5另一端、Q1_B相连，U27的12脚通过稳压二极管接二极管D12阳极，D12阴极接Q1_D；
STM32F030F4芯片U33的12脚接U33_PA6，STM32F030F4芯片U33的13脚接U33_PA7，STM32F030F4芯片U33的10脚接U33_PA4，STM32F030F4芯片U33的11脚接U33_PA5；
U33的1脚通过电阻R250接GND，四脚接插件P5的1脚分别与+3.3V、电容C90一端相连，C90另一端分别与GND、P5的4脚相连，P5的2、3脚分别与U33的19、20脚对应相连；
电容C100～104并联在+3.3V与GND之间。Capacitors C100-104 are connected in parallel between +3.3V and GND.
作为另一种优选方案，本发明所述驱动电路包括X9C103芯片U24，U24的5脚分别与电阻R208一端、TL431芯片U23的1脚相连，R208另一端分别与电阻R207一端、光耦OP1输入端阳极相连，OP1输入端阴极接U23的3脚，U23的2脚分别与GND、电容C27、电容C28负极、U24的3脚、U23的2脚、U24的4脚、电容C29一端、电容C30一端相连，U24的8脚分别与+3.3V、电容C29另一端、电容C30另一端相连，U24的1、2、7脚分别与U34_PA4、U34_PA5、U34_PA6对应连接，+15V分别与C27另一端、C28另一端、R207另一端相连；As another preferred solution, the drive circuit of the present invention includes X9C103 chip U24, the 5th pin of U24 is respectively connected with one end of the resistor R208 and the 1st pin of the TL431 chip U23, the other end of R208 is respectively connected with one end of the resistor R207 and the input end of the optocoupler OP1 The anode is connected, the cathode of the OP1 input terminal is connected to the 3 pin of U23, the 2 pin of U23 is connected to GND, the capacitor C27, the negative electrode of the capacitor C28, the 3 pin of U24, the 2 pin of U23, the 4 pin of U24, the one end of the capacitor C29, the one end of the capacitor C30. Connected,
AD/DC_POW芯片U29的1脚接市电L，U29的2脚接市电N，U29的3脚分别与+15V、电容C59一端、电容C60正极、电阻R231一端、NPN三极管Q10集电极相连，R231另一端分别与Q10基极、OP1输出端集电极相连，OP1输出端发射极分别与U29的4脚、C59另一端、C60负极、电阻R237一端、Q3_S相连，R237另一端分别与Q3_B、电阻R226一端相连，R226另一端接Q10发射极；AD/DC_POW chip U29's
STM32F030F4芯片U34的10、11、12分别与U34_PA4、U34_PA5、U34_PA6对应连接，U34的1接通过电阻R251接GND，四角接插接P6的1脚分别与+3.3V、电容C91一端相连，C91另一端分别与P6的4脚、GND相连，P6的2、3脚分别与U34_TMS、U34_TCK对应相连；10, 11 and 12 of STM32F030F4 chip U34 are connected to U34_PA4, U34_PA5 and U34_PA6 respectively. The 1 connection of U34 is connected to GND through resistor R251. One end is connected to pin 4 and GND of P6 respectively, and pins 2 and 3 of P6 are connected to U34_TMS and U34_TCK respectively;
电容C105～109并联在+3.3V与GND之间。Capacitors C105-109 are connected in parallel between +3.3V and GND.
作为另一种优选方案，本发明还包括输入交流电过零捕获电路，输入交流电过零捕获电路包括变压器T1第二副边，T1第二副边一端依次通过二极管D3、电阻R1接光耦U49输入端阳极，U49输入端阴极分别与T1第二副边中心抽头、光耦U50输入端阴极相连，U50输入端阳极依次通过电阻R255、二极管D4接T1第二副边另一端；As another preferred solution, the present invention also includes an input AC zero-crossing capture circuit, the input AC zero-crossing capture circuit includes the second secondary side of the transformer T1, and one end of the second secondary side of T1 is connected to the input of the optocoupler U49 through the diode D3 and the resistor R1 in turn. Terminal anode, U49 input terminal cathode is respectively connected to the center tap of T1 second secondary side, optocoupler U50 input terminal cathode, U50 input terminal anode is connected to the other end of T1 second secondary side through resistor R255 and diode D4 in turn;
U49输出端集电极接+3.3V，U49输出端发射极接U33_PB1，U50输出端发射极接U33_PB2，U50输出端集电极接+3.3V。The collector of the output terminal of U49 is connected to +3.3V, the emitter of the output terminal of U49 is connected to U33_PB1, the emitter of the output terminal of U50 is connected to U33_PB2, and the collector of the output terminal of U50 is connected to +3.3V.
作为另一种优选方案，本发明所述RS485总线第一监听部分包括SP3485芯片U39，U39的1脚接U33_PA3，U39的2、3脚接U33_PA1，U39的4脚接U33_PA2，U39的5～8脚分别与GND、A、B、+3.3V对应相连，电阻R263两端分别与B、GND相连，电阻R264两端分别与A、+3.3V相连。As another preferred solution, the first monitoring part of the RS485 bus of the present invention includes the SP3485 chip U39, the 1 pin of U39 is connected to U33_PA3, the 2 and 3 pins of U39 are connected to U33_PA1, the 4 pin of U39 is connected to U33_PA2, and the 5-8 of U39 The pins are respectively connected to GND, A, B and +3.3V, the two ends of the resistor R263 are connected to B and GND respectively, and the two ends of the resistor R264 are connected to A and +3.3V respectively.
作为另一种优选方案，本发明所述RS485总线第二监听部分包括SP3485芯片U35，U35的1脚接U34_PA3，U35的2、3脚接U34_PA1，U35的4脚接U34_PA2，U35的5、6、7、8脚分别与GND、A、B、+3.3V对应相连；As another preferred solution, the second monitoring part of the RS485 bus of the present invention includes the SP3485 chip U35, the 1 pin of U35 is connected to U34_PA3, the 2 and 3 pins of U35 are connected to U34_PA1, the 4 pin of U35 is connected to U34_PA2, and the 5 and 6 pins of U35 are connected to U34_PA1. , 7 and 8 pins are respectively connected to GND, A, B, +3.3V;
电阻R242两端分别与B、GND相连，电阻R243两端分别与A、+3.3V相连。The two ends of the resistor R242 are respectively connected to B and GND, and the two ends of the resistor R243 are respectively connected to A and +3.3V.
作为另一种优选方案，本发明还包括电压传感器电路，电压传感器电路包括HBV10A3.3芯片VP1，VP1的1脚依次通过电阻R216、R215接Q3_S，VP1的2脚依次通过电阻R221、R220接PGND，VP1的4、5、6脚分别与U43_PA7、GND、+3.3V对应相连；As another preferred solution, the present invention also includes a voltage sensor circuit. The voltage sensor circuit includes a HBV10A3.3 chip VP1.
电阻R227一端分别与U34_PA7、电容C58一端相连，R227另一端分别与GND、C58另一端相连。One end of resistor R227 is connected to U34_PA7 and one end of capacitor C58 respectively, and the other end of R227 is connected to GND and the other end of C58 respectively.
本发明是单相供盘根电感应加热电源电路；同时通过各部分的相互配合，提高户外用感应加热电源的使用效果和功能性。The invention is a single-phase electric induction heating power supply circuit for packing; meanwhile, the use effect and functionality of the outdoor induction heating power supply are improved through the mutual cooperation of various parts.
附图说明Description of drawings
下面结合附图和具体实施方式对本发明做进一步说明。本发明保护范围不仅局限于以下内容的表述。The present invention will be further described below with reference to the accompanying drawings and specific embodiments. The protection scope of the present invention is not limited to the following descriptions.
图1是本发明工作原理图Fig. 1 is the working principle diagram of the present invention
图２、３是本发明功率主电路原理图。Figures 2 and 3 are schematic diagrams of the main power circuit of the present invention.
图４～11、18是本发明RS485总线第一监听部分、RS485总线第二监听部分、电压传感器电路和驱动电路原理图。4 to 11 and 18 are schematic diagrams of the first monitoring part of the RS485 bus, the second monitoring part of the RS485 bus, the voltage sensor circuit and the driving circuit of the present invention.
图12～14是本发明主处理器电路原理图。12 to 14 are schematic diagrams of the main processor circuit of the present invention.
图15～17是本发明电流采集部分电路原理图。15 to 17 are circuit schematic diagrams of the current collection part of the present invention.
图19～24是本发明FPGA电路原理图。19 to 24 are schematic diagrams of the FPGA circuit of the present invention.
具体实施方式Detailed ways
图2所示，加热体由抽油杆（１）、油管（２）、高频线（３）按照（４）方向缠绕、绕在固定高温外壳（５）上、接线之间的连接由大功率快接高温插头（９）相连、磁力线方向按（６）方向分布，电流方向按照（７）和（８）方向，构成整个的加热体。As shown in Figure 2, the heating body is wound by the sucker rod (1), the oil pipe (2), and the high-frequency wire (3) in the direction of (4), and is wound on the fixed high temperature casing (5). The power quick-connect high temperature plug (9) is connected, the direction of the magnetic force line is distributed in the direction of (6), and the direction of the current is in the direction of (7) and (8) to form the whole heating body.
如图2-24所示，本发明包括主处理器、FPGA、功率主电路、电流采集部分、RS485总线第一监听部分、RS485总线第二监听部分和驱动电路，驱动电路的控制信号输入端口与主处理器的控制信号输出端口相连，驱动电路的信号传输端口与FPGA的信号传输端口相连，驱动电路的控制信号输出端口与功率主电路的控制信号输入端口相连；As shown in Figure 2-24, the present invention includes a main processor, an FPGA, a power main circuit, a current acquisition part, a first monitoring part of the RS485 bus, a second monitoring part of the RS485 bus, and a driving circuit. The control signal input port of the driving circuit is connected to The control signal output port of the main processor is connected, the signal transmission port of the drive circuit is connected with the signal transmission port of the FPGA, and the control signal output port of the drive circuit is connected with the control signal input port of the power main circuit;
电流采集部分的信号传输端口与FPGA的信号传输端口相连；The signal transmission port of the current acquisition part is connected with the signal transmission port of the FPGA;
RS485总线第一监听部分的信号输入端口与驱动电路的信号输出端口相连；The signal input port of the first monitoring part of the RS485 bus is connected with the signal output port of the drive circuit;
RS485总线第二监听部分的信号输入端口与驱动电路的信号输出端口相连；The signal input port of the second monitoring part of the RS485 bus is connected with the signal output port of the drive circuit;
功率主电路的电能输入端接单相市电。The power input terminal of the main power circuit is connected to the single-phase commercial power.
所述主处理器采用STM32H743IIT6 ARM处理器U5，U5的158、148、135、126、113、102、90、71、61、22、14脚接地，U5的172、159、149、136、127、114、103、91、82、72、62、49、36、23、15接+3.3V；The main processor adopts STM32H743IIT6 ARM processor U5, U5 pins 158, 148, 135, 126, 113, 102, 90, 71, 61, 22, 14 are grounded, and U5 pins 172, 159, 149, 136, 127, 114, 103, 91, 82, 72, 62, 49, 36, 23, 15 connect to +3.3V;
MPM-20-12芯片U55的1脚接UU9.8共模电感L5的2脚，L5的1脚分别与变阻器R299一端、保险丝F1一端相连，F1另一端接L，R299另一端分别与N、L5的3脚相连，L5的4脚接U55的2脚，U55的3脚分别与电容C203一端、电容C204正极、+12V相连，C203另一端分别与U55的4脚、C204负极、GND相连；
电阻R2一端接U5_BOOT0，R2另一端接GND；One end of resistor R2 is connected to U5_BOOT0, and the other end of R2 is connected to GND;
SP3485芯片U60的1脚接U5_PA3，U60的2、3脚接U5_PA1，U60的4脚接U5_PA2，U60的5～8脚分别与GND、A、B（A和B是内部的RS485总线，用于连接FPAG、处理器，主处理器U5通过RS485控制其它微处理器和FPGA协调工作）、+3.3V对应相连，电阻R290分别与B、GND相连，电阻R291分别与A、+3.3V相连；
SP3485芯片U64的1脚接U5_PA10，U64的2、3脚接U5_PA8，U64的4脚接U5_PA92，U64的5、6、7、8脚分别与GND、A、B、+3.3V对应相连，电阻R292分别与B、GND相连，电阻R293分别与A、+3.3V相连；热电偶用于测量待加工的工件的温度，根据热电偶的反馈值；当温度偏高时，通过RS485内部总线控制U33从而控制Q1和Q2的的导通时间；降低输入端电压；从而降低整机加热功率，而降低工件温升，反之亦然。
SP3485芯片U63的1脚接U5_PA10，U63的2、3脚接U5_PA8，U63的4脚接U5_PA9，U63的5、6、7、8脚分别与GND、A、B、+3.3V对应相连，电阻R294分别与B、GND相连，电阻R295分别与A、+3.3V相连；
电容C85、C69～C82并联接在+3.3V、GND之间；Capacitors C85, C69~C82 are connected in parallel between +3.3V and GND;
+3.3V通过电阻R24分别与RESET、电容C84一端、开关SW1一端相连，C84另一端分别与GND、SW1另一端相连；+3.3V is connected to RESET, one end of capacitor C84 and one end of switch SW1 through resistor R24 respectively, and the other end of C84 is connected to GND and the other end of SW1 respectively;
SD8942/A6166芯片U19的1脚通过电容C19分别与U19的6脚、电感L3一端相连，L3另一端分别与+5V、电阻R206一端相连，R206另一端分别与电阻R205一端、U19的3脚相连，R205另一端分别与GND、U19的2脚相连，U19的4脚通过电阻R204分别与U19的5脚、+12V、电容C22一端、电容C23一端、电容C24一端相连，C22另一端分别与C23另一端、C24另一端、GND相连；
4脚接插件P3的1脚接GND，P3的3脚分别与U5_JTMS、电阻R19一端相连，R19另一端接+3.3V，P3的2脚分别与U5_JTCK、电阻R22一端相连，R22另一端接GND，P3的1脚接GND；The 1-pin of the 4-pin connector P3 is connected to GND, the 3-pin of P3 is connected to one end of U5_JTMS and resistor R19, the other end of R19 is connected to +3.3V, the 2-pin of P3 is connected to U5_JTCK and one end of resistor R22, and the other end of R22 is connected to GND ,
晶振Y1的4脚接GND，Y1的1脚分别与U5_OSC_OUT、电容C67一端相连，C67另一端分别与GND、Y1的2脚、电容C68一端相连，C68另一端分别与Y1的3脚、U5_OSC_IN相连；The 4th pin of the crystal oscillator Y1 is connected to GND, the 1st pin of Y1 is connected to U5_OSC_OUT and one end of the capacitor C67, the other end of C67 is connected to GND, the 2nd pin of Y1, and the other end of the capacitor C68, and the other end of C68 is connected to the 3rd pin of Y1 and U5_OSC_IN respectively. ;
晶振Y2的一端分别与电容C66一端、U5_OSC32_IN相连，C66另一端分别与GND、电容C83一端相连，C83另一端分别与Y2的另一端、U5_OSC32_OUT相连。One end of crystal oscillator Y2 is connected to one end of capacitor C66 and U5_OSC32_IN respectively, the other end of C66 is connected to GND and one end of capacitor C83 respectively, and the other end of C83 is connected to the other end of Y2 and U5_OSC32_OUT respectively.
U5的171脚通过电阻R5分别与U5的37脚、电容C43一端、C44一端、GND相连，C43另一端分别与U5的39脚、C44另一端、电阻R4一端相连，R4另一端接+3.3V；
U5的125脚通过电容C41分别与GND、电容C39一端相连，C39另一端接U5的81脚；
U5的38脚分别与+3.3V、电容C40一端相连，C40另一端接GND；
U5的6脚分别与+3.3V、电容C36一端相连，C36另一端分别与GND、电阻R8一端相连，R8另一端接U5的48脚；
U5的166脚接U5_BOOT0；U5 pin 166 is connected to U5_BOOT0;
U5的31脚接RESET。
所述FPGA采用EP4CE10F17C8芯片U22的H7～10、J7～10、B2、B15、C5、C12、D7、D10、E4、E13脚接GND，U22的G4、G13、K4、K13、M4、M13、N7、N10、P5、P12、R2、R15、E2、H16、H15脚接GND；The FPGA uses EP4CE10F17C8 chip U22's H7~10, J7~10, B2, B15, C5, C12, D7, D10, E4, E13 pins connected to GND, U22's G4, G13, K4, K13, M4, M13, N7 , N10, P5, P12, R2, R15, E2, H16, H15 pins are connected to GND;
HT7550-1芯片VR1的Vin脚分别与电容C31、C32、C53、+5V相连，C31另一端分别与GND、C32另一端、C53另一端、VR1的GND脚、电容C33～38一端、电容C42一端、电容C45～49一端相连，电容C33另一端分别与VR1的Vout脚、C34～38另一端、电容C42另一端、电容C45～49另一端、+3.3V相连；The Vin pin of HT7550-1 chip VR1 is connected to capacitors C31, C32, C53, +5V respectively, the other end of C31 is connected to GND, the other end of C32, the other end of C53, the GND pin of VR1, one end of capacitors C33~38, and one end of capacitor C42 , One end of capacitor C45~49 is connected, the other end of capacitor C33 is connected to Vout pin of VR1, the other end of C34~38, the other end of capacitor C42, the other end of capacitor C45~49, +3.3V;
HT7550-1芯片VR2的Vin脚分别与电容C50一端、电容C51一端、电容C55一端、+3.3V相连，C50另一端分别与GND、电容C51另一端、电容C55另一端、VR2的GND脚、电容C52负极、电容C56一端相连，C52正极分别与VR2的Vout脚、C56另一端、+1.2V相连；The Vin pin of HT7550-1 chip VR2 is connected to one end of capacitor C50, one end of capacitor C51, one end of capacitor C55, and +3.3V respectively. The negative electrode of C52 and one end of capacitor C56 are connected, and the positive electrode of C52 is connected to the Vout pin of VR2, the other end of C56, and +1.2V respectively;
HT7550-1芯片VR3的Vin脚分别与电容C61～63一端、+5V相连，C61～63另一端分别与GND、VR3的GND脚、电容C65负极、电容C86一端、电容C88一端、电容C89一端、电容C93一端相连，C65正极分别与VR3的Vout脚、电容C86另一端、电容C88另一端、电容C89另一端、电容C93另一端、+2.5V相连；The Vin pin of HT7550-1 chip VR3 is connected to one end of capacitors C61~63 and +5V respectively, the other end of C61~63 is respectively connected to GND, the GND pin of VR3, the negative electrode of capacitor C65, one end of capacitor C86, one end of capacitor C88, one end of capacitor C89, One end of capacitor C93 is connected, and the positive electrode of C65 is connected to the Vout pin of VR3, the other end of capacitor C86, the other end of capacitor C88, the other end of capacitor C89, the other end of capacitor C93, and +2.5V;
SP3485芯片U65的1脚接B4，U65的2、3脚接D5，U65的4脚接D6；U65的5、6、7、8脚分别与GND、A、B、+3.3V对应相连，电阻R275分别与B、GND相连，电阻R2765分别与A、+3.3V相连。The 1 pin of U65 of SP3485 chip is connected to B4, the 2 and 3 pins of U65 are connected to D5, and the 4 pin of U65 is connected to D6; R275 is connected to B and GND respectively, and resistor R2765 is connected to A and +3.3V respectively.
U22的L5脚接+2.5V，U22的N4脚接+1.2V，U22的F12脚接+2.5V，U22的D13脚接+1.2V，U22的E12、M5脚接GND；The L5 pin of U22 is connected to +2.5V, the N4 pin of U22 is connected to +1.2V, the F12 pin of U22 is connected to +2.5V, the D13 pin of U22 is connected to +1.2V, and the E12 and M5 pins of U22 are connected to GND;
U22的H4脚通过电阻R121分别与+2.5V、电阻R131一端、U22的H12脚相连，U22的H3脚通过电阻R128接GND，R131另一端接U22的J5脚；The H4 pin of U22 is connected to +2.5V, one end of the resistor R131, and the H12 pin of U22 through the resistor R121 respectively. The H3 pin of U22 is connected to GND through the resistor R128, and the other end of R131 is connected to the J5 pin of U22;
U22的H13脚分别与U22的G12脚、GND、电阻R241一端相连，R241另一端接U22的J3脚；The H13 pin of U22 is connected to the G12 pin, GND, and one end of the resistor R241 of U22 respectively, and the other end of R241 is connected to the J3 pin of U22;
U22的H14脚通过电阻R252接+3.3V，U22的H5脚通过电阻R253接+3.3V，U22的F4脚通过电阻R254接+3.3V；Pin H14 of U22 is connected to +3.3V through resistor R252, pin H5 of U22 is connected to +3.3V through resistor R253, and pin F4 of U22 is connected to +3.3V through resistor R254;
JTAG-10-FPGA接口JTAG1的2、10脚接GND，JTAG1的4脚接+2.5V；JTAG-10-FPGA interface JTAG1 pins 2 and 10 are connected to GND, and
U22的E3、G3、K3、M3、P4、P7、T1、P10、P13、T16、K14、M14、E14、G14、A16、C10、C13、A1、C4、C7脚接+3.3V，U22的G6～G10、H6、H11、K7脚接+1.2V；U22's E3, G3, K3, M3, P4, P7, T1, P10, P13, T16, K14, M14, E14, G14, A16, C10, C13, A1, C4, C7 pins are connected to +3.3V, U22's G6 ～G10, H6, H11, K7 pins are connected to +1.2V;
晶振XTAL1的2脚接GND，XTAL1的3脚接CLK_1，XTAL1的4脚接+3.3V；The 2-pin of the crystal oscillator XTAL1 is connected to GND, the 3-pin of XTAL1 is connected to CLK_1, and the 4-pin of XTAL1 is connected to +3.3V;
M25P16芯片U30的6、5、2、8脚分别与EPCS_CLK、EPCS_ASDO、EPCS_DATA0、+3.3V对应相连，U30的4脚接GND，U30的3、7脚接+3.3V，U30的1脚接EPCS_CS。
所述功率主电路包括空气开关K1，K1一端与市电相连，K1另一端与变压器T1原边相连，T1第一副边一端分别与二极管D1阴极、IGBT Q2的漏极、Q2_D相连，D1的阳极分别与IGBT Q1的源极、Q1_S相连，Q1的门极接Q1_B，Q1的漏极分别与Q1_D、二极管D2阴极、共模电感L2的1脚相连，D2阳极分别与Q2的源极、Q2_S相连，Q2的门极接Q2_B，L2的3脚接T1第一副边另一端；The power main circuit includes an air switch K1, one end of K1 is connected to the mains, the other end of K1 is connected to the primary side of the transformer T1, and one end of the first secondary side of T1 is respectively connected to the cathode of the diode D1, the drain of the IGBT Q2, and Q2_D. The anode is connected to the source of IGBT Q1 and Q1_S respectively, the gate of Q1 is connected to Q1_B, the drain of Q1 is connected to Q1_D, the cathode of diode D2, and
L2的2脚分别与二极管D5阳极、二极管D7阴极相连，D5阴极分别与二极管D6阴极、电感L1一端相连，L1另一端分别与电容C6一端、NPN三极管Q3集电极相连，Q3基极接Q3_B，Q3发射极分别与Q3_S、电容C1～C4一端、IGBT Q4漏极、IGBT Q5漏极相连，C1～C4另一端分别与电容C9～C12一端、Q4源极、Q4_S、IGBT Q6漏极、主变压器T2原边一端相连，T2原边另一端分别与电容C7一端、电容C8一端、电容C13一端、电容C14一端、电容C5一端相连，电容C7另一端、电容C8另一端、电容C13另一端、电容C14另一端、电容C5另一端分别与Q5_S、Q5源极、IGBTQ7漏极相连，Q7源极分别与PGND、Q6源极、电容C9～C12另一端、C6另一端、D7阳极、二极管D8阳极相连，D8阴极分别与L2的4脚、D6阳极相连；
T2第一副边一端分别与电容C110～C115一端相连，C110～C115另一端接二脚接插件P8的1脚，P8的2脚通过电流互感器T3原边接T2第一副边另一端。One end of the first secondary side of T2 is respectively connected to one end of capacitors C110~C115, the other end of C110~C115 is connected to the 1st pin of the two-pin connector P8, and the 2nd pin of P8 is connected to the other end of the first secondary side of T2 through the primary side of the current transformer T3.
Q4、Q5、Q6、Q7可采用FZ800R33KF2C型号的IGBT。Q4, Q5, Q6, Q7 can use FZ800R33KF2C IGBT.
图中D1、Q1、D2、Q2及U33部分组成降压式调功电路，可以灵活的在每个交流周期的过零点开通，而在达到或接近90°之前进行关断，并可在超过90°以后和180°前进行二次开通，这样大大降低了对电网最高电位点的电流冲击；极大的提高了设备的功率因数。Parts D1, Q1, D2, Q2 and U33 in the figure form a step-down power regulation circuit, which can be flexibly turned on at the zero-crossing point of each AC cycle, and turned off before reaching or approaching 90°, and can be turned off when it exceeds 90°. After ° and before 180 °, the second turn-on is carried out, which greatly reduces the current impact on the highest potential point of the power grid; greatly improves the power factor of the equipment.
如图所示，T1B绕组35T，T1A绕组165T，将单相220V交流电升至1100V。As shown in the figure, the T1B winding is 35T, and the T1A winding is 165T, raising the single-phase 220V AC to 1100V.
电路的输入端存在容量巨大的滤波电容，由于电容特性，其上电瞬间近似于短路，导致对前端整流桥的电流冲击极大，甚至击穿整流桥。本发明大功率NPN三极管Q3安装在整流桥和输入滤波电容中间，上电前三极管工作在截止区；此时整流桥电流为0；系统上电后，通过微处理器检测电容端电压；There is a large-capacity filter capacitor at the input end of the circuit. Due to the characteristics of the capacitance, it is similar to a short circuit at the moment of power-on, resulting in a great current impact on the front-end rectifier bridge, or even breakdown of the rectifier bridge. The high-power NPN triode Q3 of the present invention is installed between the rectifier bridge and the input filter capacitor, and the triode works in the cut-off region before power-on; at this time, the current of the rectifier bridge is 0; after the system is powered on, the capacitor terminal voltage is detected by the microprocessor;
系统初次上电时候，全部微处理器部分，供电又AC220转DC15供电而来，全部微处理器优先于主电路部分开始工作。当U5系统自检成功，与其他RS485总线上从机微处理器进行通讯，获取数据，其他微处理器启动完成后，发送给U34微处理器，进入主电路启动状态，U34通过VP1电压传感器，检测出Q3_S对PGND端电压低于30V时(Q3_S对PGND端电压就是C1、C2、C3、C4、C9、C10、C11、C12组滤波电容端电压)，判断为必须防浪涌启动，通过控制Q3工作在放大区（Q3与滤波电容组为串联关系）在放大区的Q3可以通过其IB电流的大小限制对电容组充电电流的大小，从而防止浪涌对前端电路得损害。When the system is powered on for the first time, all the microprocessors are powered from AC220 to DC15, and all the microprocessors start to work prior to the main circuit. When the U5 system self-test is successful, it communicates with other slave microprocessors on the RS485 bus to obtain data. After the other microprocessors are started, they are sent to the U34 microprocessor to enter the main circuit startup state. U34 passes the VP1 voltage sensor, When it is detected that the voltage of Q3_S to PGND terminal is lower than 30V (the voltage of Q3_S to PGND terminal is the voltage of C1, C2, C3, C4, C9, C10, C11, C12 group filter capacitor terminals), it is judged that it must be anti-surge to start, by controlling Q3 works in the amplification area (Q3 and the filter capacitor group are in series relationship). Q3 in the amplification area can limit the size of the charging current to the capacitor group through the size of its IB current, thereby preventing the surge from damaging the front-end circuit.
其中IB电流的控制函数为：The control function of the IB current is:
if(VP1<(220*1.414)/0.75){IB = 0.67mA}else{IB = 1.5A};if(VP1<(220*1.414)/0.75){IB = 0.67mA}else{IB = 1.5A};
通过驱动电路控制三极管Q3缓慢的从截止区进入放大区，因为工作在放大区的三极管介入，整流桥的电流始终被限制在安全范围以内；当滤波电容电压缓慢上升后；达到75%的额定电压后；防浪涌三极管Q3进入放大区，完成一次防浪涌电流的目的。因其防浪涌工作时间非常短暂，并在未完成浪涌工作时，H桥谐振电路（Q4-Q7）并未工作，其散热装置无温升产生；所以大功率三极管Q3与H桥IGBT共用同散热器并无需增大其原始散热器体积。The transistor Q3 is controlled by the drive circuit to slowly enter the amplifying area from the cut-off area. Because of the intervention of the transistor working in the amplifying area, the current of the rectifier bridge is always limited within the safe range; when the filter capacitor voltage rises slowly, it reaches 75% of the rated voltage After that; the anti-surge triode Q3 enters the amplifying area to complete the purpose of anti-surge current. Because the anti-surge working time is very short, and when the surge work is not completed, the H-bridge resonant circuit (Q4-Q7) does not work, and its heat sink does not generate temperature rise; so the high-power transistor Q3 is shared with the H-bridge IGBT The same radiator does not need to increase its original radiator volume.
所述电流采集部分包括可调基准源控制电路、线性驱动电路、电压基准阵列和电压比较器阵列，可调基准源控制电路的输出端口与电压基准阵列的输入端口相连，电压基准阵列的输出端分别与电压比较器阵列的输入端、FPGA相连，线性驱动电路的输出端口与电压比较器阵列的输入端相连。The current acquisition part includes an adjustable reference source control circuit, a linear drive circuit, a voltage reference array and a voltage comparator array. The output port of the adjustable reference source control circuit is connected to the input port of the voltage reference array, and the output end of the voltage reference array is connected. It is respectively connected with the input end of the voltage comparator array and the FPGA, and the output port of the linear drive circuit is connected with the input end of the voltage comparator array.
所述可调基准源控制电路包括AD/DC_POW芯片U44，U44的1脚接市电L，U44的2脚接市电N，U44的3脚分别与+15VA、电容C126一端、电容C127正极、电阻R307一端、NPN三极管Q17集电极相连，R307另一端分别与Q17基极、光耦OP3输出端集电极相连，光耦OP3输出端发射极分别与电容C126另一端、电容C127负极、U44的4脚、电阻R309一端、GND相连；Q17发射极通过电阻R308分别与电阻R309另一端、VRE_1相连；The adjustable reference source control circuit includes AD/DC_POW chip U44,
OP3输入端阳极分别与电阻R305一端、电阻R306一端相连，R305另一端分别与电容C123正极、电容C122一端、+15VA相连，C122另一端分别与GND、C123负极、TL431芯片U46的2脚、X9C103芯片U45的3脚、U45的4脚、电容C124一端、电容C125一端相连；C124、C125另一端接U45的8脚、+3.3V，U45的7、2、1脚分别与J12、J14、J15对应相连；U45的5脚分别与U46的1脚、R306另一端相连，U46的3脚接OP3输入端阴极。The anode of OP3 input terminal is connected to one end of resistor R305 and one end of resistor R306 respectively. The other end of R305 is connected to the positive pole of capacitor C123, one end of capacitor C122 and +15VA respectively.
所述电压基准阵列包括电阻R10，R10一端接VRE_1，R10另一端依次通过电阻、R15～R17、R25、R30～R32、R37、R42～R44、R49、R54～R56、R61、R66、R67、R68、R73、R78～80、R85、R90～92、R97、R102～104、R109、R110、R115、R116、R122、R123、R129、R130、R136、R137、R142、R143、R148、R149、R154、R155、R160、R161、R166、R167、R172、R173、R178、R179、R184、R185、R190、R191、R196、R197、R202、R203接X9C103芯片U18的5脚，U18的3脚分别与GND、V、RE_1、U18的4脚、电容C20一端、电容C21一端相连，C20另一端分别与+3.3V、U18的8脚、C21另一端相连，U18的7、2、1分别与L6、K6、J6对应相连。The voltage reference array includes a resistor R10, one end of R10 is connected to VRE_1, and the other end of R10 passes through resistors, R15~R17, R25, R30~R32, R37, R42~R44, R49, R54~R56, R61, R66, R67, R68 in sequence. , R73, R78～80, R85, R90～92, R97, R102～104, R109, R110, R115, R116, R122, R123, R129, R130, R136, R137, R142, R143, R148, R149, R154, R155 , R160, R161, R166, R167, R172, R173, R178, R179, R184, R185, R190, R191, R196, R197, R202, R203 connect to pin 5 of U18 of X9C103 chip,
所述电压比较器阵列包括MAX9140芯片U1、U2、U3、U4、U5、U6、U7、U8、U9、U10、U11、U12、U13、U14、U15、U16、U17，U1～U17的4脚分别与电容C17正极、电容C18一端、+5V相连，U1～U17的11脚分别与电容C17负极、电容C18另一端、GND相连；The voltage comparator array includes MAX9140 chips U1, U2, U3, U4, U5, U6, U7, U8, U9, U10, U11, U12, U13, U14, U15, U16, U17, and the 4 pins of U1 to U17 are respectively Connect to the positive pole of capacitor C17, one end of capacitor C18, and +5V, and the 11 pins of U1 to U17 are respectively connected to the negative pole of capacitor C17, the other end of capacitor C18, and GND;
U1～U17的3、5、12、10脚接ADC0，U1～U17的9脚分别与V15、V30～V16对应连接，U1～U17的13脚分别与V31、V14～V0对应连接，U1～U17的6脚分别与V47～V32对应连接，U1～U17的2脚分别与V 63～V 48对应连接；
U1～U17的8脚分别通过1K电阻与K2、F3、D2、D1、G5、F2、F1、G2、G1、G16、G15、F13、F16、F15、B16、F14对应连接，K2、F3、D2、D1、G5、F2、F1、G2、G1、G16、G15、F13、F16、F15、B16、F14分别通过2K电阻接GND；The 8 pins of U1~U17 are respectively connected with K2, F3, D2, D1, G5, F2, F1, G2, G1, G16, G15, F13, F16, F15, B16, F14 through 1K resistors, K2, F3, D2 , D1, G5, F2, F1, G2, G1, G16, G15, F13, F16, F15, B16, F14 are respectively connected to GND through 2K resistors;
U1～U17的14脚分别通过1K电阻与C2、K1、L2、L1、L3、N2、N1、K5、L4、R1、P2、P1、D4、E5、F5、B1对应连接，C2、K1、L2、L1、L3、N2、N1、K5、L4、R1、P2、P1、D4、E5、F5、B1分别通过2K电阻接GND；The 14 pins of U1~U17 are respectively connected with C2, K1, L2, L1, L3, N2, N1, K5, L4, R1, P2, P1, D4, E5, F5, B1 through 1K resistors, C2, K1, L2 , L1, L3, N2, N1, K5, L4, R1, P2, P1, D4, E5, F5, B1 are respectively connected to GND through 2K resistors;
U1～U17的7脚分别通过1K电阻与D16、D15、G11、C16、C15、R9、T9、K9、L9、M9、N9、R10、T10、R11、T11、R12对应连接，D16、D15、G11、C16、C15、R9、T9、K9、L9、M9、N9、R10、T10、R11、T11、R12分别通过2K电阻接GND；The 7 pins of U1~U17 are respectively connected with D16, D15, G11, C16, C15, R9, T9, K9, L9, M9, N9, R10, T10, R11, T11, R12 through 1K resistors, D16, D15, G11 , C16, C15, R9, T9, K9, L9, M9, N9, R10, T10, R11, T11, R12 are connected to GND through 2K resistors respectively;
U1～U17的1脚分别通过1K电阻与T12、K10、L10、P9、P11、R13、T13、M10、N11、T14、T15、R14、P14、L11、M11、N12对应连接，T12、K10、L10、P9、P11、R13、T13、M10、N11、T14、T15、R14、P14、L11、M11、N12分别通过2K电阻接GND。
线性驱动电路包括MOSFET-N管Q21，Q21的漏极分别与ADC0、稳压管ZD2阴极、二极管D9阴极相连，Q21源极分别与GND、ZD2阴极、电容C16一端、电流互感器T3副边一端相连，T3副边另一端分别与电容C15一端、D9阳极相连，C15另一端分别与C16另一端、FG相连；The linear drive circuit includes MOSFET-N tube Q21, the drain of Q21 is connected to ADC0, Zener tube ZD2 cathode, diode D9 cathode respectively, Q21 source is respectively connected to GND, ZD2 cathode, one end of capacitor C16, and one end of the secondary side of current transformer T3 The other end of the secondary side of T3 is connected to one end of capacitor C15 and the anode of D9 respectively, and the other end of C15 is connected to the other end of C16 and FG respectively;
+15VA分别与电容C121一端、电容C120正极、电阻R304一端相连，R304另一端分别与电阻R303一端、光耦OP2输入端阳极相连，光耦OP2输入端阴极接TL431芯片U43的3脚，U43的2脚分别与GND、电容C121另一端、电容C120负极、X9C103芯片U42的3脚、U42的4脚、电容C99一端、电容C98一端相连，U43的1脚分别与电阻R303另一端、U42的5脚相连，U42的1、2、7脚分别与J13、J2、J1对应相连，U42的8脚分别与电容C99另一端、电容C98另一端相连；+15VA is connected to one end of capacitor C121, the positive electrode of capacitor C120, and one end of resistor R304 respectively. The other end of R304 is connected to one end of resistor R303 and the anode of the input end of optocoupler OP2. The cathode of the input end of optocoupler OP2 is connected to pin 3 of U43 of the TL431 chip, and the
L接AD/DC_POW芯片U41的1脚，U41的2脚接N，U41的3脚分别与+15VA、电容C97一端、电容C96正极、电阻R302一端、NPN三极管Q16集电极相连，R302另一端分别与Q16基极、OP2输出端集电极相连，OP2输出端发射极分别与U41的4脚、C97另一端、C96负极、电阻R300一端、GND相连，R300另一端分别与Q21_G、电阻R301一端相连，电阻R301另一端接Q16的发射极。L is connected to pin 1 of AD/DC_POW chip U41,
通过T3A电磁互感型电流传感器采集输出侧电流，该电流为感应加热负载电流。本发明通过基准阵列电路、电压比较器阵列电路、底层可变基准电压电路、FPGA电路，进行高速的对输出侧电流进行采集；利用电磁互感型电流传感器电路的高速转换率将输出侧电流进行按比例转换成电压信号，通过并保存完整的还原实际电流波形形状及电流真有效值，提供给主处理器U5。The output side current is collected by the T3A electromagnetic mutual inductance current sensor, which is the induction heating load current. The invention uses the reference array circuit, the voltage comparator array circuit, the underlying variable reference voltage circuit, and the FPGA circuit to collect the output side current at high speed; and utilizes the high-speed conversion rate of the electromagnetic mutual inductance type current sensor circuit to press the output side current. The ratio is converted into a voltage signal, and the complete restoration of the actual current waveform shape and the true RMS value of the current is passed and saved, and provided to the main processor U5.
U5正常启动后配置U5外设，通过U63接入RS485内部总线，通过U39建立与微处理器U33的通讯连接，获取U33的启动状态。通过U35建立与微处理器U34的通讯连接，获取U34的启动状态。通过U65获取U22现场可编程门阵列（FPGA）的启动状态。After U5 starts normally, configure U5 peripherals, connect to the RS485 internal bus through U63, establish a communication connection with the microprocessor U33 through U39, and obtain the startup status of U33. A communication connection with the microprocessor U34 is established through the U35 to obtain the startup state of the U34. Get the startup status of the U22 Field Programmable Gate Array (FPGA) through the U65.
U5通过内部RS485总线控制U33进去50%调压状态，控制U34进入防浪涌启动工作。U5同过于U34进行通讯确定防浪涌启动结束。U5通过内部RS485总线与U65和U22（FPGA）建立通讯，通过U22输出四路H桥驱动信号；通过U21、U28、U36、U38隔离性IGBT驱动芯片，进行驱动H桥电路（Q4、Q5、Q6、Q7）；进行扫频。U5通过内部RS485总线得到U22扫频完成的信息后；通过RS485总线；控制U33进行100调转状态；进行全功率输出。U5 controls U33 to enter the 50% voltage regulation state through the internal RS485 bus, and controls U34 to enter the anti-surge start-up work. U5 communicates with U34 to determine the end of anti-surge start. U5 establishes communication with U65 and U22 (FPGA) through the internal RS485 bus, and outputs four-way H-bridge drive signals through U22; through U21, U28, U36, and U38 isolated IGBT drive chips, it drives the H-bridge circuit (Q4, Q5, Q6). , Q7); sweep frequency. After U5 obtains the information of U22's frequency sweeping completion through the internal RS485 bus; through the RS485 bus; controls U33 to perform 100 switching state; performs full power output.
U5在控制周期中，均通过U64获取外部检点热电偶所测量的温度值；并通过自整定PID控制U33的调压值来控制输出功率，使之控制加热工件的温度符合恒温度的设定值。U22微调整H桥的工作频率，使整机始终与加热工件工作在谐振点。如果在微调整过程中未找到合适的谐振点（例如工件加热达到居里温度），U22会重新从设备所支持的最低频率扫频至最高频率再次进行扫频获取新谐振点，并固定在新谐振点继续工作。In the control cycle, U5 obtains the temperature value measured by the external inspection thermocouple through U64; and controls the output power through the self-tuning PID control of the voltage regulation value of U33, so that the temperature of the heated workpiece is in line with the set value of the constant temperature. . U22 finely adjusts the working frequency of the H bridge, so that the whole machine always works at the resonance point with the heated workpiece. If a suitable resonance point is not found during the fine-tuning process (for example, the workpiece is heated to the Curie temperature), U22 will re-sweep the frequency from the lowest frequency supported by the device to the highest frequency to obtain a new resonance point, and fix it at the new resonance point. The resonance point continues to work.
本发明电流采集部分包括63个分压电阻和一个数字可调电阻组成64位分压电路；由64个超高速电压比较组成电压比较器阵列。The current collecting part of the present invention includes 63 voltage dividing resistors and a digital adjustable resistor to form a 64-bit voltage dividing circuit; 64 ultra-high-speed voltage comparisons form a voltage comparator array.
本发明Q21工作在可变电阻区作为电流转电压电路，通过T3电磁互感型电流传感器通过公式 N1:N2=V1:V2=1/A1:1/A2 ;可得互感型电流传感器T3B端输出电流为T3A端1/5000，根据欧姆定律U=I*R；因Q21通过U22控制工作在可变电阻区；所以其Q21的电阻值可动态改变；T3B的电流适中在其后端取样阵列的敏感区间之内。The Q21 of the present invention works in the variable resistance region as a current-to-voltage circuit, and through the T3 electromagnetic mutual inductance current sensor, the formula N1:N2=V1:V2=1/A1:1/A2; the output current of the T3B terminal of the mutual inductance current sensor can be obtained It is 1/5000 of the T3A terminal, according to Ohm's law U=I*R; because Q21 is controlled by U22 to work in the variable resistance region; so the resistance value of its Q21 can be dynamically changed; the current of T3B is moderate, and the sensitivity of the sampling array at its rear end is moderate. within the range.
采集电流通过互感器经过整流电路通过电阻转换将输出端电流转换成电压信号。The collected current converts the output current into a voltage signal through the transformer through the rectifier circuit through resistance conversion.
通过电流互感器得到与输出电流特性相同电流按比例缩小的电流信号；通过工作在可变电阻区的Q21场效应管将电流信号转换成电压信号，电压信号通过由底层可变基准源及63位分压电阻组成的电压参考阵列加载到64位电压比较器的同相端，电压比较器的输出端接入FPGA。其中Q21在可变电阻区阻值变化由FPGA通过线性驱动电路控制，电阻分压阵列的底层基准源阻值由FPGA驱动。The current signal with the same current characteristics as the output current is scaled down through the current transformer; the current signal is converted into a voltage signal through the Q21 field effect transistor working in the variable resistance region, and the voltage signal is passed through the underlying variable reference source and 63-bit The voltage reference array composed of voltage dividing resistors is loaded into the non-inverting terminal of the 64-bit voltage comparator, and the output terminal of the voltage comparator is connected to the FPGA. The change of the resistance value of Q21 in the variable resistance area is controlled by the FPGA through the linear drive circuit, and the resistance value of the underlying reference source of the resistor divider array is driven by the FPGA.
互感型电流传感器其电流电压转换结果，VER_1的电压值可以通过其对地的电阻而同比增加，即电阻越大电压越高反之亦然。当被测电流较大时；可以通过调整Q21场效应管将其在可变电阻的等效电阻值降低至后端采集电路的敏感范围内；同样如果被测电流较小时，可以通过调整Q21场效应管将其可变电阻区的等效电阻值增值后端采集电路的敏感范围内，以获得最佳的采集精度。而电阻分压阵列的底层可变基准的作用在于，当在需要测量的电流值其某段范围需要高精度测量的时候的，通过调整底层的电压基准调整到所需测量范围最小值作为检测范围启动的阀值，将剩余范围作为63位的高分辨率检测范围。例如在测量某50A高频电流时；通过调整底层可变基准和电压比较器阵列的反向输入端参考基准将其测量范围测定在45A至55A之间；提高检测电流值的精度。The current-voltage conversion result of the mutual inductance current sensor, the voltage value of VER_1 can be increased year-on-year through its resistance to ground, that is, the larger the resistance, the higher the voltage and vice versa. When the measured current is large; the equivalent resistance value of the variable resistor can be reduced to the sensitive range of the back-end acquisition circuit by adjusting the Q21 FET; also if the measured current is small, the Q21 field can be adjusted by adjusting the The effect tube increases the equivalent resistance value of its variable resistance area within the sensitive range of the back-end acquisition circuit to obtain the best acquisition accuracy. The function of the underlying variable reference of the resistor divider array is that when a certain range of the current value to be measured requires high-precision measurement, the underlying voltage reference is adjusted to the minimum value of the required measurement range as the detection range. Threshold to start, the remaining range is used as a 63-bit high-resolution detection range. For example, when measuring a high-frequency current of 50A; the measurement range is determined between 45A and 55A by adjusting the underlying variable reference and the reference reference of the reverse input end of the voltage comparator array; improving the accuracy of the detected current value.
驱动电路包括KP103芯片U21、 U28、 U36、 U38，U21的4脚接+15V、U21的5脚接GND、U21的2脚分别与电阻R214一端、电容C26一端相连，C26另一端分别与R214另一端、+15V相连，U21的3脚接S8050三极管Q9集电极相连，Q9基极分别与电阻R222一端、电阻R223一端相连，R222另一端接A3，R223另一端分别与GND、Q9发射极相连；U21的13脚通过电阻R224接光耦U26输入端阴极，U26输入端阳极接U21的18脚，U26输出端发射极接A8，U26输出端集电极接+3.3V，U21的17脚分别与电阻R213一端、双向稳压二极管ZD4一端、Q4_S相连，U21的16、15脚接电阻R212一端，R212另一端分别与R213另一端、ZD4另一端、Q4_B相连，U21的12脚通过稳压二极管接二极管D11阳极，D11阴极接Q3_S；The drive circuit includes KP103 chips U21, U28, U36, U38,
U28的4脚接+15V、U28的5脚接GND、U28的2脚分别与电阻R233一端、电容C57一端相连，C57另一端分别与R233另一端、+15V相连，U28的3脚接S8050三极管Q12集电极相连，Q12基极分别与电阻R238一端、电阻R239一端相连，R238另一端接B3，R239另一端分别与GND、Q12发射极相连；U28的13脚通过电阻R240接光耦U32输入端阴极，U32输入端阳极接U28的18脚，U32输出端发射极接B8，U32输出端集电极接+3.3V，U28的17脚分别与电阻R232一端、双向稳压二极管ZD6一端、Q5_S相连，U28的16、15脚接电阻R230一端，R230另一端分别与R232另一端、ZD6另一端、Q5_B相连，U28的12脚通过稳压二极管接二极管D13阳极，D13阴极接Q3_S；
U36的4脚接+15V、U36的5脚接GND、U36的2脚分别与电阻R246一端、电容C64一端相连，C64另一端分别与R246另一端、+15V相连，U36的3脚接S8050三极管Q13集电极相连，Q13基极分别与电阻R248一端、电阻R247一端相连，R247另一端接C3，R248另一端分别与GND、Q13发射极相连；U36的13脚通过电阻R249接光耦U37输入端阴极，U37输入端阳极接U36的18脚，U37输出端发射极接C8，U37输出端集电极接+3.3V，U36的17脚分别与电阻R245一端、双向稳压二极管ZD7一端、PGND相连，U36的16、15脚接电阻R244一端，R244另一端分别与R245另一端、ZD7另一端、Q6_B相连，U36的12脚通过稳压二极管接二极管D14阳极，D14阴极接Q4_S；
U38的4脚接+15V、U38的5脚接GND、U38的2脚分别与电阻R261一端、电容C87一端相连，C87另一端分别与R261另一端、+15V相连，U38的3脚接S8050三极管Q14集电极相连，Q14基极分别与电阻R265一端、电阻R266一端相连，R265另一端接D3，R266另一端分别与GND、Q14发射极相连；U38的13脚通过电阻R267接光耦U40输入端阴极，U40输入端阳极接U38的18脚，U40输出端发射极接D8，U40输出端集电极接+3.3V，U38的17脚分别与电阻R260一端、双向稳压二极管ZD8一端、PGND相连，U38的16、15脚接电阻R259一端，R259另一端分别与R260另一端、ZD8另一端、Q7_B相连，U38的12脚通过稳压二极管接二极管D15阳极，D15阴极接Q5_S。
U21、U28、U36、U38用于驱动IGBT Q4～Q7，经过微处理器U22 或FPGA输出的PMM信号或者高低电平信号经过该电路后；转换成同相位同频率同脉宽的正15V负9V（高电平对应+15V导通IGBT，低电平对应-9V关断IGBT） 电流9A以上的具有驱动功率的信号连接IGBT控制器导通与关断。KP103具有IGBT过零时快速关断IGBT进行保护。U21, U28, U36, U38 are used to drive IGBTs Q4~Q7. After the PMM signal or high and low level signal output by microprocessor U22 or FPGA passes through this circuit, it is converted into positive 15V negative 9V with the same phase, same frequency and same pulse width. (The high level corresponds to +15V to turn on the IGBT, and the low level corresponds to -9V to turn off the IGBT.) The signal with driving power above 9A is connected to the IGBT controller to turn on and off. KP103 has the function of quickly turning off the IGBT for protection when the IGBT crosses zero.
Q1的过流信号通过U27的18、13脚通过U31反馈给微处理器U33_PA7。The overcurrent signal of Q1 is fed back to the microprocessor U33_PA7 through U31 through
Q2的过流信号通过U20的18、13脚通过U25反馈给微处理器U33_PA5。The overcurrent signal of Q2 is fed back to the microprocessor U33_PA5 through
Q4的过流信号通过U21的18、13脚通过U26反馈给微处理器U22_A8。The overcurrent signal of Q4 is fed back to the microprocessor U22_A8 through U21's 18 and 13 pins through U26.
Q5的过流信号通过U28的18、13脚通过U32反馈给微处理器U22_B8。The overcurrent signal of Q5 is fed back to the microprocessor U22_B8 through U32 through
Q6的过流信号通过U36的18、13脚通过U37反馈给微处理器U22_C8。The overcurrent signal of Q6 is fed back to the microprocessor U22_C8 through U37 through
Q7的过流信号通过U38的18、13脚通过U40反馈给微处理器U22_D8。The overcurrent signal of Q7 is fed back to the microprocessor U22_D8 through U40 through
U5主处理器电路的USART3（同异步串行通讯）端口连接U63，U63接入整机内部RS485总线，U5为内部RS485总线主机模式接入RS485总线。The USART3 (synchronous and asynchronous serial communication) port of the U5 main processor circuit is connected to U63, U63 is connected to the internal RS485 bus of the whole machine, and U5 is connected to the RS485 bus in the host mode of the internal RS485 bus.
FPGA(U22)内部通过软件建立有NIOS_II软核及同异步串行通讯软核，通过PIO的B4、D5、D6连接至U65，由U65连接至整机内部RS485总线，U22作为内部RS485从机模式接入RS485总线。FPGA (U22) has NIOS_II soft core and synchronous and asynchronous serial communication soft core established by software. It is connected to U65 through B4, D5 and D6 of PIO, and U65 is connected to the internal RS485 bus of the whole machine. U22 is used as the internal RS485 slave mode. Access to RS485 bus.
其中U22 FPGA通过VerilogHDL语言所编写的FPGA硬件单元建立的高速H桥驱动信号模块。The U22 FPGA is a high-speed H-bridge drive signal module established by the FPGA hardware unit written in VerilogHDL language.
所述驱动电路包括KP103芯片U20、U27，U20的4脚接+15V、U20的5脚接GND、U20的2脚分别与电阻R211一端、电容C25一端相连，C25另一端分别与R211另一端、+15V相连，U20的3脚接S8050三极管Q8集电极相连，Q8基极分别与电阻R217一端、电阻R218一端相连，R217另一端接U33_PA6，R218另一端分别与GND、Q8发射极相连；U20的13脚通过电阻R219接光耦U25输入端阴极，U25输入端阳极接U20的18脚，U25输出端发射极接U33_PA7，U25输出端集电极接+3.3V，U20的17脚分别与电阻R210一端、双向稳压二极管ZD3一端、Q2_S相连，U20的16、15脚接电阻R209一端，R209另一端分别与R210另一端、ZD3另一端、Q2_B相连，U20的12脚通过稳压二极管接二极管D10阳极，D10阴极接Q2_D；The drive circuit includes KP103 chips U20 and U27.
U27的4脚接+15V、U27的5脚接GND、U27的2脚分别与电阻R229一端、电容C54一端相连，C54另一端分别与R229另一端、+15V相连，U27的3脚接S8050三极管Q11集电极相连，Q11基极分别与电阻R234一端、电阻R235一端相连，R234另一端接U33_PA4，R235另一端分别与GND、Q11发射极相连；U27的13脚通过电阻R236接光耦U31输入端阴极，U31输入端阳极接U27的18脚，U31输出端发射极接U33_PA5，U31输出端集电极接+3.3V，U27的17脚分别与电阻R228一端、双向稳压二极管ZD5一端、Q1_S相连，U27的16、15脚接电阻R225一端，R225另一端分别与R228另一端、ZD5另一端、Q1_B相连，U27的12脚通过稳压二极管接二极管D12阳极，D12阴极接Q1_D；
STM32F030F4芯片U33的12脚接U33_PA6，STM32F030F4芯片U33的13脚接U33_PA7，STM32F030F4芯片U33的10脚接U33_PA4，STM32F030F4芯片U33的11脚接U33_PA5；
U33的1脚通过电阻R250接GND，四脚接插件P5的1脚分别与+3.3V、电容C90一端相连，C90另一端分别与GND、P5的4脚相连，P5的2、3脚分别与U33的19、20脚对应相连；
电容C100～104并联在+3.3V与GND之间。Capacitors C100-104 are connected in parallel between +3.3V and GND.
将输入单向交流的正弦波分为正负2个半轴，2个馒头波。Q2在正半轴开通和关断，Q1在负半轴开通和关断。以Q2正半周调功举例，而负半周控制原理与正半轴Q1相同，仅仅控制周期是在输入交流电的负半轴。Divide the input sine wave of one-way AC into positive and negative 2 half-axes and 2 steamed bread waves. Q2 turns on and off on the positive half axis, and Q1 turns on and off on the negative half axis. Take the positive half-cycle power regulation of Q2 as an example, and the negative half-cycle control principle is the same as that of the positive half-axis Q1, only the control period is the negative half-axis of the input AC power.
通过微处理器的内部定时器T1中断，设定时器溢出中断时间为每半周周期的1/100时间，通过双向计数器，最大计数值为双向50，从正半周的过零点开始从50开始递减，当正半周最大值时为计数值0，而后开始递增，到正半周结束时计数值为50。设计电压调整值0-50，其中0为最高电压，50位最小电压，每次T1发生中断计数器发生变化后；与电压调整值进行对比，调整值大于计数值的时候，就关闭Q2管，否则开通Q2。在下周正半周期过零点的时候，在从新开通。It is interrupted by the internal timer T1 of the microprocessor, and the timer overflow interrupt time is set to 1/100 of each half cycle. Through the bidirectional counter, the maximum count value is 50 in both directions, and it starts to decrease from 50 from the zero-crossing point of the positive half cycle. , when the positive half cycle is the maximum value, the count value is 0, and then starts to increase, and the count value is 50 when the positive half cycle ends. The design voltage adjustment value is 0-50, of which 0 is the highest voltage and 50-bit minimum voltage. After each T1 interrupt occurs, the counter changes; compare it with the voltage adjustment value, when the adjustment value is greater than the count value, turn off the Q2 tube, otherwise Open Q2. When the positive half cycle crosses zero next week, it will be reopened.
根据U5的RS485通讯命令；需要最大功率输出的时，Q2和Q1每个半周期均直至开通，后端整流滤波电路接收到完整的馒头波波形；其电压幅值最高。According to the RS485 communication command of U5; when the maximum power output is required, each half cycle of Q2 and Q1 is turned on, and the back-end rectifier and filter circuit receives the complete steamed bread waveform; its voltage amplitude is the highest.
所述驱动电路包括X9C103芯片U24，U24的5脚分别与电阻R208一端、TL431芯片U23的1脚相连，R208另一端分别与电阻R207一端、光耦OP1输入端阳极相连，OP1输入端阴极接U23的3脚，U23的2脚分别与GND、电容C27、电容C28负极、U24的3脚、U23的2脚、U24的4脚、电容C29一端、电容C30一端相连，U24的8脚分别与+3.3V、电容C29另一端、电容C30另一端相连，U24的1、2、7脚分别与U34_PA4、U34_PA5、U34_PA6对应连接，+15V分别与C27另一端、C28另一端、R207另一端相连；The driving circuit includes the X9C103 chip U24, the 5th pin of U24 is connected to one end of the resistor R208 and the 1st pin of the TL431 chip U23 respectively, the other end of R208 is respectively connected to one end of the resistor R207 and the anode of the input end of the optocoupler OP1, and the cathode of the input end of OP1 is connected to
AD/DC_POW芯片U29的1脚接市电L，U29的2脚接市电N，U29的3脚分别与+15V、电容C59一端、电容C60正极、电阻R231一端、NPN三极管Q10集电极相连，R231另一端分别与Q10基极、OP1输出端集电极相连，OP1输出端发射极分别与U29的4脚、C59另一端、C60负极、电阻R237一端、Q3_S相连，R237另一端分别与Q3_B、电阻R226一端相连，R226另一端接Q10发射极；AD/DC_POW chip U29's
STM32F030F4芯片U34的10、11、12分别与U34_PA4、U34_PA5、U34_PA6对应连接，U34的1接通过电阻R251接GND，四角接插接P6的1脚分别与+3.3V、电容C91一端相连，C91另一端分别与P6的4脚、GND相连，P6的2、3脚分别与U34_TMS、U34_TCK对应相连；10, 11 and 12 of STM32F030F4 chip U34 are connected to U34_PA4, U34_PA5 and U34_PA6 respectively. The 1 connection of U34 is connected to GND through resistor R251. One end is connected to pin 4 and GND of P6 respectively, and pins 2 and 3 of P6 are connected to U34_TMS and U34_TCK respectively;
电容C105～109并联在+3.3V与GND之间。Capacitors C105-109 are connected in parallel between +3.3V and GND.
U34通过10脚11脚12脚分别连接U24的1脚2脚7脚；U24芯片型号为X9C103为数字可变电阻芯片，该芯片的功能是通过控制其1脚2脚和7脚，可以改变5脚和3脚之间的电阻值。U24芯片的型号为TL431其功能为2.5V基准源芯片。其功能为该芯片的1脚和2脚之间的电压始终保持在2.5V；当电压高于2.5V时，芯片会降低3脚到2脚的电阻值，当2脚电平低于2.5V时，会增加3脚到2脚的阻值，该电路与光耦组合使用组成隔离性电压采样反馈电路。U34 is connected to pin 1,
微处理器U34通过3个GPIO引脚控制U24的5脚和3脚的电阻值。Microprocessor U34 controls the resistance value of
通过电阻R208与U24的5脚和3脚组成电阻分压电路。A resistor divider circuit is formed through resistor R208 and pins 5 and 3 of U24.
U23与OP1原边组成串联电路，其OP1原边的电流受R207和U23限制；其中R207阻值固定不变。U23 and the primary side of OP1 form a series circuit, and the current of the primary side of OP1 is limited by R207 and U23; the resistance value of R207 is fixed.
据前所述芯片U23芯片TL431的特性，通过改变1脚和2脚分压情况，可控制其OP1电流，从而改变OP1副边光敏三极管的导通深度。According to the characteristics of the chip U23 chip TL431 mentioned above, by changing the voltage division of
U29为AD220V转DC15V电源变换器，该15V电源通过Q10和R226到Q3的B极，Q10的IB电流受OP1的副边控制，当OP1副边导通深度大时，Q10的IB电流降低反之亦然，Q10的IB电流的减小，造成Q10的进入放大区，从而控制Q3的IB电流，控制Q3的工作状态。致使U34微处理器通过控制可使Q3工作在线性区（放大区），对设备进行防浪涌的保护。U29 is an AD220V to DC15V power converter. The 15V power supply passes through Q10 and R226 to the B pole of Q3. The IB current of Q10 is controlled by the secondary side of OP1. When the conduction depth of the secondary side of OP1 is large, the IB current of Q10 decreases and vice versa Of course, the reduction of the IB current of Q10 causes the entry of Q10 into the amplification area, thereby controlling the IB current of Q3 and controlling the working state of Q3. As a result, the U34 microprocessor can make Q3 work in the linear region (amplification region) through control, and protect the equipment against surges.
还包括输入交流电过零捕获电路（U33获取输入交流过零捕获信号；控制Q1和Q2，实现降压调功功能。U5通过RS485与U33通讯，将控制值传给U33）。It also includes the input AC zero-crossing capture circuit (U33 obtains the input AC zero-crossing capture signal; controls Q1 and Q2 to realize the function of step-down power regulation. U5 communicates with U33 through RS485, and transmits the control value to U33).
输入交流电过零捕获电路包括变压器T1第二副边，T1第二副边一端依次通过二极管D3、电阻R1接光耦U49输入端阳极，U49输入端阴极分别与T1第二副边中心抽头、光耦U50输入端阴极相连，U50输入端阳极依次通过电阻R255、二极管D4接T1第二副边另一端；The input AC zero-crossing capture circuit includes the second secondary side of the transformer T1. One end of the second secondary side of T1 is connected to the anode of the input terminal of the optocoupler U49 through the diode D3 and the resistor R1 in sequence. The cathode of the input terminal of U50 is connected to the cathode, and the anode of the input terminal of U50 is connected to the other terminal of the second secondary side of T1 through the resistor R255 and the diode D4 in turn;
U49输出端集电极接+3.3V，U49输出端发射极接U33_PB1，U50输出端发射极接U33_PB2，U50输出端集电极接+3.3V。The collector of the output terminal of U49 is connected to +3.3V, the emitter of the output terminal of U49 is connected to U33_PB1, the emitter of the output terminal of U50 is connected to U33_PB2, and the collector of the output terminal of U50 is connected to +3.3V.
所述RS485总线第一监听部分包括SP3485芯片U39，U39的1脚接U33_PA3，U39的2、3脚接U33_PA1，U39的4脚接U33_PA2，U39的5～8脚分别与GND、A、B、+3.3V对应相连，电阻R263两端分别与B、GND相连，电阻R264两端分别与A、+3.3V相连。The first monitoring part of the RS485 bus includes the SP3485 chip U39, the 1st pin of U39 is connected to U33_PA3, the 2nd and 3rd pins of U39 are connected to U33_PA1, the 4th pin of U39 is connected to U33_PA2, and the 5th to 8th pins of U39 are respectively connected to GND, A, B, +3.3V is connected correspondingly, both ends of resistor R263 are connected to B and GND respectively, and both ends of resistor R264 are connected to A and +3.3V respectively.
微处理器（U33）和RS485通讯总线电路，作为RS485从机时刻监听RS485总线上报文数据。根据总线上RS485主机发送的给本机的命令对IGBT管Q1和Q2的导通与关断的时长进行控制。U33程序中配置内部定时器TIM1其定时器每100uS产生一次定时器溢出中断并失能该定时器（配置好但不启动）。配置外部下降沿中断脚PB1引脚和PB2引脚，PB1外接至输入交流电过零保护电路U49二次侧，PB2接至U50，T1C、D绕组为交流输入主变压器的一组降压辅助绕组，该绕组有中心抽头；根据其同名端关系,当交流输入从正半周（同名端为高电平）到零后，其经过二极管D3至U49在U49二次侧（PB1处）可以到一矩形波其下降沿就是其负半周的过零点；Q1的导通开始时刻。反之亦然为Q2的导通开始时刻（Q2的过零捕获电路为D4和U50）。在U49二次侧得到其的下降沿触发了微处理器电路U33的PB1下降沿外部中断服务函数；其函数内首先导通Q1管，并对全局计数器COUN1进行赋值0；使能TIM1定时器，TIM1使能后没100uS产生一次TIM1溢出中断，在每次进入该服务函后，均对COUN1的值对RS485总线上主机发送导通时长数值进行比较；当COUN1的值等于其值后；使Q1立即关断。并失能TIM1定时器。当次半周期结束U50二次侧将产生下降沿；此时PB2输入下降沿中断服务函数，并相应的通过COUN1计数来控制Q2导通时长，其实现原理与Q1部分相同。The microprocessor (U33) and the RS485 communication bus circuit are used as the RS485 slave to monitor the message data on the RS485 bus at all times. According to the command sent by the RS485 host on the bus to the local machine, the on and off durations of the IGBT tubes Q1 and Q2 are controlled. The internal timer TIM1 is configured in the U33 program. The timer generates a timer overflow interrupt every 100uS and disables the timer (configured but not started). Configure the external falling edge interrupt pins PB1 and PB2. PB1 is externally connected to the secondary side of the input AC zero-crossing protection circuit U49, and PB2 is connected to U50. The T1C and D windings are a set of step-down auxiliary windings of the AC input main transformer. The winding has a center tap; according to the relationship between the same-named terminals, when the AC input goes from the positive half-cycle (the same-named terminal is high) to zero, it can reach a rectangular wave on the secondary side (PB1) of U49 through diode D3 to U49 Its falling edge is the zero-crossing point of its negative half cycle; the conduction start time of Q1. And vice versa is the turn-on start time of Q2 (the zero-crossing capture circuit of Q2 is D4 and U50). The falling edge obtained on the secondary side of U49 triggers the external interrupt service function of the PB1 falling edge of the microprocessor circuit U33; the Q1 tube is first turned on in the function, and the global counter COUN1 is assigned a value of 0; the TIM1 timer is enabled, After TIM1 is enabled, a TIM1 overflow interrupt is generated within 100uS. After each entry into the service function, the value of COUN1 is compared with the value of the on-time sent by the host on the RS485 bus; when the value of COUN1 is equal to its value; make Q1 Shut down immediately. And disable the TIM1 timer. When the second half cycle ends, the secondary side of U50 will generate a falling edge; at this time, PB2 inputs the falling edge to interrupt the service function, and accordingly controls the conduction time of Q2 through COUN1 counting. The realization principle is the same as that of Q1.
所述RS485总线第二监听部分包括SP3485芯片U35，U35的1脚接U34_PA3，U35的2、3脚接U34_PA1，U35的4脚接U34_PA2，U35的5、6、7、8脚分别与GND、A、B、+3.3V对应相连；The second monitoring part of the RS485 bus includes the SP3485 chip U35, the 1 pin of U35 is connected to U34_PA3, the 2 and 3 pins of U35 are connected to U34_PA1, the 4 pin of U35 is connected to U34_PA2, and the 5, 6, 7 and 8 pins of U35 are connected to GND, A, B, +3.3V are connected correspondingly;
电阻R242两端分别与B、GND相连，电阻R243两端分别与A、+3.3V相连。The two ends of the resistor R242 are respectively connected to B and GND, and the two ends of the resistor R243 are respectively connected to A and +3.3V.
微处理器（U34）和RS485通讯总线电路，作为RS485从机时刻监听RS485总线上报文数据。根据总线上RS485主机发送的给本机的命令进行相应的控制Q3三极管的IB电流使其工作在放大区或饱和区。在整机上电初期；Q3因为没有得到RS485通讯总线上的主机的命令，微处理器控制Q3工作在截止区，此时Q3没有电流流过。当主机控制器U5进入启动模式后，通过RS485通讯总线命令微处理器最小电路（U34）进入启动模式后，微处理器通过控制Q3的IB电流使其从截止区缓慢进入放大区，并时刻通过VP1检测Q3_S和PGND间电压；当电压达到2/3(*220*1.414)时,控制Q3进入饱和区，进行正常的运行模式。其中U24、U29、U23、OP1及外围电路组成数字可控线性驱动电路，该电路可由微处理器U34通过3位GPIO控制U24的5脚与3之间的阻值。当U24其5脚3脚阻值发生变化后，通过U23的1脚基准电压发生变化，导致U23的3脚2脚电阻发生变化，又而改变OP1一次侧的发光功率导致二次侧对Q10的IB的影响；从而改变Q3的IB电流；控制器U34在负荷的工作范围和工作区中。The microprocessor (U34) and the RS485 communication bus circuit are used as the RS485 slave to monitor the message data on the RS485 bus at all times. According to the command sent by the RS485 host on the bus to the local machine, the IB current of the Q3 transistor is controlled accordingly to make it work in the amplification area or the saturation area. At the initial stage of power-on of the whole machine; because Q3 did not get the command from the host on the RS485 communication bus, the microprocessor controlled Q3 to work in the cut-off area, and there was no current flowing through Q3 at this time. When the host controller U5 enters the startup mode, it commands the microprocessor minimum circuit (U34) to enter the startup mode through the RS485 communication bus. VP1 detects the voltage between Q3_S and PGND; when the voltage reaches 2/3 (*220*1.414), it controls Q3 to enter the saturation region and performs normal operation mode. Among them, U24, U29, U23, OP1 and peripheral circuits form a digitally controllable linear drive circuit, which can be controlled by the microprocessor U34 through 3-bit GPIO to control the resistance between
还包括电压传感器电路，电压传感器电路包括HBV10A3.3芯片VP1，VP1的1脚依次通过电阻R216、R215接Q3_S，VP1的2脚依次通过电阻R221、R220接PGND，VP1的4、5、6脚分别与U43_PA7、GND、+3.3V对应相连；It also includes a voltage sensor circuit. The voltage sensor circuit includes HBV10A3.3 chip VP1.
电阻R227一端分别与U34_PA7、电容C58一端相连，R227另一端分别与GND、C58另一端相连。One end of resistor R227 is connected to U34_PA7 and one end of capacitor C58 respectively, and the other end of R227 is connected to GND and the other end of C58 respectively.
电压传感器VP1采集Q3_S与PGND两端的电压（主储能滤波电容电压）。通过获取该位置电压用于：输入防浪涌保护、设备的输出功率计算、降压调控控制。The voltage sensor VP1 collects the voltage across Q3_S and PGND (the main energy storage filter capacitor voltage). By obtaining the voltage at this position, it is used for: input surge protection, output power calculation of equipment, and step-down regulation and control.
可以理解的是，以上关于本发明的具体描述，仅用于说明本发明而并非受限于本发明实施例所描述的技术方案，本领域的普通技术人员应当理解，仍然可以对本发明进行修改或等同替换，以达到相同的技术效果；只要满足使用需要，都在本发明的保护范围之内。It can be understood that the above specific description of the present invention is only used to illustrate the present invention and is not limited to the technical solutions described in the embodiments of the present invention. Those of ordinary skill in the art should understand that the present invention can still be modified or It is equivalent to replacement to achieve the same technical effect; as long as the needs of use are met, they are all within the protection scope of the present invention.
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