CN111833940A

CN111833940A - Memory chip and control method thereof

Info

Publication number: CN111833940A
Application number: CN201910298708.2A
Authority: CN
Inventors: 侯建杕; 郑吴全
Original assignee: Winbond Electronics Corp
Current assignee: Winbond Electronics Corp
Priority date: 2019-04-15
Filing date: 2019-04-15
Publication date: 2020-10-27
Anticipated expiration: 2039-04-15
Also published as: CN111833940B

Abstract

The invention provides a memory chip and a control method thereof. The database includes a first sub-database and a second sub-database. The first sub-database includes a first storage unit. The first memory cell is coupled to a first word line and an access line, and outputs data to the access line through a first path. The second database includes a second storage unit. The second memory cell is coupled to a second word line and the access line, and outputs data to the access line through a second path. The address decoding circuit decodes an external address to generate a row address and a column address. The control circuit turns on the first path and turns off the second path when the row address points to the first word line and the column address points to the access line.

Description

Memory chip and control method thereof

Technical Field

The present invention relates to a memory chip and a control method thereof, and more particularly, to a memory chip for performing an access operation and a refresh operation simultaneously in the same database (bank).

Background

Generally, a DRAM has a plurality of capacitors for storing data. However, since the voltage of the capacitor is lost with time, the voltage of the capacitor needs to be updated (refresh) at intervals so as to store the correct voltage. At the same time of refresh, the DRAM cannot output data or store data.

Disclosure of Invention

The invention provides a memory chip, which comprises at least one database, an address decoding circuit and a control circuit. The database includes a first sub-database and a second sub-database. The first sub-database includes a first storage unit. The first memory cell is coupled to a first word line and a first access line, and outputs data to the first access line through a first path. The second database includes a second storage unit. The second memory cell is coupled to a second word line and the first access line, and outputs data to the first access line through a second path. The address decoding circuit decodes an external address to generate a row address and a column address. The control circuit controls the first and second paths according to the row address and the column address. The control circuit turns on the first path and turns off the second path when the row address points to the first word line and the column address points to the first access line.

The invention also provides a control method, which is used for decoding an external address to generate a row address and a column address; when the row address points to the first word line and the column address points to the access line: providing an access signal to the first word line and providing a refresh signal to the second word line; conducting a first path to enable the first storage unit to output data to the access line through the first path; and not conducting a second path, so that the second memory cell does not output data to the access line through the second path.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

FIG. 1 is a diagram of an accessing system according to the present invention.

FIG. 2 is a diagram of a memory chip according to the present invention.

FIG. 3 is a schematic diagram of a memory circuit according to the present invention.

FIG. 4A is a schematic diagram of a memory cell of the present invention.

FIG. 4B is a diagram of a memory cell according to the present invention.

Fig. 5 is a schematic flow chart of a control method according to the present invention.

Description of the symbols:

100: the access system 110: external device

120: memory chip CD_E: external instruction

AR_E: external address DA_E: external data

DA_O: data 121: command address bus

122: data bus 210: address buffer circuit

220: the command decoding circuit 230: address decoding circuit

240: the memory circuit 250: temporary storage circuit

P1-P8: pin AR_R: row address

AR_C: column address 231: row decoder

232: column decoder 241: control circuit

BK₁～BK_K: database SB₁、SB₂: secondary database

AL₁、AL₂～AL_M: the access lines 310: selection circuit

320: databases 321, 322: secondary database

CE₁～CE₄: memory cell WL₁、WL₂: word line

350: the memory circuit 330: access circuit

340: logic circuit PA₁～PA₄: route of travel

360: renew the counter S_RS: re-updating signal

S_AS: access signal FL: counter with a memory

410: control switches 420, 460: amplifying circuit

430: the equalizer 440: switching circuit

450: the buffer circuit 470: reading circuit

C: capacitance Vref: reference voltage

M0-M11: transistors BL,/BL: bit line

EQ: parity signal CSL: row select signal

441. 442: switches 451-453: logic gate

L1, L2: level IN1, IN 2: input terminal

SEL: selecting an end OT: output end

DQ₁: data S511 to S517: step (ii) of

311. 312: selector device

SC, SAE _ N, SAE _ P, MDQE: control signal

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

FIG. 1 is a diagram of an accessing system according to the present invention. As shown, the access system 100 includes an external device 110 and a memory chip (chip) 120. The external device 110 is independent of the memory chip 120. The inventionThe kind of the external device 110 is not limited. In one embodiment, the external device 110 is a memory controller (memory controller). The external device 110 sends an external command CD_EAnd an external address AR_E。

Memory chip 120 decodes external command CD_EFor determining an external command CD_EThe kind of (2). For example, when the external command CD_EIn the case of a write command, the memory chip 120 operates in a write mode. In the write mode, the memory chip 120 is operated according to the external address AR_EReceiving and storing an external data DA provided by the external device 110_E. When the external command CD_EIn the case of a read command, the memory chip 120 operates in a read mode. In the read mode, the memory chip 120 is operated according to the external address AR_EOutput a data DA_OTo the external device 110.

In the present embodiment, the memory chip 120 has a command address bus 121 and a data bus 122. The command address bus 121 is used for receiving an external command CD_EAnd an external address AR_E. In one embodiment, the command address bus 121 receives the external command CD in a parallel transmission mode (parallel transmission) or a serial transmission mode (serial transmission)_EAnd an external address AR_E. The data bus 122 is used for transmitting external data DA_EAnd data DA_O. In one embodiment, the data bus 122 receives the external data DA provided by the external device 110 in a parallel transmission manner or a serial transmission manner_EOr output data DA_OTo the external device 110.

FIG. 2 is a diagram of a memory chip according to the present invention. As shown, the memory chip 120 includes a command address bus 121, a data bus 122, an address buffer circuit 210, a command decoder circuit 220, an address decoder circuit 230, a memory circuit 240, and a register circuit 250.

In the present embodiment, the command address bus 121 provides the external address AR through the pins P1-P8_ETo the address buffer circuit 210 and provided through the pins P1-P8External command CD_ETo the command decoding circuit 220. In other embodiments, the command address bus 121 has more or fewer pins.

The address buffer circuit 210 is coupled to the command address bus 121 for temporarily storing the external address AR_E. In the present embodiment, the address buffer circuit 210 transmits the external address AR_ETo the address decoding circuit 230. The present invention is not limited to the circuit architecture of the address buffer circuit 210. In one possible embodiment, the address buffer circuit 210 has a plurality of registers (not shown) for storing the external address AR_E。

The address decoding circuit 230 is coupled to the address buffer circuit 210 for receiving the external address AR_E. In the present embodiment, the address decoding circuit 230 decodes the external address AR_EFor generating a row address AR_RAnd a row address AR_C. The present invention is not limited to the architecture of the address decoding circuit 230. In a possible embodiment, the address decoding circuit 230 includes a row decoder 231 and a column decoder 232. The row decoder 231 decodes the external address AR_EFor generating a row address AR_R. The column decoder 232 decodes the external address AR_EFor generating a column address AR_C。

The memory circuit 240 is coupled to the address decoding circuit 230 for receiving the column address AR_RAnd column address AR_C. In the present embodiment, the memory circuit 240 includes a control circuit 241 and a database (Bank) BK₁～BK_K. In a possible embodiment, part of the control circuit 241 is independent of the database BK₁～BK_KBesides, another part of the control circuit 241 is integrated into the database BK₁～BK_KAmong them. In another possible embodiment, the control circuit 241 is fully integrated in the database BK₁～BK_KAmong them.

The control circuit 241 is based on the row address AR_RAnd column address AR_CControl database BK₁～BK_KThe operation of (2). In the present embodiment, the database BK₁～BK_KIs divided into two databases. With a database BK₁For example, a database BK₁Is divided into sub-databases SB₁And SB₂But are not intended to limit the invention. In other embodiments, the database BK₁～BK_KIs divided into more secondary databases. In some embodiments, the database BK₁～BK_KIs not partitioned into multiple secondary databases.

Due to the database BK₁～BK_KAll the characteristics of (A) are the same, so the following is a database BK₁For example. When line address AR_RPointing to the Secondary database SB₁The control circuit 241 is based on the column address AR_COrder sub database SB₁Output data to access line AL₁～AL_MAt least one. Thus, the secondary database SB₁Operating in an access mode. In access mode, the secondary database SB₁An access operation is performed. For example, the secondary database SB₁Possibly via an access line AL₁～AL_MReceive external data DA from the register circuit 250_EOr via the access line AL₁～AL_MProviding data DA_OTo the temporary storage circuit 250.

In the time database SB₁While operating in access mode, due to the row address AR_RNot to the secondary database SB₂Therefore, the control circuit 241 cuts off the sub-database SB₂And access line AL₁～AL_MThe path between them. Thus, the secondary database SB₂Does not output data to the access line AL₁～AL_MOr from the access line AL₁～AL_MThe data of (1). In one possible embodiment, the control circuit 241 commands the secondary database SB₂Performing a refresh operation (refresh) to the secondary database SB₂The capacitor therein is charged.

In other embodiments, the current row address AR_RPointing to the Secondary database SB₂The control circuit 241 is based on the column address AR_C, conduction sub database SB₂And access line AL₁～AL_MThe path between them. Thus, the secondary database SB₂Operating in an access moduleFormula (II) is shown. In access mode, the secondary database SB₂An access operation is performed. For example, the secondary database SB₂Through the turned-on path, the data from the register circuit 250 is received or the data is outputted to the register circuit 250. At this time, since the row address AR_RNot to the secondary database SB₁Therefore, the control circuit 241 does not turn on the sub-database SB₁And access line AL₁～AL_MThe path between them. Thus, the secondary database SB₁Do not pass through the access line AL₁～AL_MReceive data from the register circuit 250, and do not pass through the access line AL₁～AL_MThe data is output to the register circuit 250. In one embodiment, the control circuit 241 may command the secondary database SB₁And carrying out the updating operation.

In this embodiment, the same database (e.g., BK)₁) In other words, when a database (e.g., SB) is used once₁) While performing an access operation, another database (e.g., SB)₂) A refresh operation is performed, so that the data accuracy of the memory circuit 240 can be improved. Furthermore, since the secondary database SB₁And access line AL₁～AL_MThe path between them is conducted and the secondary database SB₂And access line AL₁～AL_MThe path between them is cut off, so that the database BK₁The data can be immediately output, thereby improving the performance of the memory circuit 240.

In other embodiments, the database BK₁～BK_KAt least one of the access operation and the refresh operation are not performed simultaneously. With a database BK₂For example, a database BK₂And is not divided into two databases. In this example, when the database BK₂When a memory cell of the data bank BK performs an access operation₂The remaining memory cells are not subjected to the refresh operation. Similarly, when the database BK₂When a memory cell of the data bank BK is subjected to a refresh operation₂The remaining memory cells are not accessed.

Command decoding circuit 220 decodes external command CD_EFor determining an external command CD_EOf kind, e.g.A read command, a write command, or a set command. The command decoding circuit 220 decodes the command according to the external command CD_EGenerates a control signal SC.

The register circuit 250 is used for storing external data DA from the data bus 122_EAnd data DA from memory circuit 240_O. In one possible embodiment, when the external command CD_EFor a read command, the command decoding circuit 220 passes the control signal SC, and the command register circuit 250 passes the access line AL₁～AL_MReceiving data DA from the memory circuit 240_OAnd outputs data DA via data bus 122_O. However, when the CD is externally instructed_EIn the case of a write command, the command decoding circuit 220 receives the external data DA from the data bus 122 via the command register circuit 250 via the control signal SC_EAnd through access lines AL₁～AL_MTransferring external data DA_ETo the memory circuit 240.

FIG. 3 is a diagram of a memory circuit 240 according to the present invention. For convenience of illustration, fig. 3 shows only a single database, but is not intended to limit the present invention. In other embodiments, the storage circuit 240 has more databases. As shown, the storage circuit 240 includes a selection circuit 310 and a database 320. In the present embodiment, the database 320 is divided into

sub-databases

321 and 322. As shown, the secondary database 321 has a storage unit CE₁And CE₂. The secondary database 322 has a storage unit CE₃And CE₄. In other embodiments,

secondary databases

321 and 322 have more storage units.

Memory cell CE₁Coupled word line WL₁And an access line AL₁And receives a row address AR_RAnd column address AR_C. In the present embodiment, the storage unit CE₁Includes a memory circuit 350, an access circuit 330, and a logic circuit 340. The storage circuit 350 is used for storing data. The present invention is not limited to the architecture of the memory circuit 350. In one embodiment, the storage circuit 350 includes a capacitor. In this example, the charge of the capacitor represents the memory cell CE₁The stored data.

The access circuit 330 is coupled to the memory circuit 350 and the access line AL₁For writing access lines AL₁To the memory circuit 350 or for reading data of the memory circuit 350 to the access line AL₁. In the present embodiment, the access circuit 330 includes a path PA₁. When path PA₁When turned on, the access circuit 330 provides data to the access line AL₁Or from the access line AL₁The data of (1). When path PA₁When not conducting, the access circuit 330 does not provide data to the access line AL₁. The present invention is not limited to the architecture of the access circuit 330. The access circuit 330 will be described later by fig. 4A.

The logic circuit 340 is based on the row address AR_RAnd column address AR_CConducting or non-conducting path PA₁. For example, when the column address AR_RWord line WL₁And column address AR_CDirected to access lines AL₁While, the logic circuit 340 conducts the path PA₁. However, when the row address AR_RNot to the word line WL₁Or a row address AR_CNot directed to the access line AL₁While, the logic circuit 340 does not conduct the path PA₁. In one embodiment, the logic circuit 340 and the selection circuit 310 are used as the control circuit 241 in fig. 2. The present invention is not limited to the architecture of the logic circuit 340. The architecture of the logic circuit 340 will be explained later by fig. 4A.

In FIG. 3, a memory cell CE₂Coupled word line WL₁And an access line AL₂. Memory cell CE₃Coupled word line WL₂And an access line AL₁. Memory cell CE₄Coupled word line WL₂And an access line AL₂. Due to the memory cell CE₂～CE₄Similar to the memory cell CE₁Therefore, the description is omitted.

In one possible embodiment, when the row address AR_RWord line WL₁And column address AR_CDirected to access lines AL₁In time, only the storage unit CE in the secondary database 321₁Operate in an access mode, and store all the cells (e.g., CE) in the secondary database 322₃And CE₄) Is operated in a refresh mode. In one possible embodiment, the storage unit CE in the secondary database 321₂Also operating in a refresh mode.

The selection circuit 310 receives an access signal S_ASAnd a refresh signal S_RSAnd according to the row address AR_ROutputs an access signal S_ASOr the signal S is renewed_RSFor controlling the memory cells CE₁～CE₄The operating mode of (1). For example, when the column address AR_RWord line WL₁The selection circuit 310 outputs an access signal S_ASFor word line WL₁And outputs a refresh signal S_RSFor word line WL₂. At this time, if the storage unit CE₁Path PA of₁Is turned on, the memory cell CE₁Enter an access mode for storing or outputting data. In this example, the memory cell CE₃And CE₄Entering a refresh mode for maintaining the data stored therein. In a possible embodiment, the storage unit CE₂Also operating in a refresh mode.

However, when the row address AR_RWord line WL₂The selection circuit 310 outputs an access signal S_ASFor word line WL₂And outputs a refresh signal S_RSFor word line WL₁. At this time, if the storage unit CE₃Path PA of₃Is turned on, the memory cell CE₃Enter an access mode for storing or outputting data. In this example, the memory cell CE₁And CE₂Entering a refresh mode for maintaining the data stored therein. In a possible embodiment, the storage unit CE₄Also operating in a refresh mode.

The invention does not limit how the selection circuit 310 is based on the row address AR_RLearning the row address AR_RTo which secondary database. In one possible embodiment, the row address AR_RHas a plurality of bits. The selection circuit 310 is based on the row address AR_RThe logical value of at least one first specific Bit (e.g., Most Significant Bit (MSB) and its adjacent bits) of the column(s) is knownAddress AR_RTo the

database

321 or 322. In addition, the selection circuit 310 is based on the row address AR_RThe logic value of at Least one second specific Bit (such as Least Significant Bit (LSB) and its adjacent bits) to obtain the column address AR_RWord line WL₁Or WL₂. In other embodiments, the logic circuit 340 is based on the column address AR_CThe logic value of the specific bit, the row address AR_CDirected to access lines AL₁Or AL₂。

In the present embodiment, the selection circuit 310 includes

selectors

311 and 312. The selector 311 selects the row address AR_ROutputs an access signal S_ASOr the signal S is renewed_RSFor word line WL₁. For example, when the column address AR_RWord line WL₁While, the selector 311 outputs the access signal S_ASFor word line WL₁. When line address AR_RDoes not point to word line WL₁When the selector 311 outputs the refresh signal S_RSFor word line WL₁. The present invention does not limit the architecture of the selector 311. In one embodiment, the selector 311 comprises a Multiplexer (MUX). The selector 312 is based on the row address AR_ROutputs an access signal S_ASOr the signal S is renewed_RSFor word line WL₂. Since the characteristics of the selector 312 are similar to those of the selector 311, the description thereof is omitted.

In other embodiments, the memory circuit 240 further includes a refresh counter 360 for generating the refresh signal S_RS. In this example, the refresh counter 360 sends the refresh signal S every fixed time_RS. In addition, the present invention does not limit the access signal S_ASThe source of (a). In some embodiments, signal S is accessed_ASIs generated by the address decoding circuit 230 of fig. 2.

In some embodiments, the selection circuit 310 provides the refresh signal S when the secondary database 321 has not performed the refresh operation within a predetermined period_RSTo the word lines (e.g. WL) of the secondary database 321₁) For ordering the storage unit (e.g., CE) of the secondary database 321₁And CE₂) Performing a renewalAnd (5) performing new operation. In one embodiment, the secondary database 321 has a counter FL. The counter FL has a count value. When the count value reaches a predetermined value (indicating that the sub-database 321 has not performed the refresh operation within a predetermined period), the selection circuit 310 provides the refresh signal S_RSFor word line WL₁. After the secondary database 321 performs the refresh operation, the count value of the counter FL is reset to an initial value, such as 0.

FIG. 4A is a schematic diagram of a memory cell of the present invention. Since the circuit structure of the memory cells in each bank is the same, FIG. 4A only shows a single memory cell (e.g., CE in FIG. 3)₁). In the present embodiment, the storage unit CE₁Includes a memory circuit 350, a control switch 410, an amplifier circuit 420, an equalizer (equalizer)430, a switch circuit 440, a buffer circuit 450, an amplifier circuit 460, a read circuit 470 and a logic circuit 340. In other embodiments, at least one of the equalizer 430 and the buffer circuit 450 may be omitted.

The memory circuit 350 includes a capacitor C. The capacitor C receives a reference voltage Vref. In one possible embodiment, the reference voltage Vref is half of the operating voltage (not shown) of the memory chip 120.

The control switch 410 is coupled to the word line WL₁And a bit line BL. In one embodiment, the control switch 410 is used to transmit the voltage of the bit line BL to the capacitor C or the read capacitor C. In the present embodiment, the control switch 410 is a transistor M0. The gate of the transistor M0 is coupled to the word line WL₁The first source/drain is coupled to the bit line BL, and the second source/drain is coupled to the capacitor C. In other embodiments, the transistor M0 is a P-type transistor.

The amplifying circuit 420 amplifies a voltage difference between the bit lines BL and/BL to generate an amplified data. In one embodiment, the memory cells coupled to the same access line are coupled to the same bit line. Taking FIG. 3 as an example, the memory cell CE₁And CE₃For coupling the same bit line BL and the same bit line/BL. In this example, the memory cell CE₁Bit lines BL and/BL different from memory cell CE₂Bit lines BL and/BL.

The present invention is not limited to the architecture of the amplifier circuit 420. In one embodiment, the amplifying circuit 420 is a Sense Amplifier (SA) or a differential amplifier (differential amplifier). In the present embodiment, the amplifier circuit 420 includes transistors M1 to M4. The transistor M1 has a gate coupled to the bit line/BL, a first source/drain coupled to the bit line BL, and a second source/drain receiving the control signal SAE _ N. The transistor M2 has a gate coupled to the bit line BL, a first source/drain receiving the control signal SAE _ N, and a second source/drain coupled to the bit line/BL. The transistor M3 has a gate coupled to the bit line/BL, a first source/drain coupled to the bit line BL, and a second source/drain receiving the control signal SAE _ P. The transistor M4 has a gate coupled to the bit line BL, a first source/drain receiving the control signal SAE _ P, and a second source/drain coupled to the bit line/BL. In the present embodiment, the transistors M1 and M2 are N-type transistors, and the transistors M3 and M4 are P-type transistors.

The equalizer 430 is used to reduce signal distortion on the bit lines BL and/BL. When the parity signal EQ is enabled, the equalizer 430 couples the bit lines BL and/BL together. Therefore, the bit lines BL and/BL have the same level. When the parity signal EQ is not enabled, the equalizer 430 stops operating. Therefore, the bit lines BL and/BL have different potentials.

In the present embodiment, the equalizer 430 includes transistors M5-M7. The gate of the transistor M5 receives a parity signal EQ, a first source/drain thereof is coupled to the bit line BL, and a second source/drain thereof receives a reference voltage Vref. The gate of the transistor M6 receives a parity signal EQ, a first source/drain thereof receives a reference voltage Vref, and a second source/drain thereof is coupled to the bit line/BL. The gate of the transistor M7 receives a parity signal EQ, the first source/drain of which is coupled to the bit line BL, and the second source/drain of which is coupled to the bit line/BL. The transistors M5-M7 are N-type transistors, but are not intended to limit the present invention. In other embodiments, the transistors M5-M7 are all P-type transistors. In some embodiments, the equalizer 430 may be omitted.

The switch circuit 440 is coupled to the bit lines BL and/BL and determines whether to turn on the path PA according to a column selection signal CSL₁. For example, when the row selection signal CSL is enabled, the switch circuit 440 turns on the path PA₁For transmitting the signals of bit line BL and bit line/BL to the amplifying circuit 460. However, when the row selection signal CSL is not enabled, the switch circuit 440 does not conduct the path PA₁. Thus, the memory cell CE₁Data of are not transmitted to the access line AL₁。

In the present embodiment, the switch circuit 440 includes

switches

441 and 442. The switch 441 is coupled between the bit line BL and the amplifying circuit 460. The switch 442 is coupled between the bit line/BL and the amplifying circuit 460. The present invention is not limited to the types of the

switches

441 and 442. In the present embodiment, the switch 441 is a transistor M8, and the switch 442 is a transistor M9. The gate of the transistor M8 receives the row selection signal CSL, and has a first source/drain coupled to the bit line BL and a second source/drain coupled to the amplifying circuit 460. The gate of the transistor M9 receives the row selection signal CSL, the first source/drain thereof is coupled to the bit line/BL, and the second source/drain thereof is coupled to the amplifying circuit 460. As shown, transistors M8 and M9 are both N-type transistors. In other embodiments, the transistors M8 and M9 are P-type transistors.

In the present embodiment, the row selection signal CSL is generated by the logic circuit 340. The logic circuit 340 is based on the row address AR_RAnd column address AR_CThe row selection signal CSL is generated. For example, when the column address AR_RWord line WL₁And column address AR_CDirected to access lines AL₁When enabled, the logic circuit 340 enables the row select signal CSL. However, when the row address AR_RNon-oriented word line WL₁Or a row address AR_CNot directed to access line AL₁When not enabled, the logic circuit 340 does not enable the row selection signal CSL.

The present invention is not limited to the architecture of the logic circuit 340. In the present embodiment, the logic circuit 340 has logic gates 451-453. The logic gate 451 generates a level L2 based on the level L1. In the present embodiment, the level L1 is opposite to the level L2. For example, when level L1 is high, level L2 is low. When level L1 is a low level, level L2 is a high level. In one embodiment, the logic gate 451 is an inverter.

The logic gate 452 has input terminals IN1 and IN2, a selection terminal SEL and an output terminal OT. Input deviceTerminal IN1 receives level L1. The input IN2 is coupled to the logic gate 451 and receives the level L2. The selection terminal SEL is used for receiving the row address AR_R. When line address AR_RWord line WL₁The output terminal OT outputs the level L1. When line address AR_RNot to the word line WL₁The output terminal OT outputs the level L2. In one embodiment, the logic gate 452 is a selector, such as a multiplexer.

Logic gate 453 is coupled to output OT and receives column address AR_C. When the output of the logic gate 452 is at the level L1 (i.e., the column address AR)_RWord line WL₁) And column address AR_CDirected to access lines AL₁Logic gate 453 enables row select signal CSL to turn on switches 441 and 442. However, when the output of the logic gate 452 is at level L2 (i.e., the column address AR)_RNon-oriented word line WL₁) Or a row address AR_CNot directed to access line AL₁When not enabled, the logic gate 453 does not enable the row select signal CSL. In one possible embodiment, logic gate 453 is an AND gate (AND gate).

The buffer circuit 450 is used to enhance the path PA₁The above data. In the present embodiment, the buffer circuit 450 includes transistors M10 and M11. The gate of the transistor M10 receives a control signal MDQE, and the first source/drain thereof is coupled to the switch 441 and the second source/drain thereof is coupled to the amplifying circuit 460. The gate of the transistor M11 receives a control signal MDQE, the first source/drain of which is coupled to the switch 442, and the second source/drain of which is coupled to the amplifying circuit 460. In other embodiments, the buffer circuit 450 may be omitted. In this example, the switch circuit 440 is directly coupled to the amplifying circuit 460.

The amplifying circuit 460 is coupled between the buffer circuit 450 and the reading circuit 470. When the buffer circuit 450 is omitted, the amplifying circuit 460 is coupled between the switch circuit 440 and the reading circuit 470. In the present embodiment, the current path PA₁When turned on, the amplification circuit 460 amplifies the signals on the bit lines BL and/BL and provides the amplified result to the read circuit 470. The present invention is not limited to the architecture of the amplifier circuit 460. In one embodiment, the amplifying circuit 460 is a Sense Amplifier (SA) or a differential amplifier.

Reading electricityThe circuit 470 generates a data DQ according to the voltage difference of the bit lines BL and/BL₁To access line AL₁. In one possible embodiment, the data DQ₁Buffered in a buffer circuit (e.g., 250). In other embodiments, read circuit 470 is based on access line AL₁The data on the bit lines BL and/BL, a differential signal pair is generated.

FIG. 4B is another schematic diagram of a memory cell of the present invention. Fig. 4B is similar to fig. 4A, except that the control signal MDQE of fig. 4B is generated by a logic circuit 340. In other words, in fig. 4A, the logic circuit 340 determines whether to enable the switch circuit 440, and in fig. 4B, the logic circuit 340 determines whether to enable the buffer circuit 450. In the present embodiment, the logic circuit 340 is based on the row address AR_RAnd column address AR_CA control signal MDQE is generated. For example, when the column address AR_RWord line WL₁And column address AR_CDirected to access lines AL₁When enabled, the logic circuit 340 enables the control signal MDQE to turn on the transistors M10 and M11. Thus, path PA₁Is turned on. When line address AR_RNon-oriented word line WL₁Or a row address AR_CNot directed to access line AL₁When not enabled, the logic circuit 340 does not enable the control signal MDQE. Thus, transistors M10 and M11 are non-conductive.

The row select signal CSL received by the switch circuit 440 may be generated by the column decoder 232 of fig. 2. In this example, the column decoder 232 is based on the external address AR_EThe row select signal CSL is enabled or not enabled. For example, when the external address AR_EPointing to a storage element CE₁When asserted, the column decoder 232 enables the row select signal CSL. Accordingly, the switch circuit 440 transmits the signals of the bit lines BL and/BL to the buffer circuit 450. When the external address AR_ENon-pointed to storage unit CE₁While, the column decoder 232 does not enable the row select signal CSL. Therefore, the switch circuit 440 stops transmitting the signals of the bit lines BL and/BL to the buffer circuit 450.

Fig. 5 is a schematic flow chart of a control method according to the present invention. The control method is suitable for a memory chip.

First, an external address is decoded to generate a row address and a column address (step S511).

It is determined whether the row address points to the first word line and the column address points to an access line (step S512). In one embodiment, step S512 is to determine whether the column address points to the first word line according to a logic value of at least one specific bit of the column address. In another embodiment, step S512 is to determine whether the column address points to the access line according to a logic value of at least one specific bit of the column address.

When the row address points to the first word line and the column address points to the access line, a first path between the first memory cell and the access line is turned on, so that the first memory cell outputs data to the access line through the first path (step S513). In one embodiment, step S513 does not turn on a second path between the second memory cell and the access line. Therefore, the second memory cell does not output data to the access line. In other embodiments, step S513 may provide an access signal to the first word line and a refresh signal to the second word line. Therefore, the first memory cell coupled to the first word line performs an access operation, and the second memory cell coupled to the second word line performs a refresh operation.

When the row address does not point to the first word line or the column address does not point to the access line, the first path is not turned on (step S514). Therefore, the first memory cell does not transmit data to the access line through the first path. In one embodiment, step S514 further provides a refresh signal to the first word line. Therefore, the first memory cell performs a refresh operation.

Then, whether the row address points to the second word line and the column address points to the access line (step S515). When the row address points to the second word line and the column address points to the access line, a second path between the second memory cell and the access line is turned on, so that the second memory cell outputs data to the access line through the second path (step S516). In one possible embodiment, step S516 does not turn on the first path between the first memory cell and the access line. Therefore, the first memory cell does not output data to the access line. In other embodiments, step S516 further provides an access signal to the second word line and a refresh signal to the first word line. Therefore, the first memory cell coupled to the first word line performs the refresh operation, and the second memory cell coupled to the second word line performs the access operation.

When the row address does not point to the second word line or the column address does not point to the access line, the second path is not turned on (step S517). Therefore, the second memory cell does not transmit data to the access line through the second path. In one embodiment, step S517 further provides a refresh signal to the second word line. Therefore, the second memory cell performs a refresh operation.

In other embodiments, when neither the first nor the second memory cell performs the refresh operation within a predetermined period, the refresh signal is provided to the first or the second word line, so that the first or the second memory cell performs the refresh operation.

Claims

1. A memory chip, comprising:

at least one database comprising:

a first sub-database including a first memory cell coupled to a first word line and a first access line, and outputting data to the first access line through a first path; and

a second sub-database including a second memory cell coupled to a second word line and the first access line and outputting data to the first access line through a second path;

an address decoding circuit for decoding an external address to generate a row address and a column address; and

a control circuit for controlling the first path and the second path according to the row address and the column address;

wherein the control circuit turns on the first path and does not turn on the second path when the row address points to the first word line and the column address points to the first access line.

2. The memory chip of claim 1, wherein the control circuit does not turn on the first path when the row address does not point to the first word line or the column address does not point to the first access line, wherein the control circuit does not turn on the first path and turns on the second path when the row address points to the second word line and the column address points to the first access line.

3. The memory chip of claim 1, wherein the control circuit comprises:

a selection circuit for providing an access signal to the first word line and providing a refresh signal to the second word line when the row address points to the first word line; and

a logic circuit, when the first word line receives the access signal and the column address points to the first access line, turning on the first path and turning off the second path, so that the second memory cell performs a refresh operation.

4. The memory chip of claim 3, wherein the logic circuit comprises:

a first multiplexer having a first output, said first output outputting a first level when said selection circuit provides said access signal to said first wordline, said first output outputting a second level when said selection circuit provides said refresh signal to said first wordline, said first level being opposite to said second level;

a second multiplexer having a second output, said second output outputting said second level when said selection circuit provides said refresh signal to said second wordline, said second output outputting said first level when said selection circuit provides said access signal to said second wordline;

a first logic gate coupled to the first output terminal, receiving the row address, and turning on or off the first path; and

a second logic gate coupled to the second output terminal and receiving the row address for turning on or off the second path.

5. The memory chip of claim 3, further comprising:

a first amplifying circuit for amplifying a voltage difference between a first bit line and a second bit line coupled to the first memory cell to generate a first amplified data;

a switch circuit coupled to the first amplifying circuit and determining whether to transmit the first amplified data according to a row selection signal, wherein the switch circuit transmits the first amplified data when the row selection signal is enabled, and does not transmit the first amplified data when the row selection signal is not enabled; and

a second amplifying circuit for amplifying the first amplified data transmitted by the switching circuit, wherein the logic circuit generates the row selection signal according to the row address and the column address, the logic circuit enables the row selection signal when the row address points to the first word line and the column address points to the first access line, and the logic circuit disables the row selection signal when the row address does not point to the first word line or the column address does not point to the first access line.

6. The memory chip of claim 3, further comprising:

a switch circuit coupled to the first amplifying circuit and determining whether to transmit the first amplified data according to a row selection signal, wherein the switch circuit transmits the first amplified data when the row selection signal is enabled, and does not transmit the first amplified data when the row selection signal is not enabled;

a second amplifying circuit for amplifying the first amplified data transmitted from the switching circuit; and

a buffer circuit, coupled between the switch circuit and the second amplifying circuit, for determining whether to transmit the first amplified data transmitted by the switch circuit to the second amplifying circuit according to a control signal;

wherein the logic circuit generates the control signal according to the row address and the column address, the logic circuit enables the control signal to command the buffer circuit to transmit the first amplification data transmitted by the switch circuit to the second amplification circuit when the row address points to the first word line and the column address points to the first access line, and the logic circuit disables the control signal to command the buffer circuit to stop transmitting the first amplification data transmitted by the switch circuit to the second amplification circuit when the row address does not point to the first word line or the column address does not point to the first access line.

7. The memory chip of claim 3, further comprising:

a refresh counter for generating the refresh signal, wherein the address decoding circuit decodes the external address to generate the access signal;

wherein the address decoding circuit comprises:

a row decoder for decoding the external address to generate the row address; and

a column decoder for decoding the external address to generate the column address.

8. The memory chip of claim 3, further comprising:

a command decoding circuit for decoding a command; and

a command address bus for providing the command to the command decoding circuit and the external address to the address decoding circuit;

wherein the selection circuit provides the refresh signal to the first word line when the refresh operation is not performed on the first memory cell during a predetermined period, so that the refresh operation is performed on the first memory cell.

9. A control method for a memory chip, the memory chip having a database, the database having a first sub-database and a second sub-database, the first sub-database having a first memory cell, the second sub-database having a second memory cell, the first memory cell being coupled to a first word line and an access line, the second memory cell being coupled to a second word line and the access line, the control method comprising:

decoding an external address to generate a row address and a column address;

when the row address points to the first word line and the column address points to the access line:

providing an access signal to the first word line and providing a refresh signal to the second word line;

turning on a first path to enable the first storage unit to output data to the access line through the first path; and

and a second path is not conducted, so that the second storage unit does not output data to the access line through the second path.

10. The control method of claim 9, wherein when the row address points to the second memory cell and the column address points to the access line:

providing the access signal to the second word line;

providing the refresh signal to the first word line;

turning on the second path and turning off the first path, wherein the second memory cell outputs data to the access line through the second path, and the first memory cell does not output data to the access line through the first path; and

in a predetermined period, when the first memory cell does not perform a refresh operation, the refresh signal is provided to the first word line, so that the first memory cell performs the refresh operation.