CN111816650B - SCR electrostatic protection structure and its forming method - Google Patents

Abstract

An SCR electrostatic protection structure and a forming method thereof, the structure comprises: an N-type well in the semiconductor substrate; a plurality of discrete first-to Q-th-stage main units located in the N-type well; the kth stage main unit includes: an N-type doped region located at the top of the k-th cell region of the N-type well; the first P-type doped region is positioned at the top part in the k unit region of the N-type well, is positioned at the side part of the N-type doped region and is separated from the N-type doped region; the second P-type doped region is positioned in the k unit region of the N-type well, is positioned at the bottom of the first P-type doped region and is adjacent to the first P-type doped region, and extends to the bottom of the N-type doped region and is adjacent to the N-type doped region; the N-type doped region in the first-stage main unit is electrically connected with the first P-type doped region in the Q-th-stage main unit, and the first P-type doped region in the i-1-stage main unit is electrically connected with the N-type doped region in the i-th-stage main unit. The performance of the structure is improved.

Description

SCR electrostatic protection structure and its forming method

technical field

The invention relates to the field of electrostatic protection, in particular to an SCR electrostatic protection structure and a forming method thereof.

Background technique

In the production and application of integrated circuit chips, with the continuous improvement of VLSI process technology, the current CMOS integrated circuit production technology has entered the deep submicron stage, the size of MOS devices is continuously reduced, and the thickness of the gate oxide layer is getting higher and higher. Thinner and thinner, the withstand voltage capability of MOS devices is significantly reduced, and the harm of electrostatic discharge (Electrostatic Discharge, ESD) to integrated circuits has become more and more significant. Therefore, ESD protection for integrated circuits becomes particularly important.

In order to strengthen the protection against static electricity, an electrostatic protection circuit is usually connected to the input and output interface (I/O pad) of the chip. The electrostatic protection circuit is a discharge path for the internal circuit in the chip to provide electrostatic current, so as to avoid static electricity from distorting the internal of the chip. Circuit breakdown.

However, the performance of existing electrostatic protection structures is poor.

Contents of the invention

The problem to be solved by the present invention is to provide an SCR electrostatic protection structure and a forming method thereof, so as to improve the performance of the SCR electrostatic protection structure.

In order to solve the above problems, the present invention provides an SCR electrostatic protection structure, comprising: a semiconductor substrate; an N-type well located in the semiconductor substrate, the N-type well comprising several discrete first unit regions to the Qth unit region, Q is an integer greater than or equal to 3; several discrete first-level main units to Q-level main units located in the N-type well, the k-level main unit is located in the k-th unit area, and k is greater than or equal to 1 and less than Integer equal to Q; the k-level main unit includes: an N-type doped region at the top of the k-th unit region of the N-type well; a first P-type doped region at the top of the k-th unit region of the N-type well Doped region, the first P-type doped region is located at the side of the N-type doped region and is separated from the N-type doped region; the second P-type doped region located in the kth unit region of the N-type well region, the second P-type doped region is located at the bottom of the first P-type doped region and is adjacent to the first P-type doped region, and the second P-type doped region also extends to the bottom of the N-type doped region and is connected to the N-type doped region The doped regions are adjacent; the N-type doped region in the first-level main unit is electrically connected to the first P-type doped region in the Q-th level main unit, and the first P-type doped region in the i-1-th level main unit The region is electrically connected to the N-type doped region in the i-level main unit, i is an integer greater than or equal to 3 and less than or equal to Q; the first P-type doped region in the first-level main unit is used to connect to the anode potential, and the first The N-type doped region in the secondary main unit is used to connect to the cathode potential.

Optionally, the concentration of P-type ions in the second P-type doped region is lower than the concentration of P-type ions in the first P-type doped region.

Optionally, further comprising: a silicide barrier layer located on the surface of the semiconductor substrate between the N-type doped region and the first P-type doped region.

Optionally, it further includes: an isolation layer located in the semiconductor substrate between the jth unit region and the j+1th unit region, where j is an integer greater than or equal to 1 and less than or equal to Q−1.

Optionally, the bottom surface of the isolation layer is lower than the bottom surface of the second P-type doped region and higher than the bottom surface of the N-type well.

Optionally, it also includes: a first connection line located on the semiconductor substrate, the first connection line electrically connects the N-type doped region in the first-level main unit and the first P-type doped region in the Q-th level main unit. doped area.

Optionally, it also includes: an i-2th level connection line located on the semiconductor substrate, the i-2th level connection line electrically connects the first P-type doped region in the i-1th level main unit and the The N-type doped region in the i-level main unit.

Optionally, there are substrate trap ions in the semiconductor substrate, and the conductivity type of the substrate trap ions is P type.

The present invention also provides a method for forming an SCR electrostatic protection structure, comprising: providing a semiconductor substrate; forming an N-type well in the semiconductor substrate, the N-type well including several discrete first unit regions to Qth unit regions, Q is an integer greater than or equal to 3; several discrete first-level main units to Q-level main units are formed in the N-type well, and the k-level main unit is located in the k-th unit area, and k is greater than or equal to 1 and less than An integer equal to Q; the method for forming the kth level main unit includes: forming an N-type doped region at the top of the kth unit region of the N-type well; A P-type doped region, the first P-type doped region is located at the side of the N-type doped region and is separated from the N-type doped region; a second P-type doped region is formed in the kth unit region of the N-type well type doped region, the second P-type doped region is located at the bottom of the first P-type doped region and is adjacent to the first P-type doped region, the second P-type doped region also extends to the bottom of the N-type doped region and Adjacent to the N-type doped region; the N-type doped region in the first-level main unit is electrically connected to the first P-type doped region in the Q-th level main unit, and the first P in the i-1-th level main unit The N-type doped region is electrically connected to the N-type doped region in the i-level main unit, i is an integer greater than or equal to 3 and less than or equal to Q; the first P-type doped region in the first-level main unit is used to connect to the anode Potential, the N-type doped region in the second-level main unit is used to connect to the cathode potential.

Optionally, the concentration of P-type ions in the second P-type doped region is lower than the concentration of P-type ions in the first P-type doped region.

Optionally, the method further includes: forming a silicide barrier layer on the surface of the semiconductor substrate between the N-type doped region and the first P-type doped region.

Optionally, it also includes: before forming the first-level main unit to the Q-th level main unit, an isolation layer in the semiconductor substrate between the j-th unit area and the j+1-th unit area, where j is greater than or equal to 1 and an integer less than or equal to Q-1.

Optionally, the bottom surface of the isolation layer is lower than the bottom surface of the second P-type doped region and higher than the bottom surface of the N-type well.

Optionally, it also includes: forming a first connection line on the semiconductor substrate, the first connection line electrically connects the N-type doped region in the first-level main unit and the first P-type doped region in the Q-th level main unit. doped area.

Optionally, it also includes: forming an i-2th level connection line on the semiconductor substrate, the i-2th level connection line electrically connects the first P-type doped region in the i-1th level main unit and the The N-type doped region in the i-level main unit.

Optionally, there are substrate trap ions in the semiconductor substrate, and the conductivity type of the substrate trap ions is P type.

Compared with the prior art, the technical solution of the present invention has the following advantages:

In the SCR electrostatic protection structure provided by the technical solution of the present invention, the SCR electrostatic protection structure has a current discharge structure that is a PNPN structure, and the current discharge structure includes a PNP tube and an NPN tube, the first P-type doped region in the first-level main unit and The second P-type doped region at the bottom of the first P-type doped region in the first-level main unit is used as the emitter of the PNP transistor, which is located in the second P-type doped region in the first-level main unit and the second-level main unit The N-type well at the bottom of the second P-type doped region is used as the base of the PNP transistor, and the second P-type doped region at the bottom of the N-type doped region in the second-level main unit is used as the collector of the PNP transistor. The second P-type doped region in the first-level main unit and the N-type well at the bottom of the second P-type doped region in the second-level main unit are used as the collector of the NPN transistor, located at the bottom of the N-type doped region in the second-level main unit The second P-type doped region is used as the base of the NPN transistor, and the N-type doped region in the second-level main unit is used as the emitter of the NPN transistor. The current discharge structure has a current discharge path. The N-type doped regions and the first P-type doped regions in the main units of each level are connected in series to form a diode series ring. The diode series ring has a diode conduction path. The conduction path of the diode is: from the first P-type doped region in the first-level main unit through the second P-type doped region in the first-level main unit to the N-type doped region in the first-level main unit, From the N-type doped region in the first-level main unit to the first P-type doped region in the Q-level main unit, from the first P-type doped region in the Q-level main unit through the Q-level main unit From the second P-type doped region in the Qth-level main unit to the N-type doped region in the Q-level main unit, from the N-type doped region in the i-level main unit to the first P-type doped region in the i-1-th level main unit The doped region, from the first P-type doped region in the i-1th level main unit through the second P-type doped region in the i-1th level main unit to the N-type doped area in the i-1th level main unit doped region, up to the N-type doped region in the second-level main unit.

The trigger voltage is applied on the cathode and anode, firstly the diode series loop is turned on, because the diode series loop is turned on, so for the NPN tube of the current discharge structure, the N-type doped region in the second-level main unit and the second-level main unit The second P-type doped region in the unit is forward-biased, and the base of the NPN transistor has current, that is, the second P-type doped region in the second-level main unit has current, so the NPN of the current discharge structure The tube is turned on, so that electrons pass through the second P-type doped region in the second-level main unit from the N-type doped region in the second-level main unit to the bottom of the second P-type doped region in the second-level main unit N-type well, the potential of the N-type well at the bottom of the second P-type doped region in the second-level main unit is reduced like this, reducing the potential of the N-type well at the bottom of the second P-type doped region in the second-level main unit, That is to say, the base potential of the PNP transistor in the current discharge structure is reduced, and the PNP transistor is promoted to be turned on, so that the current discharge structure is turned on. The trigger voltage of the SCR electrostatic protection structure is reduced.

Secondly, the second P-type doped region is a part of the diode series ring. Since the second P-type doped region is provided, the Darlington effect of the diode series ring is effectively suppressed and the leakage is reduced.

Again, the first-level main unit to the Q-level main unit are all in the same N-type well, so that the first-level main unit to the Q-level main unit are arranged compactly, and the integration degree of the SCR electrostatic protection structure is improved.

Thirdly, the current discharge structure in the SCR electrostatic protection structure is composed of a parasitic PNP tube and a parasitic NPN tube, and there is no other SCR structure connected to the diode series ring, so as to avoid the diversification of the current discharge structure type, thereby avoiding the SCR The electrostatic protection structure is triggered multiple times during operation to avoid the problem of secondary reset.

Description of drawings

1 to 3 are structural schematic diagrams of the formation process of the SCR electrostatic protection structure in an embodiment of the present invention.

Detailed ways

As mentioned in the background art, the performance of the existing SCR electrostatic protection structure is poor.

There are two important parameters in the SCR electrostatic protection structure, namely holding voltage and trigger voltage. For some SCR electrostatic protection structures used for low-voltage device protection, the holding voltage of the SCR electrostatic protection structure can usually meet the requirements, but the trigger voltage is relatively high, so the trigger voltage of the SCR electrostatic protection structure needs to be reduced.

On this basis, the present invention provides an SCR electrostatic protection structure, comprising: an N-type well located in a semiconductor substrate, the N-type well includes several discrete first unit regions to the Qth unit region, and Q is greater than or equal to 3 Integer; several discrete first-level main units to Q-level main units located in the N-type well, the k-level main unit is located in the k-th unit area; the k-level main unit includes: the k-th unit located in the N-type well The N-type doped region at the top of the region; the first P-type doped region at the top of the kth unit region of the N-type well, the first P-type doped region is located at the side of the N-type doped region and The N-type doped region is separated; the second P-type doped region located in the kth cell region of the N-type well, the second P-type doped region is located at the bottom of the first P-type doped region and is connected to the first P-type doped region. The doped regions are adjacent, and the second P-type doped region also extends to the bottom of the N-type doped region and is adjacent to the N-type doped region; the N-type doped region in the first-level main unit and the Q-level main unit The first P-type doped region is electrically connected, the first P-type doped region in the i-1th level main unit is electrically connected to the N-type doped region in the i-level main unit, and i is greater than or equal to 3 and less than An integer equal to Q. The performance of the SCR electrostatic protection structure is improved.

In order to make the above objects, features and advantages of the present invention more comprehensible, specific embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings.

1 to 3 are structural schematic diagrams of the formation process of the SCR electrostatic protection structure in an embodiment of the present invention.

Referring to FIG. 1 , a semiconductor substrate 200 is provided.

The semiconductor substrate 200 has substrate trap ions, and the conductivity type of the substrate trap ions is P type.

The material of the semiconductor substrate 200 includes single crystal silicon, single crystal germanium or single crystal silicon germanium.

Referring to FIG. 2 , an N-type well 210 is formed in a semiconductor substrate 200 .

The N-type well 210 includes several discrete first to Qth unit regions, where Q is an integer greater than or equal to 3.

In this embodiment, taking Q as 3 as an example, the N-type well 210 includes several discrete first unit regions, second unit regions and third unit regions.

In this embodiment, it further includes: forming an isolation layer 201 in the semiconductor substrate, and the isolation layer 201 is used for isolating adjacent main units formed subsequently.

The isolation layer 201 is located in the semiconductor substrate 200 between the j th unit area and the j+1 th unit area.

Wherein, j is an integer greater than or equal to 1 and less than or equal to Q-1.

The bottom surface of the isolation layer 201 is higher than the bottom surface of the N-type well 210 , and the bottom surface of the isolation layer 201 is lower than the bottom surface of the subsequent second P-type doped region.

Referring to FIG. 3 , several discrete first-level main cells to Qth-level main cells are formed in the N-type well 210 .

The kth level main unit is located in the kth unit area, and k is an integer greater than or equal to 1 and less than or equal to Q.

The method for forming the kth level main unit includes: forming an N-type doped region 220 at the top of the kth unit region of the N-type well 210; forming a first P Type doped region 230, the first P-type doped region 230 is located at the side of the N-type doped region 220 and is separated from the N-type doped region 220; formed in the kth unit region of the N-type well 210 The second P-type doped region 240, the second P-type doped region 240 is located at the bottom of the first P-type doped region 230 and is adjacent to the first P-type doped region 230, and the second P-type doped region 240 also extends to The bottom of the N-type doped region 220 is adjacent to the N-type doped region 220 .

The N-type doped region 220 in the first-level main unit is electrically connected to the first P-type doped region 230 in the Q-th level main unit, and the first P-type doped region 230 in the i-1-th level main unit is connected to The N-type doped region 220 in the i-level main unit is electrically connected, i is an integer greater than or equal to 3 and less than or equal to Q; the first P-type doped region 230 in the first-level main unit is used to connect to the anode potential, and the first P-type doped region 230 is used to connect to the anode potential. The N-type doped region 220 in the secondary main unit is used to connect to the cathode potential.

The concentration of P-type ions in the second P-type doped region 240 is lower than the concentration of P-type ions in the first P-type doped region 230 , which facilitates the formation of a current drain structure.

The concentration of P-type ions in the second P-type doped region 240 is smaller than the concentration of P-type ions in the first P-type doped region 230 and greater than or equal to the concentration of substrate well ions in the semiconductor substrate 200 .

In a specific embodiment, the concentration of P-type ions in the second P-type doped region 240 is 3/5˜1/20 of the concentration of P-type ions in the first P-type doped region 230 .

The method for forming the SCR electrostatic protection structure further includes: forming a silicide barrier layer 250 on the surface of the semiconductor substrate 200 between the N-type doped region 220 and the first P-type doped region 230 .

The function of the silicide barrier layer 250 includes: avoiding the formation of metal silicide material on the surface of the semiconductor substrate 200 between the N-type doped region 220 and the first P-type doped region 230, preventing the N-type doped region 220 Short circuit with the first P-type doped region 230 .

The material of the silicide barrier layer 250 is insulating material.

It should be noted that both the surface of the N-type doped region 220 and the surface of the first P-type doped region 230 have a metal silicide layer.

The method for forming the SCR electrostatic protection structure further includes: forming a first connection line on the semiconductor substrate 200, the first connection line electrically connects the N-type doped region 220 in the first-level main unit and the Q-level main unit. The first P-type doped region 230 in the cell.

One end of the first connection line is connected to the metal silicide layer on the surface of the N-type doped region 220 in the first-level main unit, and the other end of the first connection line is connected to the first P-type doped region 230 in the Q-th level main unit. Surface metal silicide layer.

The method for forming the SCR electrostatic protection structure further includes: forming an i-2th level connection line on the semiconductor substrate 200, and the i-2th level connection line is electrically connected to the first P in the i-1th level main unit. The N-type doped region 230 and the N-type doped region 220 in the i-th level main unit.

One end of the i-2th level connecting wire is connected to the metal silicide layer on the surface of the first P-type doped region 230 in the i-1th level main unit, and the other end of the i-2th level connecting line is connected to the i-th level main unit The metal silicide layer on the surface of the N-type doped region 220 in the.

The present invention also provides an SCR electrostatic protection structure formed by the above method, please refer to Figure 3, including:

a semiconductor substrate 200;

An N-type well 210 located in the semiconductor substrate 200, the N-type well 210 includes several discrete first unit regions to Qth unit regions, and Q is an integer greater than or equal to 3;

Several discrete first-level main units to Q-level main units located in the N-type well 210, the k-level main unit is located in the k-th unit area, and k is an integer greater than or equal to 1 and less than or equal to Q;

The kth level main unit includes: an N-type doped region 220 located at the top of the kth unit region of the N-type well 210; a first P-type doped region located at the top of the kth unit region of the N-type well 210 Region 230, the first P-type doped region 230 is located at the side of the N-type doped region 220 and is separated from the N-type doped region 220; the second P-type region located in the kth unit region of the N-type well 210 type doped region 240, the second P-type doped region 240 is located at the bottom of the first P-type doped region 230 and is adjacent to the first P-type doped region 230, and the second P-type doped region 240 also extends to the N-type doped region. The bottom of the impurity region 220 is adjacent to the N-type doped region 220;

The N-type doped region 220 in the first-level main unit is electrically connected to the first P-type doped region 230 in the Q-th level main unit, and the first P-type doped region 230 in the i-1-th level main unit is connected to The N-type doped region 220 in the i-level main unit is electrically connected, i is an integer greater than or equal to 3 and less than or equal to Q; the first P-type doped region 230 in the first-level main unit is used to connect to the anode potential, and the first P-type doped region 230 is used to connect to the anode potential. The N-type doped region 220 in the secondary main unit is used to connect to the cathode potential.

The concentration of P-type ions in the second P-type doped region 240 is smaller than the concentration of P-type ions in the first P-type doped region 230 .

The SCR electrostatic protection structure further includes: a silicide barrier layer 250 located on the surface of the semiconductor substrate 200 between the N-type doped region 220 and the first P-type doped region 230 .

The SCR electrostatic protection structure further includes: an isolation layer 201 located in the semiconductor substrate 200 between the j th unit area and the j+1 th unit area, where j is an integer greater than or equal to 1 and less than or equal to Q−1.

The bottom surface of the isolation layer 201 is lower than the bottom surface of the second P-type doped region 240 and higher than the bottom surface of the N-type well 210 .

The SCR electrostatic protection structure also includes: a first connection line located on the semiconductor substrate 200, the first connection line electrically connects the N-type doped region 220 in the first-level main unit and the Q-th level main unit. The first P-type doped region 230 .

The SCR electrostatic protection structure further includes: the i-2th level connection line located on the semiconductor substrate 200, the i-2th level connection line is electrically connected to the first P-type doped in the i-1th level main unit The region 230 and the N-type doped region 220 in the i-th level main unit.

The semiconductor substrate 200 has substrate trap ions, and the conductivity type of the substrate trap ions is P type.

In the SCR electrostatic protection structure in this embodiment, the SCR electrostatic protection structure has a current discharge structure which is a PNPN structure, and the current discharge structure includes a PNP transistor and an NPN transistor, the first P-type doped region 230 and the The second P-type doped region 240 at the bottom of the first P-type doped region 230 in the first-level main unit is used as the emitter of the PNP transistor, and is located between the second P-type doped region 240 and the second-level PNP in the first-level main unit. The N-type well 210 at the bottom of the second P-type doped region 240 in the main unit is used as the base of the PNP transistor, and the second P-type doped region 240 at the bottom of the N-type doped region 220 in the second-level main unit is used as a PNP transistor. The collector of the second P-type doped region 240 in the first-level main unit and the N-type well 210 at the bottom of the second P-type doped region 240 in the second-level main unit are used as the collector of the NPN transistor, located in the second The second P-type doped region 240 at the bottom of the N-type doped region 220 in the first-level main unit serves as the base of the NPN transistor, and the N-type doped region 220 in the second-level main unit serves as the emitter of the NPN transistor. The current discharge structure has a current discharge path L1. The N-type doped regions and the first P-type doped regions in the main units of each level are connected in series to form a diode series ring. The diode series ring has a diode conduction path. The conduction path of the diode is: from the first P-type doped region 230 in the first-level main unit through the second P-type doped region 240 in the first-level main unit to the N-type doped region in the first-level main unit Region 220, from the N-type doped region 220 in the first-level main unit to the first P-type doped region 230 in the Q-level main unit, from the first P-type doped region 230 in the Q-level main unit Pass through the second P-type doped region 240 in the Q-level main unit to the N-type doped region 220 in the Q-level main unit, from the N-type doped region in the i-level main unit to the i-1th level The first P-type doped region 230 in the main unit passes from the first P-type doped region 230 in the i-1th level main unit through the second P-type doped region 240 in the i-1th level main unit to The N-type doped region 220 in the main unit of the i-1th level reaches the N-type doped region 220 in the second-level main unit.

The trigger voltage is applied on the cathode and the anode, first the diode series ring conducts, because the diode series ring conducts, so for the NPN tube of the current discharge structure, the N-type doped region 220 in the second-level main unit and the second-level The second P-type doped region 240 in the main unit is forward-biased, and there is current in the base of the NPN transistor, that is, there is current in the second P-type doped region 240 in the second-level main unit, so the current discharges The NPN transistor of the structure is turned on, so that electrons pass through the second P-type doped region 240 in the second-level main unit from the N-type doped region 220 in the second-level main unit to the second P-type doped region in the second-level main unit. The N-type well 210 at the bottom of the doped region 240, so that the potential of the N-type well 210 at the bottom of the second P-type doped region 240 in the second-level main unit is reduced, reducing the second P-type doping in the second-level main unit. The potential of the N-type well 210 at the bottom of the region 240, that is to say, reduces the base potential of the PNP transistor in the current discharge structure, prompting the PNP transistor to be turned on, so that the current discharge structure is turned on. The trigger voltage of the SCR electrostatic protection structure is reduced.

Secondly, the second P-type doped region 240 is a part of the diode series ring. Since the second P-type doped region 240 is provided, the Darlington effect of the diode series ring is effectively suppressed and leakage current is reduced.

Again, the first-level main unit to the Q-level main unit are all in the same N-type well 210 , so that the first-level main unit to the Q-level main unit are arranged compactly, and the integration degree of the SCR electrostatic protection structure is improved.

Thirdly, the current discharge structure in the SCR electrostatic protection structure is composed of a parasitic PNP tube and a parasitic NPN tube, and there is no other SCR structure connected to the diode series ring, so as to avoid the diversification of the current discharge structure type, thereby avoiding the SCR The electrostatic protection structure is triggered multiple times during operation to avoid the problem of secondary reset.

The SCR electrostatic protection structure of this embodiment can be used to protect low-voltage devices, and the trigger voltage of the SCR electrostatic protection structure is relatively low.

Although the present invention is disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, so the protection scope of the present invention should be based on the scope defined in the claims.

Claims (16)

1. A SCR electrostatic protection structure, characterized in that, comprising: semiconductor substrate; An N-type well located in a semiconductor substrate, the N-type well includes a plurality of discrete first unit regions to Qth unit regions, and Q is an integer greater than or equal to 3; Several discrete first-level main units to Q-level main units located in the N-type well, the k-level main unit is located in the k-th unit area, and k is an integer greater than or equal to 1 and less than or equal to Q; The k-th level main unit includes: an N-type doped region located at the top of the k-th unit region of the N-type well; a first P-type doped region located at the top of the k-th unit region of the N-type well, A P-type doped region is located on the side of the N-type doped region and is separated from the N-type doped region; a second P-type doped region located in the kth unit region of the N-type well, the second P The type doped region is located at the bottom of the first P-type doped region and is adjacent to the first P-type doped region, and the second P-type doped region also extends to the bottom of the N-type doped region and is adjacent to the N-type doped region; The N-type doped region in the first-level main unit is electrically connected to the first P-type doped region in the Q-level main unit, and the first P-type doped region in the i-1-th level main unit is connected to the i-th level The N-type doped region in the main unit is electrically connected, i is an integer greater than or equal to 3 and less than or equal to Q; the first P-type doped region in the first-level main unit is used to connect to the anode potential, and the second-level main unit The N-type doped region is used to connect to the cathode potential. 2 . The SCR electrostatic protection structure according to claim 1 , wherein the concentration of P-type ions in the second P-type doped region is lower than the concentration of P-type ions in the first P-type doped region. 3 . 3. The SCR electrostatic protection structure according to claim 1, further comprising: a silicide barrier layer on the surface of the semiconductor substrate between the N-type doped region and the first P-type doped region . 4. The SCR electrostatic protection structure according to claim 1, further comprising: an isolation layer located in the semiconductor substrate between the j-th unit area and the j+1-th unit area, where j is greater than or equal to 1 and An integer less than or equal to Q-1. 5. The SCR electrostatic protection structure according to claim 4, wherein the bottom surface of the isolation layer is lower than the bottom surface of the second P-type doped region and higher than the bottom surface of the N-type well. 6. The SCR electrostatic protection structure according to claim 1, further comprising: a first connection line located on the semiconductor substrate, the first connection line is electrically connected to the N-type doped The impurity region and the first P-type doping region in the Qth level main unit. 7. The SCR electrostatic protection structure according to claim 1, further comprising: the i-2th level connecting wire located on the semiconductor substrate, the i-2th level connecting wire is electrically connected to the i-1th level The first P-type doped region in the i-th level main unit and the N-type doped region in the i-th level main unit. 8 . The SCR electrostatic protection structure according to claim 1 , wherein the semiconductor substrate has substrate trap ions, and the conductivity type of the substrate trap ions is P type. 9. A method for forming an SCR electrostatic protection structure, comprising: Provide semiconductor substrates; An N-type well is formed in a semiconductor substrate, the N-type well includes a plurality of discrete first unit regions to Qth unit regions, and Q is an integer greater than or equal to 3; Forming several discrete first-level main units to Q-level main units in the N-type well, the k-level main unit is located in the k-th unit area, and k is an integer greater than or equal to 1 and less than or equal to Q; The method for forming the kth level main unit includes: forming an N-type doped region at the top of the k-th unit region of the N-type well; forming a first P-type doped region at the top of the k-th unit region of the N-type well region, the first P-type doped region is located at the side of the N-type doped region and is separated from the N-type doped region; a second P-type doped region is formed in the kth unit region of the N-type well, The second P-type doped region is located at the bottom of the first P-type doped region and is adjacent to the first P-type doped region, and the second P-type doped region also extends to the bottom of the N-type doped region and is doped with the N-type doped region. District adjacency; The N-type doped region in the first-level main unit is electrically connected to the first P-type doped region in the Q-level main unit, and the first P-type doped region in the i-1-th level main unit is connected to the i-th level The N-type doped region in the main unit is electrically connected, i is an integer greater than or equal to 3 and less than or equal to Q; the first P-type doped region in the first-level main unit is used to connect to the anode potential, and the second-level main unit The N-type doped region is used to connect to the cathode potential. 10. The forming method of SCR electrostatic protection structure according to claim 9, characterized in that, the concentration of P-type ions in the second P-type doped region is less than the concentration of P-type ions in the first P-type doped region . 11. The method for forming the SCR electrostatic protection structure according to claim 9, further comprising: forming a Silicide barrier layer. 12. The method for forming the SCR electrostatic protection structure according to claim 9, further comprising: before forming the first-level main unit to the Q-th level main unit, forming the j-th unit area to the j+1-th unit In the isolation layer in the semiconductor substrate between the regions, j is an integer greater than or equal to 1 and less than or equal to Q-1. 13. The method for forming the SCR electrostatic protection structure according to claim 12, wherein the bottom surface of the isolation layer is lower than the bottom surface of the second P-type doped region and higher than the bottom of the N-type well surface. 14. The method for forming the SCR electrostatic protection structure according to claim 9, further comprising: forming a first connection line on the semiconductor substrate, the first connection line electrically connects the first-level main unit The N-type doped region and the first P-type doped region in the Qth level main unit. 15. The method for forming the SCR electrostatic protection structure according to claim 9, further comprising: forming the i-2th level connection line on the semiconductor substrate, the i-2th level connection line is electrically connected to the The first P-type doped region in the i-1 level main unit and the N-type doped region in the i-th level main unit. 16 . The method for forming the SCR electrostatic protection structure according to claim 9 , wherein the semiconductor substrate has substrate trap ions, and the conductivity type of the substrate trap ions is P type.

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