CN111816562A - Semiconductor structure and method of forming the same - Google Patents

Abstract

A semiconductor structure and a method for forming the same, the forming method includes: providing a substrate on which a dummy gate structure and a hard mask layer located on top thereof are formed; the wall and the etching stop layer of the substrate exposed by the dummy gate structure; a dielectric material layer is formed on the exposed substrate of the dummy gate structure; the first planarization process is performed on the dielectric material layer with the highest part of the top of the etching stop layer as the stop position; After the first planarization process is performed, the etching stop layer and the dielectric material layer are etched to remove the etching stop layer and the dielectric material layer higher than the top of the hard mask layer; after the etching process, the dummy gate structure is used. The top is the stop position, and the second planarization process is performed on the dielectric material layer and the hard mask layer, and the remaining dielectric material layer is used as an interlayer dielectric layer. The embodiments of the present invention are beneficial to improve the flatness of the top surface of the interlayer dielectric layer and reduce the probability of damage to the gate structure.

Description

Semiconductor structure and method of forming the same

technical field

Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a method for forming the same.

Background technique

With the development of highly integrated semiconductor devices, the gate length of metal-oxide-semiconductor (MOS) devices is being scaled down to a smaller size. device performance requirements.

Depending on the type and function of the semiconductor device, the number of wiring layers of the fabricated semiconductor device may be different. A semiconductor device usually includes a device layer located on and in the semiconductor substrate, an interlayer dielectric layer (Inter Layer Dielectric, ILD) located on the device layer, and an interlayer dielectric layer located in the interlayer dielectric layer for connecting the device layer. The wiring structure of active and passive devices. The interlayer dielectric layer is usually composed of insulating materials, which can avoid short circuits between active devices or passive devices and the wires that constitute the wiring structure.

SUMMARY OF THE INVENTION

The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, so as to improve the performance of the semiconductor structure.

In order to solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate on which a dummy gate structure is formed, and a hard mask layer is formed on top of the dummy gate structure; forming a conformal cover the top and sidewalls of the hard mask layer, the sidewalls of the dummy gate structure, and the etch stop layer of the substrate exposed by the dummy gate structure; a dielectric material layer is formed on the exposed substrate of the dummy gate structure, the The dielectric material layer covers the etch stop layer on the hard mask layer; taking the highest part of the top of the etch stop layer as the stop position, the dielectric material layer is subjected to a first planarization treatment; After a planarization process, the etching stop layer and the dielectric material layer are etched to remove the etching stop layer and the dielectric material layer above the top of the hard mask layer; after the etching process, Taking the top of the dummy gate structure as a stop position, a second planarization process is performed on the dielectric material layer and the hard mask layer, and the remaining dielectric material layer is used as an interlayer dielectric layer.

Correspondingly, an embodiment of the present invention further provides a semiconductor structure, including: a semiconductor structure formed by the foregoing formation method.

Compared with the prior art, the technical solutions of the embodiments of the present invention have the following advantages:

In the embodiment of the present invention, the highest part of the top of the etching stop layer is used as the stop position, and the first planarization process is performed on the dielectric material layer. Therefore, in the step of the first planarization process, only the dielectric material layer is The first planarization treatment is performed without contact with other film layers, which is beneficial to prevent the problem of difference in grinding amount due to different pattern densities in each area or different top surface heights of each film layer structure, and reduces the top of the dielectric material layer. The probability of occurrence of the problem of dishing makes the height consistency of the top of the dielectric material layer after the first planarization process better, and at the same time, the thickness of the dielectric material layer to be removed in the subsequent etching process can be reduced, so that the etching process can reduce the thickness of the dielectric material layer. The required process time is short, and by using the anisotropic etching process, it is easy to remove different materials in the same step at a similar etching rate, which is beneficial to reduce the effect of the etching process on the medium in the regions with different pattern densities. The difference in the etching amount of the material layer, therefore, after the etching process is completed, the height consistency of the top of the remaining dielectric material layer is also better, and it is also beneficial to reduce the dummy gate caused by the difference in the etching amount of the dielectric material layer. The probability of loss of the etch stop layer on the sidewall of the structure ensures the protection of the etch stop layer on the sidewall of the gate structure formed in the subsequent process and prevents the sidewall of the gate structure from occurring. loss; to sum up, the embodiment of the present invention combines the first planarization treatment and the etching treatment to improve the flatness of the top surface of the interlayer dielectric layer while reducing the probability of damage to the gate structure, thereby improving the semiconductor structure. performance.

Description of drawings

1 to 7 are schematic structural diagrams corresponding to each step in a method for forming a semiconductor structure;

Fig. 8 is a scanning electron microscope view of a semiconductor structure;

9 to 19 are schematic structural diagrams corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention.

Detailed ways

In the semiconductor field, the step of forming an interlayer dielectric layer generally includes: forming a dielectric material layer on the exposed substrate of the dummy gate structure, the dielectric material layer covering the top of the dummy gate structure; flattening the top of the dielectric material layer After processing, the remaining dielectric material layer is used as an interlayer dielectric layer, and the interlayer dielectric layer exposes the top of the dummy gate structure.

In the semiconductor field, according to the design requirements of integrated circuits, the pattern density of different regions on the substrate is usually different. For example, the substrate usually includes a pattern dense area and a pattern sparse area. Compared with the pattern dense area, the pattern sparse area is The number of the adjacent dummy gate structures is relatively small, the distance between the adjacent dummy gate structures is relatively far, and the size of the opening enclosed by the adjacent dummy gate structures and the substrate is relatively large.

Due to the loading effect, the larger the size of the opening, the faster the rate of planarization, and the greater the removal at the same time. Therefore, in the step of flattening the top of the dielectric material layer in the formation method, the flattening rate of the dielectric material layer in the pattern sparse area is relatively fast, which easily leads to the height of the top surface of the interlayer dielectric layer. The consistency is poor, and the probability of a concave problem on the top surface of the interlayer dielectric layer is high.

In order to solve the above problems, a method for forming a semiconductor structure has been proposed. Referring to FIG. 1 to FIG. 7 , schematic structural diagrams corresponding to each step in a method for forming a semiconductor structure are shown.

Referring to FIG. 1 , a substrate 1 is provided, on which a dummy gate structure 2 is formed, a hard mask layer 3 is formed on top of the dummy gate structure 2 , and a conformal cover for the hard mask is also formed on the substrate 1 The top and sidewalls of the film layer 3 , the sidewalls of the dummy gate structure 2 , and the first etch stop layer 4 of the substrate 1 exposed by the dummy gate structure 2 .

Referring to FIG. 2 , a bottom dielectric material layer 5 is formed on the substrate 1 exposed by the dummy gate structure 2 , and the bottom dielectric material layer 5 covers the first etch stop layer 4 on the hard mask layer 3 .

Referring to FIG. 3 , a partial thickness of the bottom dielectric material layer 5 is etched, and the remaining bottom dielectric material layer 5 exposes a part of the sidewall of the dummy gate structure 2 .

Referring to FIG. 4 , a dummy gate structure 2 exposed to the remaining bottom dielectric material layer 5 and a second etch stop layer 6 remaining on the bottom dielectric material layer 5 are formed conformally.

Referring to FIG. 5 and FIG. 6, a top dielectric material layer 7 is formed on the second etch stop layer 6; the top of the second etch stop layer 6 on the dummy gate structure 2 is used as a stop position, and the The top dielectric material layer 7 is described.

Referring to FIG. 7 , after the top dielectric material layer 7 is planarized, the top of the hard mask layer 3 is used as the stop position, the top dielectric material layer 7 higher than the hard mask layer 3 is removed by grinding, and a second etching process is performed. The stop layer 6 and the first etch stop layer 4, the remaining top dielectric material layer 7, the second etch stop layer 6 and the bottom dielectric material layer 5 between the adjacent dummy gate structures 2 are used as interlayer dielectrics layer (not labeled).

In the forming method, by forming a second etch stop layer 6 on the remaining bottom dielectric material layer 5, the second etch stop layer 6 can be defined in the subsequent step of planarizing the top dielectric material layer 7. The location of the flattening process is beneficial to reduce the problem of the difference in the flattening process rate due to the different pattern densities in each region, thereby improving the flatness and height uniformity of the top of the interlayer dielectric layer.

However, in the step of etching the bottom dielectric material layer 5 with a partial thickness, the formation method tends to cause loss to the first etch stop layer 4 located on the sidewall of the dummy gate structure 2, so that it is difficult to ensure the first etch stop layer 4. The etching stop layer 4 has a protective effect on the gate structure formed later in the subsequent process, the gate structure has a high probability of being damaged, and the performance of the formed semiconductor structure is poor.

Referring to FIG. 8 , an electron microscope scanning image of a semiconductor structure is shown. As can be seen from the figure, the first etch stop layer 4 suffers a large loss, and it is difficult to protect the sidewall of the gate structure, forming poor formation of semiconductor structures.

In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate on which a dummy gate structure is formed, and a hard mask layer is formed on top of the dummy gate structure; forming an etch stop layer that covers the top and sidewalls of the hard mask layer, the sidewalls of the dummy gate structure, and the substrate exposed by the dummy gate structure; forming a dielectric material layer on the exposed substrate of the dummy gate structure, The dielectric material layer covers the etch stop layer on the hard mask layer; taking the highest part of the top of the etch stop layer as the stop position, the dielectric material layer is subjected to a first planarization treatment; After the first planarization process, the etching stop layer and the dielectric material layer are etched to remove the etch stop layer and the dielectric material layer above the top of the hard mask layer; and the etching process is performed. Then, taking the top of the dummy gate structure as a stop position, a second planarization process is performed on the dielectric material layer and the hard mask layer, and the remaining dielectric material layer is used as an interlayer dielectric layer.

In the embodiment of the present invention, the highest part of the top of the etching stop layer is used as the stop position, and the first planarization process is performed on the dielectric material layer. Therefore, in the step of the first planarization process, only the dielectric material layer is The first planarization treatment is performed without contact with other film layers, which is beneficial to prevent the problem of difference in grinding amount due to different pattern densities in each area or different top surface heights of each film layer structure, and reduces the top of the dielectric material layer. The probability of occurrence of the concave problem makes the height consistency of the top of the dielectric material layer after the first planarization process better, and at the same time, the thickness of the dielectric material layer to be removed in the subsequent etching process can be reduced, so that the required amount of the etching process can be reduced. The process time is short, and by using the anisotropic etching process, it is easy to remove different materials in the same step at a similar etching rate, which is beneficial to reduce the etching of the dielectric material layer in different pattern density regions by the etching process. Therefore, after the etching process is completed, the height consistency of the top of the remaining dielectric material layer is also better, and it is also beneficial to reduce the sidewall of the dummy gate structure caused by the difference in the etching amount of the dielectric material layer. The probability of loss of the etch stop layer is reduced, so as to ensure the protective effect of the etch stop layer on the sidewall of the gate structure formed in the subsequent process, and prevent the sidewall of the gate structure from being lost; In the embodiment of the present invention, combining the first planarization process and the etching process, the top surface flatness of the interlayer dielectric layer can be improved, and at the same time, the probability of damage to the gate structure can be reduced, thereby improving the performance of the semiconductor structure.

In order to make the above objects, features and advantages of the embodiments of the present invention more clearly understood, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

9 to 19 are schematic structural diagrams corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention.

Referring to FIG. 9 , a substrate 100 is provided on which a dummy gate structure 101 is formed, and a hard mask layer 102 is formed on top of the dummy gate structure 101 .

The substrate 100 is used to provide a process platform for the subsequent formation of semiconductor structures.

In this embodiment, the substrate 100 is used to form a planar transistor, and the substrate 100 only includes a substrate (not shown). In other embodiments, when the substrate is used to form a fin field effect transistor, the substrate correspondingly includes a substrate and a fin protruding from the substrate.

In this embodiment, the substrate is a silicon substrate. In other embodiments, the material of the substrate can also be other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, and the substrate can also be a silicon-on-insulator substrate or an insulator other types of substrates such as germanium substrates. The material of the substrate may be a material suitable for process requirements or easy integration.

The dummy gate structure 101 is used to occupy a space for the subsequent formation of the gate structure.

In this embodiment, the dummy gate structure 101 is a polysilicon gate structure, and the dummy gate structure 101 accordingly includes a dummy gate oxide layer 1011 on the substrate 100 and a dummy gate on the dummy gate oxide layer 1011 Layer 1012.

The material of the dummy gate layer 1012 can be polysilicon, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride or amorphous carbon. The material of the dummy gate oxide layer 1011 may be silicon oxide or silicon oxynitride. In this embodiment, the material of the dummy gate layer 1012 is polysilicon. The material of the dummy gate oxide layer 1011 is silicon oxide.

In other embodiments, the dummy gate structure may also include only a dummy gate layer.

In this embodiment, sidewalls 103 are further formed on the sidewalls of the dummy gate structure 101 . The sidewall spacers 103 are used to protect the sidewalls of the dummy gate structure 101 , and the sidewall spacers 103 are also used to define the formation regions of the source and drain doped layers.

The material of the spacers 103 may be one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbonitride, silicon oxycarbide, boron nitride and boron carbonitride.

The sidewall 103 may be a single-layer structure or a laminated structure. In this embodiment, the side wall 103 is a laminated structure.

Specifically, the sidewall spacer 103 is an ONO (Oxide Nitride Oxide, oxide-silicon nitride-oxide) structure, and the sidewall spacer 103 includes a first sidewall spacer located on the sidewall of the dummy gate structure 101 ( FIG. Not shown), a second sidewall (not shown) located on the sidewall of the first sidewall, and a third sidewall (not shown) located on the sidewall of the second sidewall. Correspondingly, the material of the first spacer is silicon oxide, the material of the second spacer is silicon nitride, and the material of the third spacer is silicon oxide.

It should be noted that, in the integrated circuit design, according to design requirements, different film layer structures will be formed on the sidewalls and the top surface of the dummy gate structure 101 of different devices. For example: in this embodiment, the substrate 100 includes an NMOS device region (not marked) and a PMOS device region (not marked), and the top surface of the dummy gate structure 101 on the substrate is located at the junction of the NMOS device region and the PMOS device region. A low dielectric constant layer 1051 and an N/P interface layer 1052 located on the top surface and the sidewalls of the low dielectric constant layer 1051 are also formed on the sidewalls. Wherein, the low dielectric constant layer 1051 is used to reduce the leakage current of the device, and the N/P boundary layer 1052 is used to define the boundary between the NMOS device region and the PMOS device region.

The hard mask layer 102 is used as an etching mask for forming the dummy gate structure 101 , and the hard mask layer 102 is also used to protect the top of the dummy gate structure 101 in subsequent processes. .

The subsequent process further includes: forming an etch stop layer conformally covering the top and sidewalls of the hard mask layer 102 , the sidewalls of the dummy gate structure 101 , and the substrate 100 exposed by the dummy gate structure 101 ; A dielectric material layer is formed on the substrate 100 exposed by the gate structure 101, and the dielectric material layer covers the etch stop layer located on the hard mask layer 102; The dielectric material layer is subjected to a first planarization treatment; after the first planarization treatment is performed, an anisotropic etching process is used to perform an etching treatment on the etching stop layer and the dielectric material layer, and the removal is higher than the Etch stop layer and dielectric material layer on top of hard mask layer 102 .

The hard mask layer 102 is used to define an etching stop position in the subsequent steps of etching the etching stop layer and the dielectric material layer.

In this embodiment, the hard mask layer 102 includes a bottom hard mask layer 1021 and a top hard mask layer 1022 located on the bottom hard mask layer 1021, and the bottom hard mask layer 1021 is made of nitrogen The material of the top hard mask layer 1022 is silicon oxide.

In the subsequent steps of etching the etch stop layer and the dielectric material layer 107, the top surface of the top hard mask layer 1022 is used to define the etch stop position. Wherein, the material of the top hard mask layer 1022 is silicon oxide, and the adhesion between silicon oxide and other material layers is good, which facilitates the formation of subsequent layers.

The subsequent step further includes the step of performing a third planarization process, and the bottom hard mask layer 1021 is used to define a stop position of the third planarization process, so as to improve the flatness of the top surface of the material layer to be ground after the third planarization process Spend. Wherein, the material of the bottom hard mask layer 1021 is silicon nitride, and the density and hardness of silicon nitride are relatively high, and the function of defining the stop position of the third planarization process is significant.

In this embodiment, source and drain doped layers 104 are further formed in the substrate 100 on both sides of the dummy gate structure 101 . Specifically, the source and drain doped layers 104 are located in the substrate 100 on both sides of the dummy gate structure 101 .

When forming an NMOS transistor, the source-drain doped layer 104 includes a stressor layer doped with N-type ions, the stressor layer is made of Si or SiC, and the stressor layer provides tensile stress to the channel region of the NMOS transistor function, thereby helping to improve the carrier mobility of the NMOS transistor, wherein the N-type ions are P ions, As ions or Sb ions; when the PMOS transistor is formed, the source-drain doped layer 104 includes doped The stress layer of P-type ions, the material of the stress layer is Si or SiGe, and the stress layer provides compressive stress to the channel region of the PMOS transistor, thereby helping to improve the carrier mobility of the PMOS transistor. The P-type ions are B ions, Ga ions or In ions.

Referring to FIG. 10 , an etch stop layer 106 is formed conformally covering the top and sidewalls of the hard mask layer 102 , the sidewalls of the dummy gate structure 101 , and the substrate 100 exposed by the dummy gate structure 101 . Specifically, the etch stop layer 106 conformally covers the top and sidewalls of the hard mask layer 102 , the sidewalls of the dummy gate structure 101 , and the source-drain doping layer 104 .

The etch stop layer 106 is a contact hole etch stop layer (Contact Etch Stop Layer, CESL). Wherein, the etching stop layer 106 on the top surface of the source and drain doping layer 104 is used to define the etching stop position in the subsequent contact hole etching process, which is beneficial to reduce the source and drain doping in the contact hole etching process. Damage to the impurity layer 104 ; the etch stop layer 106 on the sidewall of the dummy gate structure 101 is used to protect the dummy gate structure 101 in subsequent processes, and the dummy gate structure 101 is subsequently After the gate structure is formed, the etch stop layer 106 is also used to protect the gate structure in subsequent processes.

In this embodiment, the material of the etching stop layer 106 is silicon nitride. The silicon nitride material has high density and high hardness, so as to ensure that the etching stop layer 106 can play a role of defining an etching stop position and a corresponding protective role.

In this embodiment, the etch stop layer 106 is formed by an atomic layer deposition (Atomic Layer Deposition, ALD) process. The atomic layer deposition process has better step coverage capability, which is beneficial to conformally cover the top and sidewalls of the hard mask layer 102 , the sidewalls of the dummy gate structure 101 , and the dummy gate structure with the etch stop layer 106 . The substrate 100 exposed by 101 ; and, the atomic layer deposition process includes performing multiple atomic layer deposition cycles to form a thin film with a desired thickness, which is beneficial to improve the thickness uniformity and density of the etch stop layer 106 .

It should be noted that, in this embodiment, a low dielectric constant layer 1051 is formed on the top surface and sidewall of the dummy gate structure 101 at the junction of the first device region and the second device region, and a low dielectric constant layer 1051 is formed on the low dielectric constant layer 1051 . The N/P boundary layer 1052 on the top surface and sidewalls of the constant layer 1051, therefore, in the step of forming the etch stop layer 106, the etch stop layer 106 also conformally covers the N/P boundary layer 1052 . After the etch stop layer 106 is formed, the top surface of the etch stop layer 106 has different heights.

Referring to FIG. 11 , a dielectric material layer 107 is formed on the substrate 100 exposed by the dummy gate structure 101 , and the dielectric material layer 107 covers the etch stop layer 106 on the hard mask layer 102 .

The dielectric material layer 107 is used to form an interlayer dielectric layer subsequently, so as to achieve isolation between adjacent devices.

Therefore, the material of the dielectric material layer 107 is an insulating material, such as one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon oxycarbonitride. In this embodiment, the dielectric material layer 107 has a single-layer structure, and the material of the dielectric material layer 107 is silicon oxide.

In this embodiment, the dielectric material layer 107 is formed by a flowable chemical vapor deposition (FCVD) process. The fluid chemical vapor deposition process has good filling ability and is suitable for filling openings with high aspect ratios, which is beneficial to reduce the probability of forming voids and other defects in the dielectric material layer 107, and is correspondingly beneficial to improve the film quality of the subsequent interlayer dielectric layers. .

Referring to FIG. 12 , a first planarization process is performed on the dielectric material layer 107 with the highest position on the top of the etch stop layer 106 as a stop position.

It should be noted that the top surface of the etch stop layer 106 has different heights, and the highest part of the top of the etch stop layer 106 refers to, The farthest distance from the top surface of the stop layer 106 to the surface of the substrate 100 .

By taking the highest part of the top of the etching stop layer 106 as the stop position, the first planarization process is performed on the dielectric material layer 107. Therefore, in the step of the first planarization process, only the dielectric material layer 107 is subjected to the first planarization process. The first planarization process is performed without contact with other film structures, which is beneficial to prevent the problem of difference in grinding amount due to different pattern densities in each area or different top surface heights of each film structure, and reduces the remaining top of the dielectric material layer 107. The probability of occurrence of the concave problem makes the height consistency of the top of the dielectric material layer 107 after the first planarization process better, which is correspondingly beneficial to improve the height consistency of the top of the subsequent interlayer dielectric layers.

Moreover, the subsequent steps further include performing an etching process on the etching stop layer 106 and the dielectric material layer 107, and removing the etching stop layer 106 and the dielectric material layer 107 above the top of the hard mask layer 102. Compared with the scheme of performing the first planarization treatment and directly etching the dielectric material layer, the first planarization treatment reduces the thickness of the dielectric material layer 107 to be removed by the subsequent etching treatment, so that the The process time required for the etching treatment is short, which is beneficial to reduce the difference in the etching amount of the dielectric material layer 107 in the regions with different pattern densities, which is not only beneficial to improve the subsequent interlayer dielectric layer top. The high consistency is also beneficial to reduce the probability of loss of the etch stop layer 106 on the sidewall of the dummy gate structure 101 due to the difference in the etching amount of the dielectric material layer 107 , thereby ensuring that the etch stop layer 106 is used in the subsequent The protective effect on the sidewalls of the gate structure 101 during the manufacturing process prevents the sidewalls of the gate structure 101 from being worn out and improves the performance of the semiconductor structure.

In this embodiment, a low dielectric constant layer 1051 is formed on the top surface and sidewall of the dummy gate structure 101 at the junction of the first device region and the second device region, and a low dielectric constant layer 1051 is formed on the low dielectric constant layer 1051 N/P boundary layer 1052 on the top surface and sidewalls, therefore, the highest point on top of the etch stop layer 106 refers to the top of the etch stop layer 106 on top of the N/P boundary layer 1052 .

In this embodiment, the first planarization treatment is performed using a chemical mechanical polishing (Chemically-Mechanically Polishing, CMP) process. By adopting the chemical mechanical polishing process, it is beneficial to precisely locate the highest part of the top of the etching stop layer 106, so as to precisely control the stop position of the first planarization process, reduce the technological difficulty of the first planarization process, and also It is beneficial to further improve the flatness of the top surface of the dielectric material layer 107 after the first planarization process.

Specifically, during the first planarization process using the chemical mechanical polishing process, an endpoint detection (EPD) method is used, and the highest point on the top of the etching stop layer 106 is used as the polishing stop position.

In other embodiments, the first planarization process may further include performing an etchback and a chemical mechanical polishing process in sequence.

Referring to FIG. 13 , after the first planarization process is performed, the etch stop layer 106 and the dielectric material layer 107 are etched to remove the etch stop layer 106 and the top of the hard mask layer 102 . Dielectric material layer 107 .

By using the etching process, it is easy to remove different materials in the same step at a similar etching rate, which is beneficial to reduce the difference in the etching amount of the dielectric material layer 107 in different pattern density regions by the etching process. Therefore, After the etching process is completed, the height consistency of the top of the remaining dielectric material layer 107 is also good, and it is also beneficial to reduce the etching stop on the sidewalls of the dummy gate structure 101 caused by the difference in the etching amount of the dielectric material layer 107 The probability of the loss of the layer 106 is guaranteed, thereby ensuring the protection of the etch stop layer 106 on the sidewall of the gate structure formed in the subsequent process and preventing the sidewall of the gate structure from being lost.

In this embodiment, the etch stop layer 106 and the dielectric material layer 107 above the top of the top hard mask layer 1022 are removed. The top hard mask layer 1022 is used to define an etch stop position in the step of etching the etch stop layer 106 and the dielectric material layer 107, so as to improve the performance of the dielectric material layer after the etching process. High consistency at the top of the 107.

Moreover, the material of the top hard mask layer 1022 is silicon oxide, and the adhesion between the silicon oxide layer and other film layers is high, which is convenient for subsequent formation on the top hard mask layer 1022 and the dielectric material layer 107 Other film layers are correspondingly beneficial to improve the quality of the subsequently formed film layers.

In this embodiment, the etching process is performed by using the Siconi process. As a low-strength and high-precision chemical etching method, the Siconi process generally includes the following steps: first, generating an etching gas; etching the material layer to be etched through the etching gas to form by-products; performing an annealing process to etch the The by-products are sublimated and decomposed into gaseous products; the gaseous products are removed by means of suction.

In this embodiment, the etching gas of the _Siconi process includes _{CxFy gas and CxHyFz gas .}

Using the Siconi process is easy to make the etching rate of the silicon nitride material and the silicon oxide material relatively close, so that the etch stop layer 106 and the top of the hard mask layer 102 can be removed in the same step. The dielectric material layer 107, and the use of the Siconi process is also conducive to improving the etching load effect of the etching process, thereby further improving the height consistency of the top surface of the dielectric material layer 107 after the etching process; in addition, The Siconi process is easy to obtain a higher etching selectivity ratio, which is beneficial to reduce the probability of damage to other film structures in the etching process.

In other embodiments, according to actual process requirements, a dry etching process may also be used to perform the etching process.

The bias voltage of the Siconi process should not be too small nor too large. If the bias voltage is too small, it is easy to reduce the plasma concentration of the etching process, thereby reducing the etching rate; if the bias voltage is too large, it is easy to reduce the uniformity of the etching rate, thereby reducing the etching process. Then, the height of the top surface of the dielectric material layer 107 is uniform. Therefore, in this embodiment, the bias voltage of the Siconi process is 15V to 25V.

In this embodiment, in the step of performing the etching process, the process parameters of the etching process are reasonably set, so that after the etching process is performed, the height difference of the top surface of the dielectric material layer 107 in each region is less than 10 nm, Thus, the height uniformity of the top surface of the dielectric material layer 107 is improved.

In this embodiment, in the step of removing the etch stop layer 106 and the dielectric material layer 107 above the top of the hard mask layer 102 , the N/P boundary layer above the top of the hard mask layer 102 is also removed 1052 and a low dielectric constant layer 1051.

In this embodiment, after the etching process is performed, the method further includes:

Referring to FIG. 14 , a cross-sectional view of the semiconductor structure along the extension direction of the dummy gate structure 101 is shown. In this embodiment, after the etching process is performed, the method further includes: cutting the dummy gate structure 101 through an etching process. , an opening 200 exposing the substrate 100 is formed in the dielectric material layer 107 , and the opening 200 is distributed in the extending direction of the dummy gate structure 101 .

By cutting off the dummy gate structure 101 , the unnecessary dummy gate structure 101 is removed, so that the layout of the dummy gate structure 101 can meet the design requirements of the integrated circuit.

In this embodiment, the step of forming the opening 200 includes: forming a mask pattern layer 108 on the hard mask layer 102; using the mask pattern layer 108 as a mask, using a dry etching process to The dummy gate structure 101 is cut off, and an opening 200 exposing the substrate 100 is formed in the dielectric material layer 107 .

In this embodiment, the material of the mask pattern layer 108 is silicon oxide, the mask pattern layer 108 is formed on the top hard mask layer 1022, the mask pattern layer 108 and the top hard mask layer The film layer 1022 has good adhesion, which is beneficial to improve the process effect of pattern transfer.

The dry etching process has the characteristics of anisotropic etching, which is beneficial to improve the precision of pattern transfer, and is beneficial to make the cross section of the opening 200 meet the process requirements.

Referring to FIGS. 15 to 17 , an isolation material layer 111 (as shown in FIG. 17 ) is formed to fill the opening 200 , and the isolation material layer 111 also covers the dielectric material layer 107 and the hard mask layer 102 .

By filling the isolation material layer 111 in the opening 200 , the remaining dummy gate structures 101 are isolated from each other in the extending direction of the dummy gate structure 101 , and a gate is subsequently formed at the position of the dummy gate structure 101 After the structure, the isolation material layer 111 in the opening 200 can also electrically isolate the gate structures on both sides of the opening 200 .

Therefore, the material of the isolation material layer 111 is an insulating material, such as one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon oxycarbonitride. In this embodiment, the isolation material layer 111 has a single-layer structure, and the material of the isolation material layer 111 is silicon oxide.

In this embodiment, the isolation material layer 111 is formed by a fluid chemical vapor deposition process, which is beneficial to reduce the probability of forming defects such as voids in the isolation material layer 111 .

Specifically, the isolation material layer 111 covers the mask pattern layer 108 .

It should be noted that, with reference to FIGS. 15 to 16 , in this embodiment, after forming the opening 200 and before forming the isolation material layer 111 , the method further includes: forming a protective layer 110 on the sidewall of the opening 200 .

After the subsequent removal of the dielectric material layer 107 higher than the top of the dummy gate structure 101 to form an interlayer dielectric layer, the method further includes: removing the dummy gate structure 101, forming a gate opening in the dielectric material layer 107; A gate structure is formed in the electrode opening. The protective layer 110 is used to protect the isolation material layer 111 located in the opening 200 during the step of forming the gate opening, thereby reducing damage to the isolation material layer 111 located in the opening 200 The probability.

In this embodiment, the material of the protective layer 110 is silicon nitride. The density and hardness of silicon nitride are relatively high, which is beneficial to ensure the protective effect of the protective layer 110 on the isolation material layer 111 .

Specifically, the step of forming the protective layer 110 includes: forming a protective material layer 109 that conformally covers the bottom and sidewalls of the opening 200 and the top of the hard mask layer 102 and the dielectric material layer 107 (as shown in FIG. 15 ). shown); anisotropic etching process is used to remove the protective material layer 109 on the top of the hard mask layer 102 and the dielectric material layer 107 and the bottom of the opening 200, and the remaining protection on the sidewall of the opening 200 is retained. The material layer 109 serves as the protective layer 110 .

By making the protective material layer 109 conformally cover the bottom and sidewalls of the opening 200 and the top of the hard mask layer 102 and the dielectric material layer 107, a maskless etching process can be used to remove the hard mask layer 102 and the top of the dielectric material layer 107. The top of the mask layer 102 and the dielectric material layer 107 and the protective material layer 109 at the bottom of the opening 200 make the process of forming the protective layer 110 unnecessary to use a photomask, which is beneficial to reduce the process cost.

In this embodiment, the protective material layer 109 is formed by an atomic layer deposition process. Using the atomic layer deposition process is beneficial to improve the conformal covering ability of the protective material layer 109 so that it can be formed on the sidewall of the opening 200 , and the atomic layer deposition process is also beneficial to improve the protective material layer 109 The uniformity and density of the thickness of the film are further favorable to ensure the protective effect of the protective material layer 109 on the isolation material layer 111 located in the opening 200 .

The anisotropic etching process described in this embodiment is a dry etching process. The dry etching process is easy to achieve anisotropic etching, which is beneficial to reduce damage to the protective material layer 109 located on the sidewall of the opening 200 , so that the protective layer 110 can play a corresponding protective effect.

Referring to FIG. 18 , with the top of the hard mask layer 102 as a stop position, a third planarization process is performed on the isolation material layer 111 and the dielectric material layer 107 .

In this embodiment, the materials of the isolation material layer 111 and the bottom hard mask layer 1021 are different. Therefore, in the third planarization step, the bottom hard mask layer 1021 is used as the stop position , which is beneficial to improve the uniformity of the top height of the isolation material layer 111 after the third planarization process.

In this embodiment, the chemical mechanical polishing process is used to perform the third planarization treatment.

Specifically, the end point detection (EPD) method is adopted, and the highest position on the top of the bottom hard mask layer 1021 is used as the grinding stop position.

Referring to FIG. 19 , after the etching process is performed, the top of the dummy gate structure 101 is used as a stop position to perform a second planarization process on the dielectric material layer 107 and the hard mask layer 102 , and the dielectric material layer remains. 107 serves as the interlayer dielectric layer 120 .

It can be seen from the foregoing that the top height of the dielectric material layer 107 after the first planarization treatment and the etching treatment is relatively consistent. Therefore, in the step of performing the second planarization treatment, the uniformity of the polishing rate is better, forming the above After the interlayer dielectric layer 120 is formed, the uniformity of the top height of the interlayer dielectric layer 120 is improved.

Moreover, the uniformity of the polishing rate of the second planarization process is good, which is also beneficial to reduce the damage to the etch stop layer 106 on the sidewall of the dummy gate structure 101 during the second planarization process. Therefore, after the gate structure is subsequently formed at the position of the dummy gate structure 101, the etch stop layer 106 can have a corresponding protective effect on the gate structure in the subsequent process, so that the gate The probability of losses experienced by the sidewalls of the structure is reduced, improving the performance of the semiconductor structure.

In this embodiment, a chemical mechanical polishing process is used to perform the second planarization treatment. Using the chemical mechanical polishing process is beneficial to accurately locate the stop position of the second planarization process, reduce the technological difficulty of the second planarization process, and further improve the flatness of the top surface of the interlayer dielectric layer 120 .

Specifically, during the second planarization process using the chemical mechanical polishing process, the end point detection method is adopted, and the top of the dummy gate structure 101 is used as the polishing stop position.

In this embodiment, an isolation material layer 111 (as shown in FIG. 18 ) is further formed on the substrate 100 and located in the opening 200 (as shown in FIG. 18 ), and the top of the isolation material layer 111 is higher than the top of the isolation material layer 111 . Therefore, in the step of performing the second planarization process, the isolation material layer 111 is also subjected to a second planarization process, and the remaining isolation material layer 111 after the second planarization process is used for isolation structure (not shown).

After the gate structure is subsequently formed at the position of the dummy gate structure 101 , the isolation structure is used to achieve electrical isolation between adjacent gate structures along the extension direction of the gate structure.

Correspondingly, the present invention also provides a semiconductor structure formed by the aforementioned method.

It can be seen from the foregoing that the top height consistency of the interlayer dielectric layer formed by the foregoing method is better, and the etch stop layer located on the dummy gate structure suffers less loss, which is beneficial to ensure the etch stop layer. The protection effect on the sidewall of the subsequent gate structure, thereby reducing the probability of loss of the sidewall of the gate structure in the subsequent process. In conclusion, the performance of the semiconductor structure formed by the aforementioned method is improved.

The semiconductor structure can be formed using the formation methods described in the foregoing embodiments. For the specific description of the semiconductor structure in this embodiment, reference may be made to the corresponding descriptions in the foregoing embodiments, which will not be repeated in this embodiment.

Although the present invention is disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be based on the scope defined by the claims.

Claims (14)

1. A method of forming a semiconductor structure, comprising:

providing a substrate, wherein a pseudo gate structure is formed on the substrate, and a hard mask layer is formed on the top of the pseudo gate structure;

forming an etching stop layer which conformally covers the top and the side wall of the hard mask layer, the side wall of the pseudo gate structure and the substrate exposed by the pseudo gate structure;

forming a dielectric material layer on the substrate exposed out of the pseudo gate structure, wherein the dielectric material layer covers the etching stop layer positioned on the hard mask layer;

taking the highest position at the top of the etching stop layer as a stop position, and performing first planarization treatment on the dielectric material layer;

after the first planarization treatment, etching the etching stop layer and the dielectric material layer to remove the etching stop layer and the dielectric material layer which are higher than the top of the hard mask layer;

and after the etching treatment, performing second planarization treatment on the dielectric material layer and the hard mask layer by taking the top of the pseudo-gate structure as a stop position, and taking the residual dielectric material layer as an interlayer dielectric layer.

2. The method of claim 1, wherein said first planarization process is performed using a chemical mechanical polishing process.

3. The method of forming a semiconductor structure of claim 1, wherein the etching process is performed using a dry etching process.

4. The method of forming a semiconductor structure of claim 1, wherein said etching is performed using a Siconi process.

5. The method of claim 1, wherein the step of performing the etching process has a difference in height of the top surface of the dielectric material layer of less than 10nm for each region.

6. The method of claim 1, wherein said second planarization process is performed using a chemical mechanical polishing process.

7. The method of forming a semiconductor structure of claim 1, wherein after the etching process and before the second planarizing process, further comprising: cutting off the dummy gate structure by an etching process, and forming openings exposing the substrate in the dielectric material layer, wherein the openings are distributed in the extending direction of the dummy gate structure; forming an isolation material layer filled in the opening, wherein the isolation material layer also covers the medium material layer and the hard mask layer; taking the top of the hard mask layer as a stop position, and carrying out third planarization treatment on the isolation material layer and the medium material layer;

and in the step of performing second planarization treatment, second planarization treatment is also performed on the isolation material layer, and the residual isolation material layer after the second planarization treatment is used as an isolation structure.

8. The method for forming a semiconductor structure according to claim 7, wherein the hard mask layer comprises a bottom hard mask layer and a top hard mask layer located on the bottom hard mask layer, the bottom hard mask layer is made of silicon nitride, and the top hard mask layer is made of silicon oxide;

in the step of etching the etching stop layer and the dielectric material layer, removing the etching stop layer and the dielectric material layer which are higher than the top of the top hard mask layer;

and in the third planarization treatment step, the bottom hard mask layer is taken as a stop position.

9. The method of claim 7, wherein said third planarization process is performed using a chemical mechanical polishing process.

10. The method of forming a semiconductor structure of claim 7, wherein after forming the opening and before forming the layer of isolation material, further comprising: and forming a protective layer on the side wall of the opening.

11. The method of claim 10, wherein in the step of forming the protective layer, the protective layer is formed of silicon nitride.

12. The method of forming a semiconductor structure of claim 10, wherein the process of forming the protective layer comprises an atomic layer deposition process.

13. The method of forming a semiconductor structure of claim 10, wherein forming the protective layer comprises: forming a protective material layer conformally covering the bottom and the side wall of the opening and the top of the hard mask layer and the dielectric material layer;

and removing the protective material layers positioned at the tops of the hard mask layer and the dielectric material layer and at the bottom of the opening by adopting an anisotropic etching process, and reserving the residual protective material layer on the side wall of the opening as the protective layer.

14. A semiconductor structure formed using the method of any of claims 1-13.

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