CN111816565A - Method of manufacturing semiconductor device - Google Patents

Abstract

A method of fabricating a semiconductor device is provided, the method comprising: forming an active fin and a sacrificial gate structure intersecting the active fin in a first region of a substrate; forming a first spacer and a second spacer on the substrate forming a mask in the second region of the substrate to expose the first region of the substrate; removing the second spacer from the first spacer in the first region of the substrate by using the mask; by removing Portions of the active fins form recesses at opposite sides of the sacrificial gate structure; source and drain electrodes are formed in the recesses; and an etch stop layer is formed to cover both sidewalls of the sacrificial gate structure and the source and drain electrodes pole top surface.

Description

Method of manufacturing semiconductor device

This application claims priority to Korean Patent Application No. 10-2019-0042933 filed in the Korean Intellectual Property Office on April 12, 2019, the disclosure of which is incorporated herein by reference in its entirety.

technical field

The inventive concept relates to a semiconductor device and a method of fabricating the same.

Background technique

As semiconductor devices have further developed, they have been rapidly scaled down. In addition, since a semiconductor device is expected to have high operation speed and high operation accuracy, various techniques are being developed to optimize the structure of a transistor included in the semiconductor device. For example, multi-gate transistors have been proposed as a way to increase the density of integrated circuit devices. Typically, a multi-gate transistor has a three-dimensional channel in which an active fin is formed on a substrate and a gate is formed on the active fin.

SUMMARY OF THE INVENTION

According to an exemplary embodiment of the inventive concept, a method of fabricating a semiconductor device includes: forming an active fin and a sacrificial gate structure crossing the active fin in a first region of a substrate; forming on the substrate a first spacer and a second spacer to cover the sacrificial gate structure; forming a mask in the second area of the substrate to expose the first area of the substrate; removing the first spacer from the first area of the substrate by using the mask removing the second spacer; forming recesses at opposite sides of the sacrificial gate structure by removing portions of the active fins; forming source and drain electrodes in the recesses; and forming an etch stop layer to cover both sides of the sacrificial gate structure sidewalls and top surfaces of the source and drain.

According to an exemplary embodiment of the inventive concept, a method of fabricating a semiconductor device includes forming a first active fin and a first sacrificial gate crossing the first active fin in a first region of a substrate structure, and a second active fin and a second sacrificial gate structure crossing the second active fin are formed in the second region of the substrate; first spacers and a first spacer are formed in the first and second regions of the substrate two spacers to cover the sidewalls of the first sacrificial gate structure and the second sacrificial gate structure; a first mask is formed in the second area of the substrate to expose the first area of the substrate; from the first area of the substrate removing the second spacer; forming a first recess at the opposite side of the first sacrificial gate structure by removing portions of the first active fin; removing the first mask from the second region of the substrate; and A first source electrode and a first drain electrode are formed in the first recess.

According to an exemplary embodiment of the inventive concept, a semiconductor device includes: a substrate having first and second regions; and first and second active fins disposed in the first and second regions of the substrate, respectively , and extends in the first direction; the first gate structure is disposed in the first region of the substrate and extends in the second direction to intersect with the first active fins; the second gate structure is disposed in the substrate in the second region and extending in the second direction to intersect the second active fins; a first spacer disposed on the sidewall of the first gate structure and including an edge formed on a lower portion of the first spacer a first undercut in a drain disposed in a region of the first active fin on opposite sides of the first gate structure; and a second source and a second drain disposed in the second gate structure of the second active fin in the area on the opposite side.

Description of drawings

The above and other features of the present inventive concept will become more apparent by describing in detail exemplary embodiments of the present inventive concept with reference to the accompanying drawings, in which:

FIG. 1 is a plan view of a semiconductor device according to an exemplary embodiment of the inventive concept;

FIG. 2 is a cross-sectional view taken along line AA' and line BB' of FIG. 1 according to an exemplary embodiment of the present inventive concept;

3A, 3B, 3C, 3D, and 3E are cross-sectional views illustrating a process of forming a source/drain in a first region in a method of fabricating a semiconductor device according to an exemplary embodiment of the inventive concept;

4A , 4B, 4C, 4D, 4E and 4F are diagrams illustrating a process of forming source/drain in a second region in a method of fabricating a semiconductor device according to exemplary embodiments of the inventive concepts sectional view;

5A, 5B, 5C, and 5D are cross-sectional views illustrating a process of forming a source/drain in a first region in a method of fabricating a semiconductor device according to an exemplary embodiment of the inventive concept;

6A, 6B, 6C, 6D, 6E, and 6F are diagrams illustrating a process of forming source/drain in a second region in a method of fabricating a semiconductor device according to exemplary embodiments of the inventive concept sectional view;

FIGS. 7A , 7B and 7C are cross-sectional views illustrating a process of forming source/drain electrodes in a first region in a method of fabricating a semiconductor device according to an exemplary embodiment of the inventive concept; and

FIGS. 8A , 8B, 8C, 8D, 8E and 8F are diagrams illustrating a process of forming source/drain in a second region in a method of manufacturing a semiconductor device according to exemplary embodiments of the inventive concept. sectional view.

Detailed ways

Hereinafter, exemplary embodiments of the inventive concept will be described with reference to the accompanying drawings.

1 is a plan view of a semiconductor device according to an exemplary embodiment of the inventive concept, and FIG. 2 is a cross-sectional view taken along line AA' and BB' of FIG. 1 according to an exemplary embodiment of the inventive concept .

1 and 2 , the semiconductor device 100 may include a first transistor 100A disposed in a first region I of the substrate 101 and a second transistor 100B disposed in a second region II of the substrate 101 .

The substrate 101 may have a top surface extending in a first direction (eg, X direction) and a second direction (eg, Y direction). The substrate 101 may include a semiconductor material, such as a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor. For example, the substrate 101 may be a semiconductor substrate of silicon, germanium, silicon germanium, etc., a silicon-on-insulator (SOI) substrate, or a germanium-on-insulator (GeOI) substrate. For example, the first transistor 100A disposed in the first region I may be an N-type fin field effect transistor (FinFET), and the second transistor 100B disposed in the second region II may be a P-type fin field effect transistor (FinFET). ).

The first transistor 100A includes a first active fin 105 , a first gate structure 140 crossing the first active fin 105 , and spacers 150 sequentially disposed on opposite sidewalls of the first gate structure 140 . Additionally, the first transistor 100A includes a first source/drain 110 disposed on opposite sides of the first gate structure 140 and adjacent to the first gate structure 140 . The first transistor 100A also includes a first contact 160 disposed on an opposite side of the first gate structure 140 and connected to the first source/drain 110 . For example, the first contact 160 may be adjacent to the first gate structure 140 .

Similarly, the second transistor 100B includes a second active fin 205 , a second gate structure 240 intersecting the second active fin 205 , and spacers 150 on opposite sidewalls of the second gate structure 240 . Additionally, the second transistor 100B includes a second source/drain 210 disposed on opposite sides of the second gate structure 240 and adjacent to the second gate structure 240 . The second transistor 100B also includes a second contact 260 disposed at the opposite side of the second gate structure 240 and connected to the second source/drain 210 . For example, the second contact 260 may be adjacent to the second gate structure 240 .

The first and second contacts 160 and 260 may include first and second contact plugs 165 and 265 and first and second conductive barriers 161 and 261 , respectively, the first and second contact plugs 165 and 261 , respectively. 265 is formed in a direction substantially perpendicular to the top surface of the substrate 101 (eg, the Z direction), and the first conductive barrier 161 and the second conductive barrier 261 are disposed on the surfaces of the first contact plug 165 and the second contact plug 265 . The semiconductor device 100 may further include an etch stop layer 158 disposed between the first and second contacts 160 and 260 and the spacers 150, respectively. For example, the etch stop layer 158 may be disposed between the first contacts 160 and the etch stop layer 158 may be disposed between the second contacts 260 .

In this embodiment, unlike the second transistor 100B, the first transistor 100A may further include a protective insulating layer 154 disposed along the surface of the spacer 150 between the spacer 150 and the etch stop layer 158 . Since the protective insulating layer 154 serves as a spacer element, the thickness of the first transistor 100A may be greater than that of the second transistor 100B by an additional thickness of the protective insulating layer 154 . The protective insulating layer 154 may remain without removing the second one-time (also referred to as temporary or removable) spacers introduced in the source/drain formation process (see FIGS. 4A-4F ).

Spacers 150 may be disposed on opposite sidewalls of the first gate structure 140 and the second gate structure 240 . For example, the spacers 150 may be in contact with sidewalls of the first and second gate structures 140 and 240 and top surfaces of the first and second active fins 105 and 205 . In addition, the protective insulating layer 154 may have a shape like "L".

As shown in the enlarged view of FIG. 2 , the spacer 150 may be provided with a first undercut C1 or a second undercut C2 formed on lower ends of the spacers 150 (eg, at the lower ends of the gate structures 140 and 240 ). curved corners). For example, the first undercut C1 and the second undercut C2 may be concave recessed portions. The first undercut C1 and the second undercut C2 may be formed in the extending direction of the first gate structure 140 and the second gate structure 240, respectively. For example, the first undercut C1 and the second undercut C2 may extend in the first direction (X direction). For example, the first gate structure 140 and the second gate structure 240 may be sacrificial gate structures 140 and 240 .

In the present embodiment, the undercuts C1 and C2 may be formed on the lower ends of the spacers 150 of both the first transistor 100A and the second transistor 100B. It will be appreciated that during removal of the one-time spacers (eg, 152 of FIG. 3B ) used to form the source/drain 110 and 210 , the lower corners of the spacers 150 are over-etched to form undercuts C1 and C2 (see FIG. 3B ) 3B and 3C). In an example, since the first undercut C1 and the second undercut C2 are formed by wet etching, each of the undercuts C1 and C2 may have a slightly irregular profile according to the extending direction thereof.

In the present embodiment, the first undercut C1 formed on the spacer 150 of the first transistor 100A and the second undercut C2 formed on the spacer 150 of the second transistor 100B may have different shapes from each other (eg, size and/or depth). It will be appreciated that such differences may be due to the conditions and number of processes used to remove the disposable spacers. This will be described in detail through various examples of the manufacturing method which will be described later.

Hereinafter, components of a semiconductor device according to exemplary embodiments of the inventive concept will be described in further detail.

The first active fin 105 and the second active fin 205 may be disposed on the substrate 101 to extend in the second direction (eg, the Y direction). The first active fin 105 and the second active fin 205 may have fin structures protruding from the substrate 101 . The first active fin 105 and the second active fin 205 may be formed by etching the substrate 101 . In exemplary embodiments of the inventive concept, the first active fin 105 and the second active fin 205 may include epitaxial layers grown from the substrate 101 . For example, the first active fin 105 may be formed of silicon including P-type impurities, and the second active fin 205 may be formed of silicon including N-type impurities. The directions in which the first active fin 105 and the second active fin 205 extend are shown to be the same, but are not limited thereto. For example, the first active fin 105 and the second active fin 205 may extend in different directions from each other. The respective numbers of the first active fins 105 and the second active fins 205 are shown as three, but the inventive concept is not limited thereto.

In exemplary embodiments of the inventive concept, device isolation layers may be disposed between the first active fins 105 and between the second active fins 205 . The device isolation layer may be formed to have a height such that upper portions of the first and second active fins 105 and 205 are exposed. The device isolation layer may be formed by, for example, a shallow trench isolation (STI) process. Each device isolation layer may be formed of an insulating material. Each device isolation layer may include, for example, silicon oxide, silicon nitride, a low-k dielectric, or a combination thereof. Low-k dielectrics may include borophosphosilicate glass (BPSG), Tonen silazane (TOSZ), undoped silicate glass (USG), spin-on glass (SOG), flowable oxide (FOX), ortho-silicon Tetraethyl acid (TEOS), oxides of high density plasma CVD (HDP-CVD), etc.

The first gate structure 140 and the second gate structure 240 may extend in a first direction (eg, the X direction) on the substrate 101 and may be disposed across the first active fin 105 and the second active fin 205 . Like the present embodiment, the first gate structure 140 and the second gate structure 240 may intersect the first active fin 105 and the second active fin 205, respectively. For example, the first gate structure 140 and the second gate structure 240 may be substantially perpendicular to the first active fin 105 and the second active fin 205, respectively. Channel regions may be formed in the first and second active fins 105 and 205 crossing the first and second gate structures 140 and 240 . The directions in which the first gate structure 140 and the second gate structure 240 extend are shown to be the same as each other, but the inventive concept is not limited thereto. For example, the first gate structure 140 and the second gate structure 240 may extend in different directions from each other.

Each of the first gate structures 140 may include a first gate insulating layer 142 , a first bottom gate electrode 145 and a first top gate electrode 147 . The first gate insulating layer 142 may be disposed between the first active fin 105 and the first bottom gate electrode 145 . The first gate insulating layer 142 may extend between the spacer 150 and the first bottom gate electrode 145 . The first bottom gate electrode 145 and the first top gate electrode 147 may be sequentially disposed on the first gate insulating layer 142 .

Similarly, each of the second gate structures 240 may include a second gate insulating layer 242 , a second bottom gate electrode 245 and a second top gate electrode 247 . The second gate insulating layer 242 may be disposed between the second active fin 205 and the second bottom gate electrode 245 . The second gate insulating layer 242 may extend between the spacer 150 and the second bottom gate electrode 245 . The second bottom gate electrode 245 and the second top gate electrode 247 may be sequentially disposed on the second gate insulating layer 242 .

For example, each of the first gate insulating layer 142 and the second gate insulating layer 242 may include silicon oxide, silicon oxynitride, silicon nitride, or a high-k dielectric. A high-k dielectric may refer to a material having a higher dielectric constant than that of silicon oxide (SiO ₂ ). High-k dielectrics may include, for example, aluminum oxide (Al ₂ O ₃ ), tantalum oxide (Ta ₂ O ₅ ), titanium oxide (TiO ₂ ), yttria (Y ₂ O ₃ ), zirconium oxide (ZrO ₂ ), zirconia silicon oxide ( _ZrSixOy ), hafnium oxide ( _HfO2 ), hafnium silicon oxide ( _HfSixOy ), lanthanum oxide ( _{La2O3 )} , lanthanum aluminum oxide ( _{LaAlxOy )} , lanthanum hafnium oxide _{( LaHfxO ) y} ), hafnium aluminium oxide (HfAl _x O _y ) or praseodymium oxide (Pr ₂ O ₃ ).

For example, each of the first bottom gate electrode 145 and the second bottom gate electrode 245 may include, for example, titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN) , at least one of titanium aluminum (TiAl), tantalum carbide (TaC), titanium carbide (TiC), and the like. Each of the first top gate electrode 147 and the second top gate electrode 247 may include a metal material such as aluminum (Al), tungsten (W), or molybdenum (Mo), or a semiconductor material such as doped polysilicon.

Spacer 150, protective insulating layer 154, and etch stop layer 158 may include, for example, silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. However, the spacer 150 may include a material having an etch selectivity with respect to at least the protective insulating layer 154 . In exemplary embodiments of the inventive concept, the spacer 150 may include a material having a lower dielectric constant than at least that of the protective insulating layer 154 . For example, the spacers 150 may include SiO ₂ and/or silicon oxynitride (SiON). For example, the protective insulating layer 154 serving as a disposable spacer may include silicon nitride (SiN) and/or Al ₂ O ₃ . In exemplary embodiments of the inventive concept, the spacer and the protective insulating layer may respectively include silicon oxynitride having different nitrogen contents from each other. For example, the silicon oxynitride of the protective insulating layer 154 may be configured to have a higher nitrogen content than that of the spacer.

The etch stop layer 158 is a component arranged to form holes for the first contacts 160 and the second contacts 260 . For example, the etch stop layer 158 may include silicon nitride, silicon oxynitride, or a combination thereof. The etch stop layer 158 may be provided to have the same thickness in the first region I and the second region II. Although not limited thereto, in exemplary embodiments of the present inventive concept, the etch stop layer 158 may include the same or similar material as that of the protective insulating layer 154 .

The first source/drain 110 may be disposed on the first active fin 105 and on opposite sides of the first gate structure 140 . For example, the first source/drain 110 may have a recessed region in which the top surface thereof is disposed higher than the top surface of the first active fin 105 while the first source/drain 110 is disposed in the first active fin 105 in the raised shape. For example, the first source/drain 110 may be connected or fused to each other on the first active fin 105 . The first source/drain 110 may be an epitaxial layer grown through a selective epitaxy process. The first source/drain 110 may include, for example, silicon carbon (SiC) or silicon heavily doped with N-type impurities. An intentionally undoped silicon layer may also be provided on the uppermost portion of the first source/drain 110 .

Similarly, the second source/drain 210 may be disposed in the recessed region of the second active fin 205 and may be disposed on the opposite side of the second gate structure 240 . The second source/drain 210 may be disposed in the source region or the drain region of the second transistor 100B. The top surface of the second source/drain electrode 210 may be disposed at substantially the same level as the bottom surface of the second gate structure 240 . In exemplary embodiments of the inventive concept, the second source/drain 210 may have a raised source/drain shape in which a top surface thereof is disposed higher than a bottom surface of the second gate structure 240 . The embedded second source/drain 210 may be connected or fused to each other on the second active fin 205 . The second source/drain 210 may be an epitaxial layer grown through a selective epitaxy process. The second source/drain 210 may include, for example, silicon germanium (Si-Ge) heavily doped with P-type impurities. The second source/drain 210 including silicon germanium may increase the mobility of holes by applying compressive stress to the channel region of the second active fin 205 including silicon (Si). The second source/drain 210 including silicon germanium (Si-Ge) may include a plurality of regions having germanium (Ge) contents different from each other.

In an exemplary embodiment of the inventive concept, an interlayer dielectric may be provided on the etch stop layer 158 around the first contact 160 and the second contact 260 . For example, interlayer dielectrics may include borophosphosilicate glass (BPSG), Tonen silazane (TOSZ), undoped silicate glass (USG), spin-on glass (SOG), flowable oxide (FOX), Tetraethyl orthosilicate (TEOS), oxides of high density plasma CVD (HDP-CVD), etc.

As semiconductor devices have been miniaturized, the distance between the first gate structure and the second gate structure can be reduced. With the trend toward miniaturization, the space for source/drain regions decreases. The present inventive concept provides various methods of protecting the spacers using disposable spacers and selectively removing the disposable spacers to secure spaces for forming source/drain electrodes.

Hereinafter, a method of manufacturing a semiconductor device according to an exemplary embodiment of the inventive concept will be described with reference to the accompanying drawings.

FIGS. 3A to 3E and FIGS. 4A to 4F illustrate a method of fabricating a semiconductor device according to an exemplary embodiment of the present inventive concept, and will be understood as part of the method of fabricating the semiconductor device illustrated in FIGS. 1 and 2 . Example.

3A to 3E are cross-sectional views illustrating a process of forming the first source/drain 110 in the first region I according to an exemplary embodiment of the inventive concept, and FIGS. 4A to 4F are diagrams illustrating a process according to the inventive concept. A cross-sectional view of a process of forming the second source/drain 210 in the second region II of the exemplary embodiment.

Referring to FIG. 3A , a first active fin 105 and a first sacrificial gate structure DG1 crossing the first active fin 105 are formed in the first region I of the substrate 101 , and the second active fin 105 is formed in the second region II of the substrate 101 . The active fin 205 and the second sacrificial gate structure DG2 crossing the second active fin 205 .

A mask pattern may be formed on the substrate 101 . The substrate 101 may be etched using the mask pattern as an etch mask to form the first active fin 105 in the first region I and the second active fin 205 in the second region II. Trenches may be formed between the first active fins 105 and between the second active fins 205 through an etching process, respectively. The lower portion of the trench may be filled with insulating material to form an isolation layer. As a result, upper portions of the first and second active fins 105 and 205 may protrude from the top surface of the isolation layer.

The first sacrificial gate structure DG1 and the second sacrificial gate structure DG2 are formed to cover the first active fin 105 and the second active fin 205 . Each of the first sacrificial gate structure DG1 and the second sacrificial gate structure DG2 may be a structure in which the sacrificial gate insulating layer 132 , the sacrificial gate 135 and the gate mask pattern 136 are stacked, and may be after the stacking It is formed by anisotropic etching. For example, the sacrificial gate insulating layer 132 may include silicon oxide, and the sacrificial gate 135 may include polysilicon. The gate mask pattern 136 may be silicon nitride.

3B , spacers 150 and first disposable spacers 152 may be sequentially formed in the first region I and the second region II of the substrate 101 to cover the first sacrificial gate structure DG1 and the second sacrificial gate structure Opposite sidewalls of DG2.

The spacer 150 may be formed of a low-k dielectric, and the first disposable spacer 152 may include a material having etch selectivity with respect to the spacer 150 in view of electrical properties. In exemplary embodiments of the present inventive concept, the spacer 150 and the first disposable spacer 152 may include different materials from each other. For example, spacer 150 may include SiO ₂ and/or SiON, and first disposable spacer 152 may include SiN and/or Al ₂ O ₃ . The spacers 150 and the first disposable spacers 152 may be formed by, for example, an atomic layer deposition (ALD) process.

Referring to FIG. 3C , a first mask M1 is formed in the second region II to expose the first region I of the substrate 101 . In the first region I of the substrate 101, the first disposable spacers 152 are removed from the spacers 150 using the first mask M1.

A first mask M1 (eg, a spin-on hard mask (SOH)) may be formed to cover the second region II. In the first region I of the substrate 101, the first disposable spacers 152 may be removed from the spacers 150 using a wet etching process. As described above, the removal of the first disposable spacer 152 may be performed before forming the first recess for securing the first source/drain forming space.

In the process of removing the first disposable spacers 152 by wet etching, even if the etching rate of the spacers 150 is low, the edges of the lower ends of the spacers 150 may be etched due to the concentration of wet etching thereon. Since the edge of the lower end of the spacer 150 is etched, the first undercut C1 may be formed in the lower end of the spacer 150 along the extending direction of the first sacrificial gate structure DG1. For example, the first undercut C1 may be formed in a region where the vertical portion of the spacer 150 meets the horizontal portion of the spacer 150 . For example, the first undercut C1 may extend toward the first sacrificial gate structure DG1. Such a first undercut C1 may be obtained by selectively removing the first disposable spacers 152 using etching.

Referring to FIG. 3D, a portion of the first active fin 105 may be removed to form a first recess R1 on an opposite side adjacent to the first sacrificial gate structure DG1.

Anisotropic dry etching may be selectively applied to the spacers disposed in the first region I by using the first mask M1. In the process of the anisotropic dry etching, the portion of the spacer 150 disposed between the first sacrificial gate structures DG1 in the first region I may be connected to the portion of the spacer 150 disposed on top of the first sacrificial gate structure DG1 Portions on the surface are selectively removed together.

By using such spacers, a first recess R1 may be formed in a portion of the first active fin 105 located on the opposite side of the first sacrificial gate structure DG1 and adjacent to the first sacrificial gate structure DG1. An isotropic dry etching or wet etching process may be additionally performed during the formation of the first recess R1. As a result, as shown in the drawings, a portion of the first recess R1 may extend to the lower side of the spacer 150 .

Referring to FIG. 3E, the first mask M1 may be removed, and the first source/drain 110 may be formed adjacent to the first sacrificial gate structure DG1 on opposite sides of the first sacrificial gate structure DG1.

After removing the first mask M1, a pre-cleaning process for a selective epitaxial growth (SEG) process may be performed on the first recesses R1. The pre-cleaning process may be performed through a wet cleaning process, a dry cleaning process, or a combination thereof. The insulating layer portions (eg, 136, 150, and 152) may be provided as barrier layers that allow epitaxial layers to be selectively grown in the first recesses R1 during a subsequent epitaxial growth process.

An epitaxial layer is grown using a selective epitaxial growth process to fill the first recesses R1 so that the first source/drain electrodes 110 can be formed. The top surfaces of the first source/drain electrodes 110 may be formed to a position higher than the top surfaces of the first active fins 105 . However, the position of the top surface of the first source/drain 110 is not limited to the position shown in the drawings. The first source/drain 110 may be, for example, a silicon (Si) layer. During the growth process, the first source/drain 110 may be heavily doped with N-type impurities such as phosphorus (P) in situ. In the final step of the growth process, an undoped silicon layer may be formed on the uppermost portion of the first source/drain 110 by stopping the supply of N-type impurities. The first source/drain 110 may be fused to each other while growing on the first active fin 105 . The first source/drain 110 may be formed using a molecular beam epitaxy (MBE) process, a chemical vapor deposition (CVD) process, a reduced pressure chemical vapor deposition (RPCVD) process, or an ultra-high vacuum chemical vapor deposition (UHV CVD) process.

Then, a second source/drain forming process may be performed in the second region II of the substrate 101 . The process will be described with reference to FIGS. 4A to 4F .

Referring to FIG. 4A , the first disposable spacer 152 may be removed from the spacer 150 in the second region II of the substrate 101 .

The first disposable spacers 152 may be removed from the spacers 150 in the second region II of the substrate 101 by using a wet etching process. Except for the gate mask pattern 136, other portions are not etched in the first region I, and thus, the first disposable spacers 152 may be selectively removed in the second region II. By removing the first disposable spacers 152, sufficient space for forming the second source/drain can be ensured.

Similar to the process of FIG. 3C , in this process, the wet etching may be concentrated on the edges of the lower ends of the spacers 150 . Therefore, edges of the lower ends of the spacers 150 may be etched to form second undercuts C2 ′ in the lower ends of the spacers 150 along the extending direction of the second sacrificial gate structure DG2 . For example, the second undercut C2 ′ may be formed in a region where the vertical portion of the spacer 150 meets the horizontal portion of the spacer 150 . For example, the second undercut C2' may extend toward the second sacrificial gate structure DG2.

Referring to FIG. 4B , a second disposable spacer 154 may be formed on the spacer 150 in the first region I and the second region II of the substrate 101 .

The second disposable spacer 154 may comprise a material having an etch selectivity relative to the spacer 150 . For example, the second disposable spacer 154 may include SiN and/or Al ₂ O ₃ . In exemplary embodiments of the present inventive concept, the second disposable septum 154 may include the same material as that of the first disposable septum 152 . The second disposable spacers 154 may be formed by, for example, an atomic layer deposition (ALD) process.

Referring to FIG. 4C , a second mask M2 may be formed in the first region I to expose the second region II of the substrate 101 . The second disposable spacers 154 may be removed from the spacers 150 in the second region II by using a mask (eg, the second mask M2).

Similar to the process shown in FIG. 3C , the second mask M2 may be formed to cover the first region I of the substrate 101 , and the second mask M2 may be removed from the spacers 150 in the second region II of the substrate 101 by using a wet etching process Disposable spacer 154 . As described above, the selective removal process of the second disposable spacers 154 in the second region II may be performed before forming the second recess for securing the second source/drain forming space.

In the process of removing the second disposable spacer 154, the edge of the lower end of the spacer 150 may be etched due to the concentration of wet etching thereon. The second undercut C2 may be additionally etched to extend further toward the second sacrificial gate structure DG2. In the drawing, the dashed line represents the outline of the previous second undercut C2'. In the present embodiment, one etch is applied to the edges (eg, corners) of the lower ends of the spacers 150 in the first region I, and two etchings are applied to the edges of the lower ends of the spacers 150 in the second region II. Thus, under similar wet etch conditions, the second undercut C2 may have a larger profile (eg, depth and/or size) than the first undercut C1. As described above, in the case of the present embodiment, the first undercut C1 and the second undercut C2 may be formed to have sizes significantly different from each other.

4D, a portion of the second active fin 205 is removed to form a second recess R2 adjacent to the second sacrificial gate structure DG2 on the opposite side of the second sacrificial gate structure DG2.

Similar to the process of FIG. 3D, a portion of the second active fin 205 may be anisotropically dry etched using spacers 150 to be adjacent to the second sacrificial gate structure DG2 on the opposite side of the second sacrificial gate structure DG2 The second recess R2 is formed on the ground. The second recess R2 may have a shape extending to the lower side of the spacer 150 . For this, an isotropic dry etching process or a wet etching process may be additionally performed.

4E, after removing the second mask M2, a second source/drain 210 may be formed adjacent to the second sacrificial gate structure DG2 on the opposite side of the second sacrificial gate structure DG2.

Similar to the process of FIG. 3E , in this embodiment, an epitaxial layer may be grown to fill the second recess R2 by using a pre-clean process and a selective epitaxial growth process together. Therefore, the second source/drain 210 may be formed.

During the growth process, the second source/drain 210 may be heavily doped with P-type impurities such as boron (B) in situ. During the growth process, the concentration of germanium (Ge) may be controlled such that the second source/drain 210 may have a higher germanium (Ge) concentration in the upper region than in the lower region. The second source/drain 210 may be formed to be fused while growing on the second active fin 205 . For example, the second source/drain may be formed using a molecular beam epitaxy (MBE) process, a chemical vapor deposition (CVD) process, a reduced pressure chemical vapor deposition (RPCVD) process, or an ultra-high vacuum chemical vapor deposition (UHV CVD) process 210.

Referring to FIG. 4F , an etch stop layer 158 may be formed to cover sidewalls of the first and second sacrificial gate structures DG1 and DG2 and tops of the first and second source/drain 110 and 210 surface.

In the present embodiment, the second sacrificial gate structure DG2, The surfaces of the spacers 150 and the second source/drain electrodes 210 form an etch stop layer 158 with a substantially uniform thickness. For example, the etch stop layer 158 may be formed by an atomic layer deposition (ALD) process. The etch stop layer 158 may include silicon nitride, silicon oxynitride, or a combination thereof. Although not limited thereto, in exemplary embodiments of the present inventive concept, the etch stop layer 158 may include the same or similar material as that of the first disposable spacer 152 and the second disposable spacer 154 .

In a subsequent process, by performing a process of forming the first contact 160 and the second contact 260 connected to the first source/drain 110 and the second source/drain 210, respectively, and using the first gate structure 140 and the second gate structure 240 replace the first sacrificial gate structure DG1 and the replacement process of the second sacrificial gate structure DG2 together to manufacture the semiconductor device shown in FIG. 2 .

In the replacement process, an interlayer dielectric is formed on the substrate 101 to cover the first sacrificial gate structure DG1 and the second sacrificial gate structure DG2. The interlayer dielectric is planarized to expose the top surfaces of the first sacrificial gate structure DG1 and the second sacrificial gate structure DG2. The gate mask pattern 136, the sacrificial gate 135, and the sacrificial gate insulating layer 132 are removed to form openings. Gate insulating layers 142 and 242, bottom gate electrodes 145 and 245, and top gate electrodes 147 and 247 are sequentially formed in the openings, and then planarized. Accordingly, as shown in FIG. 2 , the first gate structure 140 and the second gate structure 240 may be formed.

Contact holes are formed to be connected to the first source/drain 110 and the second source/drain 210 , respectively, by using the etch stop layer 158 . Conductive stoppers 161 and 261 are formed, and contact holes are filled with contact plugs 165 and 265 . Accordingly, the first contact 160 and the second contact 260 are formed to be connected to the first source/drain 110 and the second source/drain 210, respectively. For example, the conductive barriers 161 and 261 may be formed of metal nitride such as TiN, TaN or WN. For example, the contact plugs 165 and 265 may be formed of tungsten (W), cobalt (Co), titanium (Ti), alloys thereof, or combinations thereof.

In the above-described method of manufacturing a semiconductor device, both the first disposable spacer and the second disposable spacer are materials having etching selectivity with respect to the spacers, and include the same or similar materials to each other. However, some disposable spacers may be formed from a material similar to that of the spacer. Additionally, the second disposable spacer was not removed (see Figure 4F), and even remained in the final structure. However, the second disposable spacer can also be removed without remaining in the final structure.

Such modified embodiments will be described with reference to FIGS. 5A to 5D and FIGS. 6A to 6F .

5A , spacers 150 and first disposable spacers 153 are sequentially formed in the first region I and the second region II of the substrate 101 to cover the first sacrificial gate structure DG1 and the second sacrificial gate structure The two side walls of DG2.

This process will be understood with reference to the process of FIGS. 3A and 3B . Unlike the method according to the previous embodiment, the first disposable spacer 153 employed in this embodiment may be formed of an oxide, such as SiO ₂ , of a material similar to the spacer 150 . For example, the spacer 150 may be SiON.

Referring to FIG. 5B , a first mask M1 may be formed in the second region II to expose the first region I of the substrate 101 .

In the present embodiment, the first region may be formed by forming a mask in the first region I and the second region II of the substrate 101 using a material such as SOH and selectively removing the mask portion provided in the first region I Mask M1. When the mask portion disposed in the first region I is removed, it may be removed in the first region I of the substrate 101 together with the first disposable spacers 153, and the spacers 150 may be exposed. As described above, in the present embodiment, the process of removing the first disposable spacers 153 in the first region I may be performed without an additional etching process.

Referring to FIG. 5C, a portion of the first active fin 105 may be removed to form a first recess R1 adjacent to the first sacrificial gate structure DG1 on an opposite side of the first sacrificial gate structure DG1.

Similar to the process described with reference to FIG. 3D , the process may be performed by anisotropic dry etching using the spacers 150 of the first region I. In exemplary embodiments of the present inventive concept, an isotropic dry etching process or a wet etching process may be additionally performed during the formation of the first recess R1.

Referring to FIG. 5D , the first mask M1 may be removed, and the first source/drain 110 may be formed adjacent to the first sacrificial gate structure DG1 on opposite sides of the first sacrificial gate structure DG1 .

Similar to the process described with reference to FIG. 3E , the process of forming the first source/drain 110 may be performed through a selective epitaxial growth process. In this embodiment, the portion of the first disposable spacer 153 disposed in the second region II may also be removed during the removal of the first mask M1.

6A to 6F are cross-sectional views illustrating a process of forming source/drain electrodes in a second region in a method of fabricating a semiconductor device according to an exemplary embodiment of the inventive concept.

Referring to FIG. 6A , a second disposable spacer 154 may be formed on the spacer 150 in the first region I and the second region II of the substrate 101 .

This process may be performed similarly to the process described with reference to FIG. 4B. The second disposable spacer 154 may comprise a material having an etch selectivity relative to the spacer 150 . For example, the second disposable spacer 154 may include SiN and/or Al ₂ O ₃ .

6B , a second mask M2 may be formed in the first region I to expose the second region II of the substrate 101, and the second mask M2 may be removed from the spacers 150 in the second region II by using the second mask M2 Disposable spacer 154 .

Similar to the process described with reference to FIG. 4C , this process may be performed through a wet etching process using the second mask M2 covering the first region I. During removal of the second disposable spacer 154, the edge of the lower end of the spacer 150 may be etched due to the concentration of wet etch thereon to form a second undercut C2.

Referring to FIG. 6C, a portion of the second active fin 205 may be removed to form a second recess R2 adjacent to the second sacrificial gate structure DG2 on the opposite side of the second sacrificial gate structure DG2.

Similar to the process described with reference to FIG. 4D , the second active fin 205 on the opposite side of the second sacrificial gate structure DG2 and the The process is performed on adjacent portions of the two sacrificial gate structures DG2. In exemplary embodiments of the inventive concept, an anisotropic dry etching process or a wet etching process may be additionally performed.

Referring to FIG. 6D , a second source/drain 210 may be formed adjacent to the second sacrificial gate structure DG2 on an opposite side of the second sacrificial gate structure DG2 in the second region II.

Similar to the process described with reference to FIG. 4E, this process may be performed by performing a selective epitaxial growth process adjacent to the second sacrificial gate structure DG2 on the opposite side of the second sacrificial gate structure DG2 in the second region II .

Referring to FIG. 6E , the second disposable spacer 154 may be removed from the spacer 150 in the first region I of the substrate 101 .

In this embodiment, the second disposable spacers 154 may be removed from the spacers 150 in the first region I of the substrate 101 by using a wet etching process. During the removal of the second disposable spacer 154, the edge of the lower end of the spacer 150 may be etched due to the concentration of wet etching thereon, thereby forming a first undercut in the extending direction of the first sacrificial gate structure DG1 C1.

Referring to FIG. 6F , an etch stop layer 158 may be formed to cover sidewalls of the first and second sacrificial gate structures DG1 and DG2 and tops of the first and second source/drain 110 and 210 surface.

The etch stop layer 158 may be formed to have a substantially uniform thickness on the surface of the substrate 101 . For example, the etch stop layer 158 may cover the entire surface of the substrate 101 . For example, the etch stop layer 158 may be formed by an atomic layer deposition (ALD) process. For example, the etch stop layer 158 may include silicon nitride, silicon oxynitride, or a combination thereof, but the material of the etch stop layer 158 is not limited thereto. In exemplary embodiments of the present inventive concept, the etch stop layer 158 may include the same or similar material as that of the second disposable spacer 154 .

According to the present embodiment, in structure, unlike the configuration shown in FIG. 2 , both the first transistor and the second transistor may similarly have a spacer structure including a spacer 150 and an etch stop layer 158 without protective insulation layer 154 (see Figure 2).

7A to 7C are cross-sectional views illustrating a process of forming a first source/drain in a first region in a method of fabricating a semiconductor device according to an exemplary embodiment of the inventive concept, and FIGS. 8A to 8F are views illustrating a process of forming a first source/drain in a first region. A cross-sectional view illustrating a process of forming a second source/drain in a second region in a method of fabricating a semiconductor device according to an exemplary embodiment of the inventive concept.

In the present embodiment, unlike the method of manufacturing a semiconductor device according to the above-described embodiments, the gate mask pattern may have a structure including a plurality of layers formed of materials different from each other. In this case, damage to the first sacrificial gate structure and the second sacrificial gate structure may be reduced during the formation of the source/drain.

Referring to FIG. 7A , spacers 150 and first disposable spacers 152 may be sequentially formed in the first region I and the second region II of the substrate 101 to cover the first sacrificial gate structure DG1 and the second sacrificial gate Sidewall of structure DG2.

The gate mask pattern 136 may include two or more layers. For example, the gate mask pattern 136 may include a first layer 136a and a second layer 136b. The first layer 136a includes a material that is etch selective relative to the spacers 150 , and the second layer 136b is disposed on the first layer 136a and includes a material that is etch selective relative to the first disposable spacers 152 . In the present embodiment, the gate mask pattern 136 may have a three-layer structure, and may further include a third layer 136c disposed on the second layer 136b and including a material having etching selectivity with respect to the spacers 150 .

For example, in the case where the spacer 150 may include SiO ₂ and/or SiON and the first disposable spacer 152 may include SiN and/or Al ₂ O ₃ , the first layer 136a and the third layer 136c may include SiN and/or Al ₂ O ₃ , and the second layer 136b may include SiO ₂ and/or SiON.

7B, the first disposable spacers 152 may be removed from the spacers 150 in the first region I of the substrate 101 by using the first mask M1, and a portion of the first active fins 105 may be removed to A first recess R1 is formed on the opposite side of a sacrificial gate structure DG1 adjacent to the first sacrificial gate structure DG1.

This process may be performed similar to the process described with reference to FIGS. 3C and 3D . During the removal of the first disposable spacer 152 , a first undercut C1 ′ may be formed on the edge of the lower end of the spacer 150 along the extending direction of the first sacrificial gate structure DG1 . The top surface of the first sacrificial gate structure DG1 may be exposed in the anisotropic etching process forming the first recess R1.

7C , after removing the first mask M1 in the second region II, adjacent to the first sacrificial gate structure DG1 may be formed in the first region I on the opposite side of the first sacrificial gate structure DG1 The first source/drain 110 . Similar to the process described with reference to FIG. 3E , the process of forming the first source/drain 110 may be performed through a selective epitaxial growth process.

Referring to FIG. 8A , the first disposable spacer 152 may be removed from the spacer 150 in the second region II of the substrate 101 .

Similar to the process described with reference to FIG. 4A , the process may remove the first disposable spacers 152 in the second region II by using a wet etching process. During removal of the first disposable spacer 152 , the edge of the lower end of the spacer 150 may also be etched due to the concentration of wet etching thereon, thereby extending along the second sacrificial gate structure DG2 in the lower end of the spacer 150 The direction forms a second undercut C2'. In this process, even if the third layer 136c is removed from the first sacrificial gate structure DG1, the second layer 136b may serve as an etch stop layer. The gate insulating pattern 136 having the multi-layer structure may reduce the etching of the first sacrificial gate structure DG1.

Referring to FIG. 8B , a second disposable spacer 154 may be formed on the spacer 150 in the first region I and the second region II of the substrate 101 .

This process may be performed similarly to the process described with reference to FIG. 4B. The second disposable spacer 154 may comprise a material having an etch selectivity relative to the spacer 150 . For example, the second disposable spacer 154 may include SiN and/or Al ₂ O ₃ .

8C , the second disposable spacers 154 may be removed from the spacers 150 in the second region II by using the second mask M2, and a second recess R2 may be formed in the second region II.

This process may be performed similarly to the process described with reference to FIGS. 4C and 4D . The second disposable spacers 154 in the second region II may be removed by a wet etching process using the second mask M2 covering the first region I. During removal of the second disposable spacer 154, the wet etch may be focused on the edge of the lower end of the spacer 150 to form an extended second undercut C2 in the second region II. A portion of the second active fin 205 may be anisotropically dry etched adjacent to the second sacrificial gate structure DG2 on the opposite side of the second sacrificial gate structure DG2 in the second region II using the spacers 150 . In exemplary embodiments of the inventive concept, an isotropic dry etching process or a wet etching process may be additionally performed.

Referring to FIG. 8D , a second source/drain 210 may be formed adjacent to the second sacrificial gate structure DG2 on an opposite side of the second sacrificial gate structure DG2 in the second region II.

Similar to the process described with reference to FIG. 4E, this process may be performed by performing a selective epitaxial growth process adjacent to the second sacrificial gate structure DG2 on the opposite side of the second sacrificial gate structure DG2 in the second region II .

Referring to FIG. 8E , the second disposable spacer 154 may be removed from the spacer 150 in the first region I of the substrate 101 . During removal of the second disposable spacer 154, the wet etch may focus on the edge of the lower end of the spacer 150 to form the extended first undercut C1. In this process, even though the third layer 136c is removed from the second sacrificial gate structure DG2, the second layer 136b may function as an etch stop layer. The gate insulating pattern 136 having the multi-layer structure may reduce the etching of the second sacrificial gate structure DG2.

Referring to FIG. 8F , an etch stop layer 158 may be formed on the substrate 101 .

The etch stop layer 158 may be formed to have a substantially uniform thickness on the surface of the substrate 101 . For example, the etch stop layer 158 may be formed by an atomic layer deposition (ALD) process. For example, the etch stop layer 158 may include silicon nitride, silicon oxynitride, or a combination thereof. Although not limited thereto, in exemplary embodiments of the present inventive concept, the etch stop layer 158 may include the same or similar material as that of the second disposable spacer 154 .

According to example embodiments of the inventive concept, narrow spaces between gate structures may be formed through a simplified process using an outer spacer layer (also referred to as a “one-shot spacer”) that may be selectively removed during subsequent processes source/drain is stably formed. Additionally, spacers with improved electrical properties (eg, low-k) can be achieved through the use of disposable spacers.

While the inventive concept has been specifically shown and described with reference to exemplary embodiments of the inventive concept, it will be apparent to those of ordinary skill in the art that the inventive concept can be implemented without departing from the spirit and scope of the inventive concept as defined by the claims. Where appropriate, various changes in form and detail may be made therein.

Claims (20)

1. A method of manufacturing a semiconductor device, the method comprising: forming active fins and a sacrificial gate structure intersecting the active fins in the first region of the substrate; forming first spacers and second spacers on the substrate to cover the sacrificial gate structures; forming a mask in a second region of the substrate to expose the first region of the substrate; removing the second spacer from the first spacer in the first region of the substrate by using the mask; forming recesses at opposite sides of the sacrificial gate structure by removing portions of the active fins; forming a source electrode and a drain electrode in the recess; and An etch stop layer is formed to cover both sidewalls of the sacrificial gate structure and top surfaces of the source and drain electrodes. 2. The method of claim 1, wherein the second spacer comprises a material having an etch selectivity relative to the first spacer. 3. The method of claim 2, wherein the step of removing the second spacer is performed by wet etching. 4. The method of claim 3, wherein, in the step of removing the second spacer, an undercut is formed in a lower end of the first spacer. 5. The method of claim 1, wherein the first spacer comprises _SiO2 or SiON. 6. The method of claim 5, wherein the _second spacer comprises SiN or _Al2O3 . 7. The method of claim 1, further comprising: The mask is removed from the second region of the substrate between the step of forming the recess and the step of forming the source and drain electrodes. 8. The method of claim 7, further comprising: The second spacer is removed from the second region of the substrate between the step of forming the source and drain and the step of forming the etch stop layer. 9. The method of claim 1, wherein the sacrificial gate structure comprises a sacrificial gate layer and a gate mask pattern disposed on the sacrificial gate layer. 10. The method of claim 9, wherein the gate mask pattern comprises a first layer and a second layer, the first layer comprising a material having an etch selectivity with respect to the first spacer, The second layer is disposed on the first layer and includes a material having etch selectivity with respect to the second spacer. 11. A method of fabricating a semiconductor device, the method comprising: A first active fin and a first sacrificial gate structure intersecting the first active fin are formed in a first region of the substrate, and a second active fin and a second active fin are formed in a second region of the substrate the second sacrificial gate structure crossed by the second active fins; First spacers and second spacers are formed in the first and second regions of the substrate to cover sidewalls of the first sacrificial gate structure and the second sacrificial gate structure the side wall; forming a first mask in the second region of the substrate to expose the first region of the substrate; removing the second spacer from the first spacer in the first region of the substrate; forming a first recess at opposite sides of the first sacrificial gate structure by removing portions of the first active fin; removing the first mask from the second region of the substrate; and A first source electrode and a first drain electrode are formed in the first recess. 12. The method of claim 11, after the step of forming the first source and the first drain, the method further comprising: removing the second spacer from the first spacer in the second region of the substrate; forming third spacers on the first spacers in the first region and the second region of the substrate; forming a second mask in the first region of the substrate to expose the second region of the substrate; removing the third spacer from the first spacer in the second region of the substrate by using the second mask; forming a second recess at an opposite side of the second sacrificial gate structure by removing a portion of the second active fin; forming a second source electrode and a second drain electrode in the second recess; and An etch stop layer is formed in the first region and the second region to cover the sidewalls of the first sacrificial gate structure and the sidewalls of the second sacrificial gate structure. 13. The method of claim 12, further comprising: The third spacer is removed from the first spacer in the first region of the substrate between the step of forming the second recess and the step of forming the etch stop layer . 14. The method of claim 13, wherein each of the first sacrificial gate structure and the second sacrificial gate structure comprises a sacrificial gate layer and a sacrificial gate layer disposed on the sacrificial gate layer gate mask pattern, and The gate mask pattern includes a first layer, a second layer, and a third layer that are sequentially stacked, and the second layer includes a material having an etch selectivity with respect to the first layer and the third layer . 15. The method of claim 14, wherein in the step of removing the second spacer from the second region of the substrate, the third layer is removed from the first sacrificial gate structure is removed, and the second layer acts as an etch stop layer in the first sacrificial gate structure, and In the step of removing the third spacer from the first region of the substrate, the third layer is removed from the second sacrificial gate structure, and the second layer serves as the Etch stop layer in the second sacrificial gate structure. 16. The method of claim 12, wherein the first spacer comprises at least one of _SiO2 and SiON, and The second spacer and the third spacer include SiN or Al ₂ O ₃ . 17. The method of claim 11, wherein the step of forming the first mask comprises forming the first mask in the first region and the second region of the substrate , and remove the mask portion of the first mask disposed in the first region, The step of removing the mask portion disposed in the first region includes removing the second spacer in the first region of the substrate, and The step of removing the first mask includes removing the second spacer from the first spacer in the second region. 18. The method of claim 17, after the step of forming the first source and the first drain, the method further comprising: forming third spacers on the first spacers in the first region and the second region of the substrate; forming a second mask in the first region of the substrate to expose the second region of the substrate; removing the third spacer from the first spacer in the second region of the substrate by using the second mask; forming a second recess at an opposite side of the second sacrificial gate structure by removing portions of the second active fin; forming a second source electrode and a second drain electrode in the second recess; and An etch stop layer is formed in the first region and the second region to cover the sidewalls of the first sacrificial gate structure and the sidewalls of the second sacrificial gate structure. 19. The method of claim 18, further comprising: The third spacer is removed from the first spacer in the first region of the substrate between the step of forming the second recess and the step of forming the etch stop layer . 20. The method of claim 18, wherein the first spacer comprises _SiO2 or SiON, and Wherein, the second spacer includes oxide, and the third spacer includes SiN or Al ₂ O ₃ .

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