CN111800138B - An electronic trimming reference voltage analog-to-digital conversion device - Google Patents
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Abstract
本发明涉及一种电微调参考电压模数转换装置，该装置包括模数转换器和向该模数转换器提供参考电压的电微调参考电压电路。电微调参考电压电路包括：带隙基准源、可调正参考电压产生电路、负参考电压产生电路和电微调电路。电微调电路根据第一输入电压生成第一控制电压，根据第二输入电压生成第二控制电压；可调正参考电压产生电路接收并根据第一控制电压和第二控制电压处理带隙基准源产生的带隙电压，生成正参考电压；负参考电压产生电路接收并根据正参考电压生成负参考电压。将上述装置应用于MEMS闭环数字加速度计系统，在封装后用电微调的方式修正并固化模数转换器的参考源电压，使得模数转换器达到更高的分辨率，加速度计系统达到更高的精度。
The invention relates to an analog-to-digital conversion device for an electrically trimmed reference voltage, which comprises an analog-to-digital converter and an electrically trimmed reference voltage circuit for supplying a reference voltage to the analog-to-digital converter. The electric trimming reference voltage circuit includes a bandgap reference source, an adjustable positive reference voltage generating circuit, a negative reference voltage generating circuit and an electric trimming circuit. The electric trimming circuit generates a first control voltage according to the first input voltage, and generates a second control voltage according to the second input voltage; the adjustable positive reference voltage generating circuit receives and processes the bandgap reference source according to the first control voltage and the second control voltage to generate The bandgap voltage of , generates a positive reference voltage; the negative reference voltage generating circuit receives and generates a negative reference voltage according to the positive reference voltage. The above device is applied to the MEMS closed-loop digital accelerometer system, and the reference source voltage of the analog-to-digital converter is corrected and solidified by electrical trimming after packaging, so that the analog-to-digital converter can achieve higher resolution and the accelerometer system can achieve higher accuracy.
Description
Technical Field
The invention relates to a capacitive inertial sensor, in particular to an electric trimming reference voltage analog-to-digital conversion device.
Background
Capacitive inertial sensors generally comprise inertial sensors such as acceleration sensors and gyroscopes, which measure in real time parameters such as the acceleration of the vehicle with respect to the ground, to determine the position of the vehicle and the parameters of the earth gravitational field, and convert the measured variations into variations in capacitance.
The following description will take a mems (micro Electro Mechanical system) capacitive inertial sensor as an example.
With the increasing maturity of the MEMS (micro Electro Mechanical system) technology, the MEMS capacitive inertial sensor has the advantages of small size, high sensitivity, stable dc characteristic, small drift, low power consumption, small temperature coefficient, etc. and is widely used, however, the MEMS capacitive inertial sensor has small capacitance change, so the MEMS capacitive inertial sensor servo circuit is required to have the characteristics of high precision, good linearity, large dynamic range, etc.
The existing MEMS capacitive inertial sensor servo circuit is divided into a closed loop structure and an open loop structure from the structure, and an output signal is divided into an analog signal output and a digital signal output. The servo circuit of the capacitive inertial sensor with an open-loop structure is restricted in linearity, measuring range, dynamic range and the like; the closed loop implementation scheme is divided into two schemes, one scheme is a negative feedback scheme based on an analog closed loop, the other scheme is a negative feedback scheme based on a digital closed loop, aiming at the defects of integral saturation and the like of the existing mainstream MEMS analog closed-loop accelerometer system, an analog-to-digital converter is introduced to convert analog signals output by a capacitance-voltage conversion circuit into digital signals, and then the digital signals are processed by a digital loop filter implemented by an FPGA (field programmable gate array).
In the negative feedback scheme of the digital closed loop, the resolution capability of the system is determined by the quantization bit number of the analog-to-digital converter, and the measurement accuracy of the system is limited by the conversion accuracy of the analog-to-digital converter. In order to improve the resolution of the system, it is common practice to increase the number of quantization bits of the analog-to-digital converter, however, the conventional high-order analog-to-digital converter is not ideal in terms of conversion speed. The analog-digital converter for electrically trimming the reference voltage is adopted, the measurement precision of the analog-digital converter is improved by properly reducing the reference voltage, the design difficulty is reduced, the influence of quantization noise of the analog-digital converter on the system performance is reduced, and the requirements of the system on the precision and the speed of the analog-digital converter are met.
Under the condition of closed-loop operation of the MEMS capacitive inertial sensor system, the output of a capacitance-voltage conversion circuit behind the MEMS sensitive unit is tested, and the final reference voltage of the analog-digital converter is determined in an electric fine tuning mode according to the range of the capacitance-voltage conversion circuit.
The reference voltage of an analog-to-digital converter in the existing MEMS capacitive inertial sensor servo circuit is usually the maximum reference voltage within a certain power supply range, and the widest input range can be realized, but the method is not favorable for improving the system precision. In addition, the reference voltage of the analog-to-digital converter is dynamically adjusted by monitoring the output of the capacitance-to-voltage conversion circuit behind the MEMS sensitive unit, and the defect is that the real-time change of the reference voltage can reduce the speed of the system, and the reference voltage needs time for stabilization after being modified, so the speed of the system is reduced.
Disclosure of Invention
The invention aims to solve the technical problems and provides an electric fine-tuning reference voltage analog-to-digital conversion device which is applied to an MEMS closed-loop digital accelerometer system and can realize high-precision application of an analog-to-digital converter.
To achieve the above object, in a first aspect, an embodiment of the present invention provides an electrical trimming reference voltage analog-to-digital conversion apparatus, which includes an analog-to-digital converter and an electrical trimming reference voltage circuit that provides a reference voltage to the analog-to-digital converter. The electrical trimming reference voltage circuit comprises: the circuit comprises a band gap reference source, an adjustable positive reference voltage generating circuit, a negative reference voltage generating circuit and an electric fine tuning circuit. The band-gap reference source is used for generating band-gap voltage; the electric trimming circuit is used for generating a first control voltage according to the first input voltage and/or generating a second control voltage according to the second input voltage; the adjustable positive reference voltage generating circuit is used for receiving the first control voltage and the second control voltage, processing the band gap voltage according to the first control voltage and the second control voltage and generating a positive reference voltage; the negative reference voltage generating circuit is used for receiving the positive reference voltage and generating a negative reference voltage according to the positive reference voltage.
In one embodiment, the adjustable positive reference voltage generating circuit comprises a first switch, a second switch, a first amplifier, a ground resistor, a first resistor and a second resistor; the positive input end of the first amplifier is connected with a band gap voltage; the negative input end of the first amplifier is grounded after sequentially passing through the first switch and the grounding resistor; the output end of the first amplifier is connected with the negative input end of the first amplifier after sequentially passing through the second resistor and the first resistor; the voltage of the output end of the first amplifier is used as a positive reference voltage; the second resistor is connected with the second switch in parallel; the first switch adjusts the on-off according to the first control voltage; the second switch adjusts the on-off according to the second control voltage.
And the on-off of the first switch and the second switch is controlled by adjusting the electric potentials of the first control voltage and the second control voltage, and the positive reference voltage and the negative reference voltage are adjusted.
In one embodiment, the negative reference voltage generating circuit includes a second amplifier, a third resistor, and a fourth resistor. One end of the third resistor is connected with a positive reference voltage; the other end of the third resistor is connected with the negative input end of the second amplifier; the positive input end of the second amplifier is grounded; the output end of the second amplifier is connected with one end of a fourth resistor, and the other end of the fourth resistor is connected with the negative input end of the second amplifier; the voltage at the output of the second amplifier is used as a negative reference voltage.
In one embodiment, an electrical trimming circuit includes: the power supply comprises a current source, a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a first PMOS tube, a second PMOS tube, a third PMOS tube, a fifth resistor, a sixth resistor, a first electric fuse and a second electric fuse. The source electrodes of the first PMOS tube, the second PMOS tube and the third PMOS tube are connected with working voltage; the grid electrodes of the first PMOS tube, the second PMOS tube and the third PMOS tube are connected with the drain electrode of the first PMOS tube; the drain electrode of the first PMOS tube is connected with the drain electrode of the second NMOS tube; the drain electrode of the second PMOS tube is connected with the drain electrode of the third NMOS tube; the drain electrode of the third PMOS tube is connected with the drain electrode of the fourth NMOS tube; the drain electrode of the first NMOS tube, and the grid electrodes of the first NMOS tube, the second NMOS tube, the third NMOS tube and the fourth NMOS tube are connected with a current source; the source electrodes of the first NMOS tube and the second NMOS tube are grounded; the source electrode of the third NMOS tube is sequentially connected with the fifth resistor and the first electric fuse and then grounded; and the source electrode of the fourth NMOS tube is sequentially connected with the sixth resistor and the second electric fuse and then grounded.
Determining that the first electrical fuse is connected or fused according to the fifth resistor and the first input voltage applied to the connection point of the first electrical fuse to obtain a first control voltage of the connection point of the second PMOS tube and the third NMOS tube; and/or determining that the second electrical fuse is connected or fused according to the sixth resistor and the second input voltage applied by the second electrical fuse connection point to obtain a second control voltage of the third PMOS tube connection point and the fourth NMOS tube connection point.
In a second aspect, an embodiment of the present invention provides a MEMS closed-loop digital accelerometer system, which includes a MEMS sensitive chip, a readout circuit ASIC, and an FPGA digital circuit; wherein the readout circuitry ASIC comprises: capacitive voltage conversion and electrical trimming reference voltage analog to digital conversion means as in the first aspect; testing the packaged system; determining the reference voltage of the electric trimming reference voltage analog-to-digital conversion device according to the output of the capacitor voltage conversion circuit in the test; the reference voltage is corrected and solidified by means of electric fine adjustment.
The embodiment of the invention has the beneficial effects that: the electric fine-tuning reference voltage circuit disclosed in the application is combined with a low-precision analog-to-digital converter to form an electric fine-tuning reference voltage analog-to-digital conversion device, which is different from the analog-to-digital converters of the current common non-adjustable reference voltage and the dynamic adjustable reference voltage, and realizes the function of reducing the quantization noise of the analog-to-digital converter. Furthermore, the electric fine tuning reference voltage analog-to-digital conversion device is arranged in the MEMS closed-loop digital accelerometer system, so that the influence of the quantization noise of the analog-to-digital converter on the performance of the MEMS closed-loop digital accelerometer system is reduced. The modification and solidification of the internal circuit can be realized after the ASIC chip is packaged by adopting an electric fine adjustment mode.
Drawings
FIG. 1 is a diagram of an electrical trimming reference voltage analog-to-digital conversion apparatus according to an embodiment of the present invention;
FIG. 2 is an electrical trimming circuit according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of a MEMS closed-loop digital accelerometer system according to an embodiment of the invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in further detail with reference to the accompanying drawings and embodiments, and it is apparent that the described embodiments are some, but not all embodiments of the present invention. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without any creative effort, shall fall within the protection scope of the present invention.
In the following detailed description of the present invention, certain specific details are set forth in order to provide a better understanding of the present invention. It will be apparent to one skilled in the art that the present invention may be practiced without these specific details.
Fig. 1 is a diagram illustrating an electrical trimming reference voltage analog-to-digital conversion apparatus according to an embodiment of the present invention. As shown in fig. 1, the apparatus includes an analog-to-digital converter and an electrical trim reference voltage circuit that provides a reference voltage to the analog-to-digital converter. The electric trimming reference voltage circuit comprises a band gap reference source, an adjustable positive reference voltage generating circuit, a negative reference voltage generating circuit and an electric trimming circuit.
The bandgap reference source generates a bandgap voltage Vbg. The electrical trimming circuit generates a first control voltage cp1 from a first input voltage cp1_ in and a second control voltage cp2 from a second input voltage cp2_ in. The adjustable positive reference voltage generation circuit receives cp1 and cp2, processes Vbg according to cp1 and cp2 and generates a positive reference voltage Vp; the negative reference voltage generating circuit receives Vp and generates a negative reference voltage Vn according to Vp. The analog-to-digital converter receives Vp and Vn, processes the input analog signals at Vp and Vn and outputs digital signals.
As shown in fig. 1, the adjustable positive reference voltage generating circuit includes a first switch MP0, a second switch MN0, a first amplifier, a ground resistor R0, a first resistor R1, and a second resistor R2. The positive input end of the first amplifier is connected with Vbg. The negative input terminal of the first amplifier is grounded after passing through MP0 and R0 in sequence. The output end of the first amplifier is connected with the negative input end of the first amplifier after sequentially passing through R2 and R1; the voltage at the output of the first amplifier is output as Vp. R2 is connected in parallel with MN 0. MP0 is switched on or off according to cp 1; MN0 is switched on and off according to cp 2.
As shown in fig. 1, the negative reference voltage generating circuit includes a second amplifier, a third resistor R3, and a fourth resistor R4. One end of R3 is connected to Vp, i.e. connected to the output of the first amplifier; the other end of R3 is connected to the negative input of the second amplifier. The positive input of the second amplifier is grounded. The output end of the second amplifier is connected with one end of the R4, and the other end of the R4 is connected with the negative input end of the second amplifier. The voltage at the output of the second amplifier is taken as Vn.
By adjusting the potentials of cp1 and cp2, the on and off of MP0 and MN0 are controlled, and Vp and Vn generated by the reference voltage generation circuit based on Vbg are adjusted.
Fig. 2 is an electrical trimming circuit according to an embodiment of the invention. As shown in fig. 2, the electrical trimming circuit includes: the current source IB, the first NMOS transistor MN1, the second NMOS transistor MN2, the third NMOS transistor MN3, the fourth NMOS transistor MN4, the first PMOS transistor MP1, the second PMOS transistor MP2, the third PMOS transistor MP3, the fifth resistor R5, the sixth resistor R6, the first FUSE PUSE1, and the second FUSE 2.
The sources of MP1, MP2 and MP3 are connected with the working voltage; the gates of MP1, MP2 and MP3 are connected with the drain of MP 1; the drain of the MP1 is connected with the drain of the MN 2; the drain of the MP2 is connected with the drain of the MN 3; the drain of the MP3 is connected with the drain of the MN 4; the drain electrode of MN1, and the gate electrodes of MN1, MN2, MN3 and MN4 are connected with IB; the sources of MN1 and MN2 are grounded; the source of MN3 is grounded through R5 and PUSE1 in sequence; the source of MN4 is grounded through R6 and put 2 in that order. The voltage of the connection point of R5 and PUSE1 is cp1_ in; the voltage at the junction of R6 and PUSE2 is cp2_ in.
cp1_ in and cp2_ in are applied voltages by connecting off-chip pins. The voltages of the cp1 and the cp2, namely the voltages at the connection points of the MP2 and the MN3 and the connection points of the MP3 and the MN4, are changed by controlling the voltage values of the cp1_ in and/or the cp2_ in to blow the corresponding electrical fuses PUSE1 and/or PUSE 2.
In the process of specifically designing an electrical trimming circuit. For the purpose of blowing the electrical fuses PUSE1 and/or PUSE2 by applying the voltages cp1_ in and/or cp2_ in, the on-resistance of the PMOS transistor in the circuit is much larger than the on-resistance of the NMOS transistor and the resistance of other resistors. So that the voltage values applied at cp1_ in and cp2_ in are related to the voltage values of cp1 and cp2 as follows:
1) when the cp1_ in and cp2_ in pins have no voltage, that is, the cp1_ in and cp2_ in have no external voltage, the electrical fuse is not blown and remains on, and cp1 and cp2 are at low level;
2) when voltage is applied to the cp1_ in pin, FUSE1 is blown, and cp1 is switched to high level;
3) when voltage is applied to the cp2_ in pin, FUSE2 is blown, and cp2 is switched to high level;
4) when voltages are applied to the cp1_ in and cp2_ in pins, FUSE1 and FUSE2 blow, and cp1 and cp2 switch to high.
In one practical embodiment, in the device shown in fig. 1, if R0 ═ R1 ═ R2 ═ R.
Assuming that the initial states cp1 and cp2 are both low, the reference voltages generated by the positive and negative reference voltage generation circuits are adjusted by changing the potentials of cp1_ in and cp2_ in applied in the electrical trimming circuit.
When both cp1 and cp2 are low, MP0 is off, MN0 is on, and Vp ═ Vn | ═ Vbg.
When cp1_ in is asserted high, cp1 switches high, MP0 is on, MN0 remains on, and Vp ═ Vn | ═ 2 Vbg.
When cp2_ in is applied high, cp2 switches to high, MN0 is off, MP0 remains off, and Vp ═ Vn | ═ Vbg.
When cp1_ in and cp2_ in apply high, cp1 and cp2 switch high, MP0 turns on, MN0 turns off, and Vp ═ Vn | ═ 3 Vbg.
The low-precision analog-to-digital converter receives an output signal Vx of the capacitor voltage conversion circuit and takes the output signal Vx as an input signal ADCin of the low-precision analog-to-digital converter; vp and Vn are received from the output of the electrical trim reference voltage circuit. ADCin is processed at Vp and Vn to output signal ADCout.
The electric trimming reference voltage analog-to-digital conversion device is applied to an MEMS closed-loop digital accelerometer system, and the positive and negative reference voltages of the analog-to-digital converter are adjusted through cp1_ in and cp2_ in the electric trimming reference voltage analog-to-digital conversion device. The correction and curing of the internal circuit after the ASIC chip is packaged can be achieved.
The MEMS closed-loop digital accelerometer system comprises an MEMS sensitive chip and a closed-loop servo circuit, wherein the common acceleration sensitive chip is equivalent to a second-order system model and can be embedded into an accelerometer open-loop or closed-loop system.
Fig. 3 is a schematic structural diagram of a MEMS closed-loop digital accelerometer system according to an embodiment of the invention. As shown in FIG. 3, the system comprises a MEMS sensitive chip, a readout circuit ASIC and FPGA digital circuits. Wherein, FPGA digital circuit includes: a loop filter and a clock generation circuit. Readout circuitry ASIC comprising: a capacitance-to-voltage conversion circuit and an electrically trimmed reference voltage analog-to-digital conversion device as shown in fig. 1. It should be noted that the analog-to-digital converter is a low-precision analog-to-digital converter.
In the readout circuit ASIC, the voltage range of the output voltage Vx of the capacitance-voltage conversion circuit is used to determine the reference voltage of the analog-to-digital conversion device.
The least Significant bit lsb (least Significant bit) of the analog-to-digital converter refers to the minimum input analog voltage that the analog-to-digital converter can recognize, and is determined by the number of conversion bits N and the reference voltage (Vp + | Vn |):
the signal-to-Noise ratio (snr) of the analog-to-digital converter refers to the ratio of the power of the effective component in the signal to the Noise power, and the unit is usually expressed in dB, and the expression can be simplified as follows:
SNR＝6.02N+1.76 (2)
because the output range of the capacitance voltage conversion circuit in the MEMS closed-loop digital accelerometer system is very small, the reference voltage of the analog-to-digital conversion device can be adjusted to a corresponding voltage range. As the reference voltage becomes smaller, the LSB becomes correspondingly smaller (equation 1); compared with the analog-digital converter before correction, the reduction of the LSB is equivalent to the increase of the conversion bit number N of the analog-digital converter, namely, the increase of the signal-to-noise ratio SNR (formula 2), and the performance of the high-precision analog-digital converter is realized.
The invention provides an electric fine tuning reference voltage analog-to-digital conversion device applied to an MEMS closed-loop digital accelerometer system. The reference voltage is corrected and solidified in an electric fine adjustment mode, and the measurement precision of the analog-digital converter is improved by reducing the reference voltage properly. Compared with the existing high-precision analog-to-digital converter obtained based on circuit design, the device in the embodiment of the invention formed by combining the low-precision analog-to-digital converter and the electric fine tuning reference voltage circuit not only reduces the design difficulty, but also reduces the influence of the quantization noise of the analog-to-digital converter on the system performance, and simultaneously meets the requirements of the system on the precision and the speed of the analog-to-digital converter.
The above-mentioned embodiments are intended to illustrate the objects, technical solutions and advantages of the present invention in further detail, so that it should be understood that the above-mentioned embodiments are only one of the embodiments of the present invention, and are not intended to limit the scope of the present invention, and any modifications, equivalent substitutions, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.
Claims (3)
1. An MEMS closed-loop digital accelerometer system is characterized in that the system comprises an MEMS sensitive chip, a readout circuit ASIC and an FPGA digital circuit; wherein the readout circuitry ASIC comprises: the capacitor voltage conversion circuit and the electric fine tuning reference voltage analog-to-digital conversion device;
the electric trimming reference voltage analog-to-digital conversion device comprises an analog-to-digital converter and an electric trimming reference voltage circuit for providing reference voltage for the analog-to-digital converter; the electrical trim reference voltage circuit includes: the circuit comprises a band gap reference source, an adjustable positive reference voltage generating circuit, a negative reference voltage generating circuit and an electric fine tuning circuit; wherein,
the band-gap reference source is used for generating a band-gap voltage;
the adjustable positive reference voltage generating circuit is used for receiving a first control voltage and a second control voltage, processing the band gap voltage according to the first control voltage and the second control voltage and generating a positive reference voltage;
the electrical trimming circuit includes: the power supply comprises a current source, a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a first PMOS tube, a second PMOS tube, a third PMOS tube, a fifth resistor, a sixth resistor, a first electric fuse and a second electric fuse; the source electrodes of the first PMOS tube, the second PMOS tube and the third PMOS tube are connected with working voltage; the grid electrodes of the first PMOS tube, the second PMOS tube and the third PMOS tube are connected with the drain electrode of the first PMOS tube; the drain electrode of the first PMOS tube is connected with the drain electrode of the second NMOS tube; the drain electrode of the second PMOS tube is connected with the drain electrode of the third NMOS tube; the drain electrode of the third PMOS tube is connected with the drain electrode of the fourth NMOS tube; the drain electrode of the first NMOS tube, and the grid electrodes of the first NMOS tube, the second NMOS tube, the third NMOS tube and the fourth NMOS tube are connected with a current source; the source electrodes of the first NMOS tube and the second NMOS tube are grounded; the source electrode of the third NMOS tube is sequentially connected with the fifth resistor and the first electric fuse and then grounded; the source electrode of the fourth NMOS tube is sequentially connected with the sixth resistor and the second electric fuse and then grounded; determining that the first electrical fuse is connected or fused according to a first input voltage applied by a fifth resistor and a first electrical fuse connection point to obtain the first control voltage of the connection point of the second PMOS tube and the third NMOS tube; and/or determining that the second electrical fuse is connected or fused according to a second input voltage applied by a sixth resistor and a second electrical fuse connection point to obtain a second control voltage of a third PMOS tube and a fourth NMOS tube connection point;
the negative reference voltage generating circuit comprises a second amplifier, a third resistor and a fourth resistor; one end of the third resistor is connected to the positive reference voltage; the other end of the third resistor is connected with the negative input end of the second amplifier; the positive input end of the second amplifier is grounded; the output end of the second amplifier is connected with one end of a fourth resistor, and the other end of the fourth resistor is connected with the negative input end of the second amplifier; the voltage at the output end of the second amplifier is used as a negative reference voltage;
testing the packaged system; determining the reference voltage of the electric trimming reference voltage analog-to-digital conversion device according to the output of the capacitor voltage conversion circuit in the test; and correcting and solidifying the reference voltage in an electric fine adjustment mode.
2. The system of claim 1, wherein the adjustable positive reference voltage generating circuit comprises a first switch, a second switch, a first amplifier, a resistance to ground, a first resistance, and a second resistance; wherein,
the positive input end of the first amplifier is connected with the band gap voltage; the negative input end of the first amplifier is grounded after sequentially passing through the first switch and the grounding resistor; the output end of the first amplifier is connected with the negative input end of the first amplifier after sequentially passing through the second resistor and the first resistor; the voltage of the output end of the first amplifier is used as a positive reference voltage; the second resistor is connected with the second switch in parallel;
the first switch adjusts the on-off according to the first control voltage; the second switch adjusts the on-off according to the second control voltage.
3. The system of claim 2, wherein the positive reference voltage and the negative reference voltage are adjusted by adjusting potentials of the first control voltage and the second control voltage to control on and off of the first switch and the second switch.
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| CN105912059B (en) * | 2016-05-23 | 2017-08-15 | 深圳创维－Rgb电子有限公司 | The reference voltage of integrated circuit trims circuit and system |
| KR102324194B1 (en) * | 2017-05-22 | 2021-11-10 | 삼성전자주식회사 | Voltage trimming circuit including anti-fuses, operating method thereof, and integrated circuit having the voltage trimming circuit |
| CN110504001B (en) * | 2018-05-18 | 2021-07-30 | 华润微集成电路(无锡)有限公司 | Successive approximation principle-based trimming code generation circuit, trimming system and method |
| CN208607546U (en) * | 2018-08-24 | 2019-03-15 | 上海东软载波微电子有限公司 | Fuse calibrates circuit |
| CN209765366U (en) * | 2019-05-27 | 2019-12-10 | 天津鹏翔华夏科技有限公司 | Band gap reference circuit with adjusting circuit |
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2020
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