CN111786670A - Charge pump circuit for relieving negative bias temperature instability - Google Patents
Charge pump circuit for relieving negative bias temperature instability Download PDFInfo
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
- H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/14—Arrangements for reducing ripples from DC input or output
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of DC power input into DC power output
- H02M3/02—Conversion of DC power input into DC power output without intermediate conversion into AC
- H02M3/04—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters
- H02M3/10—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M3/145—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M3/155—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/156—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/087—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop
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Abstract
The invention discloses a charge pump circuit for relieving negative bias temperature instability, which comprises an N-type MOS tube M1, an N-type MOS tube M2, an N-type MOS tube M3, an N-type MOS tube M6, an N-type MOS tube M7, an N-type MOS tube M8, an N-type MOS tube M11, an N-type MOS tube M12, an N-type MOS tube M13, a P-type MOS tube M4, a P-type MOS tube M5, a P-type MOS tube M9, a P-type MOS tube M10 and an operational amplifier, wherein a current source Iref is a reference current source, the two N-type MOS tubes M2 and M3 are connected to form a cascode structure, the two N-type MOS tubes M7 and M8 are connected to form a cascode structure, the two N-type MOS tubes M12 and M13 are connected to form a cascode structure, and the grid electrode of the P-type MOS tube M9 is connected to an input end UP. Through the mode, the NBTI effect caused by the MOS transistor M9 can be solved, even if the MOS transistor M9 is used for a long time, the accurate matching of the charging current and the discharging current of the charge pump can be still ensured, and the reliability of the circuit is improved.
Description
Technical Field
The present invention relates to the field of integrated circuits, and more particularly, to a charge pump circuit for mitigating negative bias temperature instability.
Background
As transistor fabrication processes enter the nanometer scale, aging becomes a major cause of reliability concerns for integrated circuits. When the process size of the transistor is less than 65nm, when the PMOS transistor is under negative bias (i.e., Vgs ═ Vdd), under the action of an electric field force, Si — H bonds on the surface of the transistor are broken, a large number of positive ions are generated, the threshold voltage is raised, and a Negative Bias Temperature Instability (NBTI) effect occurs. Over a long period of time, this increase in threshold voltage can lead to degradation of the electrical performance of the PMOS device. NBTI is mainly caused by changes in trapped charges and oxide layer charges at the silicon/oxide layer interface. The variation of the interface trap charges is proportional to the electric field intensity, which increases with the increase of the process node and the decrease of the thickness of the oxide layer. It is therefore believed that the NBTI effect increases significantly with the increase in technology nodes. This NBTI effect, which leads to device performance degradation, is also more pronounced with increasing temperature.
The sensitivity of the rf receiver module is affected by the noise and spurs of the charge pump pll. The good stray performance enables the phase-locked loop to meet the sensitivity requirement of the receiver, and meanwhile, more redundancy designs can be provided for other modules. The charge pump based on CMOS has the characteristics of low power consumption, low jitter, high speed and the like, so that the charge pump is widely applied to a clock recovery circuit and a frequency synthesis circuit. However, the charge pump inevitably causes problems of charge sharing, current mismatch, etc., which may cause the output frequency of the voltage controlled oscillator to be unstable.
A conventional charge pump circuit structure is shown in fig. 1. Usually, an operational amplifier is added to the charge pump to ensure accurate mirroring of the mirrored current source. The current source Iref represents a reference current source, and is connected into a cascode structure through an MOS transistor M2 and an MOS transistor M3, so that the output impedance of the mirror current source is increased, and the current mismatch rate of the charge pump is reduced. By adding the operational amplifier, the voltage of the X point can be always equal to Vout, thereby ensuring the accurate image of the image current source. When the MOS transistor width-to-length ratio M2, M7, M3, M8, M13, M1, M6, M11, M4, M9, and M5, M10 are both on, the current source and the current sink are both on (UP is "0" and DN is "1"), and Iref I1 is I2, an accurate mirror of the charge pump current is ensured. However, since the MOS transistor M9 is always biased negatively (i.e., Vgs — Vdd), a negative bias temperature instability (hereinafter NBTI) effect occurs, the threshold voltage increases, the electrical performance decreases, and the effect is particularly significant at high temperatures. The electrical performance of the M9 and the M4 can be different under long-term use, and the mismatch of the charge pump current can be caused. The current mismatch will result in a higher ripple amplitude and degrade the reference spurs of the pll.
The problem of circuit aging is always one of the hot spots of domestic and foreign research. Wherein Karl and other dynamic anti-aging technologies provide a time relationship circuit aging model based on load bias and a dynamic reliability Management scheme (DRM), so that the service life can be prolonged, and the circuit performance can be improved by 20-35%; raychowdhury and the like provide a self-adaptive word line charge pump technology in an ISSCC conference, and improve the resistance of a register file to circuit aging and PVT (process Voltage temperature) disturbance; keane et al propose to use the array sensor way to monitor the aging condition of the system circuit, but do not propose the corresponding anti-aging scheme; kumar et al propose to use Adaptive Body Bias (ABB) and Adaptive Supply Voltage (ASV) to resist circuit parameter deviations, set constraints during circuit synthesis, and keep the system in an optimal operating state during the life cycle. However, these anti-aging techniques are mainly applied to digital circuits or memory circuits, and no mention is made of anti-aging treatment of analog circuits.
Fig. 1 shows that, in the conventional charge pump structure, after a long NBTI effect, the threshold voltage of the MOS transistor M9 increases, which results in an increase in the on-resistance of the MOS transistor M9, and thus a current mismatch occurs, that is, the current I2 flowing through the MOS transistor M9 is smaller than the current I1 flowing through the MOS transistor M4, and the discharging current I4 is smaller than the charging current I1 because the current I2 is equal to I3 and I4. Charge pump mismatch produces a non-zero net output current that increases or decreases the output voltage of the following Low Pass Filter (LPF) at each phase comparison instant. The average value of the LPF output voltage should be a constant when the loop is locked. Therefore, the phase-locked loop introduces a steady-state phase error between the input reference signal and the output signal to compensate for the effect of the current mismatch, so that the average net output current of the charge pump is kept at 0 during one period, thereby causing the voltage of the voltage-controlled oscillator (VC0) to have a periodic ripple.
Disclosure of Invention
The invention aims to provide a charge pump circuit for relieving negative bias temperature instability, which can solve the NBTI effect caused by an MOS transistor M9, can still ensure the accurate matching of the charging current and the discharging current of the charge pump even after long-time use, and improves the reliability of the circuit.
In order to solve the technical problems, the invention adopts a technical scheme that: the charge pump circuit comprises an N-type MOS tube M1, an N-type MOS tube M2, an N-type MOS tube M3, an N-type MOS tube M6, an N-type MOS tube M7, an N-type MOS tube M8, an N-type MOS tube M11, an N-type MOS tube M12, an N-type MOS tube M13, a P-type MOS tube M4, a P-type MOS tube M5, a P-type MOS tube M9, a P-type MOS tube M10 and an operational amplifier, wherein a current source Iref is a reference current source, the two N-type MOS tubes M2 and M3 are connected into a cascode structure, the two N-type MOS tubes M7 and M8 are connected into a cascode structure, the two N-type MOS tubes M12 and M13 are connected into a cascode structure, and the grid electrode of the P-type MOS tube M9 is connected to an input end.
Further, the MOS transistor width-to-length ratio N-type MOS transistor M2 is N-type MOS transistor M7 is N-type MOS transistor M12, the N-type MOS transistor M3 is N-type MOS transistor M8 is N-type MOS transistor M13, the N-type MOS transistor M1 is N-type MOS transistor M6 is N-type MOS transistor M11, the P-type MOS transistor M4 is P-type MOS transistor M9, and the P-type MOS transistor M5 is P-type MOS transistor M10.
Further, during the normal operation, the phase-locked loop is in a locked state, the output Vout of the charge pump is stabilized at a certain voltage value, and two input signals UP and DOWN of the charge pump are two signals with the same pulse width.
Further, the voltage of Vout is adjusted by the pulse widths of the UP signal and the DOWN signal before the phase locked loop is in a stable locked state.
Further, the pulse width of the UP signal is greater than that of the DOWN signal, at this time, the P-type MOS transistor M4 is turned on, the N-type MOS transistor M6 is turned off, the I1 current of Iref charges the output Vout through the P-type MOS transistor M4 and the P-type MOS transistor M5, at this time, Vout rises linearly, and the rising of Vout decreases the pulse width of the UP signal through system feedback and increases the pulse width of the DOWN signal at the same time until the pulse widths of the UP and the DOWN are equal, the output Vout of the charge pump is not charged continuously, so that the voltage value is stabilized at a certain voltage value, and the phase-locked loop enters a locked state.
Further, the pulse width of the UP signal is smaller than that of the DOWN signal, at this time, the P-type MOS transistor M4 is turned off, the N-type MOS transistor M6 is turned on, the I2 current with the magnitude of Iref discharges the output Vout through the N-type MOS transistor M6, the N-type MOS transistor M7 and the N-type MOS transistor M8, at this time, Vout linearly drops, and the drop of Vout increases the pulse width of the UP signal through system feedback while decreasing the pulse width of the DOWN signal until the pulse widths of UP and DOWN are equal, the output Vout of the charge pump is not continuously discharged, so that the voltage value is stabilized at a certain voltage value, and the phase-locked loop enters a locked state.
The invention has the beneficial effects that: the charge pump circuit for relieving the negative bias temperature instability can solve the NBTI effect caused by the MOS transistor M9, can still ensure the accurate matching of the charging current and the discharging current of the charge pump even after long-time use, and improves the reliability of the circuit.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments described in the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a prior art circuit diagram;
fig. 2 is a circuit diagram of a charge pump circuit for mitigating negative bias temperature instability in accordance with the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention are described in detail below with reference to the accompanying drawings. Examples of these preferred embodiments are illustrated in the accompanying drawings. The embodiments of the invention shown in the drawings and described in accordance with the drawings are exemplary only, and the invention is not limited to these embodiments.
It should be noted that, in order to avoid obscuring the present invention with unnecessary details, only the structures and/or processing steps closely related to the scheme according to the present invention are shown in the drawings, and other details not so relevant to the present invention are omitted.
Also, in the description of the present invention, the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. indicate orientations or positional relationships based on those shown in the drawings, only for convenience of description and simplification of description, but do not indicate or imply that the referred device or element must have a specific orientation, be constructed in a specific orientation, and be operated, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
Referring to fig. 2, an embodiment of the invention includes: a charge pump circuit for relieving negative bias temperature instability comprises an N-type MOS tube M1, an N-type MOS tube M2, an N-type MOS tube M3, an N-type MOS tube M6, an N-type MOS tube M7, an N-type MOS tube M8, an N-type MOS tube M11, an N-type MOS tube M12, an N-type MOS tube M13, a P-type MOS tube M4, a P-type MOS tube M5, a P-type MOS tube M9, a P-type MOS tube M10 and an operational amplifier, wherein a current source Iref is a reference current source, the two N-type MOS tubes M2 and M3 are connected into a cascode structure, the two N-type MOS tubes M7 and M8 are connected into a cascode structure, the two N-type MOS tubes M12 and M13 are connected into a cascode structure, and the grid electrode of the P-type MOS tube M9 is connected to an input end.
Further, the MOS transistor width-to-length ratio N-type MOS transistor M2 is N-type MOS transistor M7 is N-type MOS transistor M12, the N-type MOS transistor M3 is N-type MOS transistor M8 is N-type MOS transistor M13, the N-type MOS transistor M1 is N-type MOS transistor M6 is N-type MOS transistor M11, the P-type MOS transistor M4 is P-type MOS transistor M9, and the P-type MOS transistor M5 is P-type MOS transistor M10.
Further, during the normal operation, the phase-locked loop is in a locked state, the output Vout of the charge pump is stabilized at a certain voltage value, and two input signals UP and DOWN of the charge pump are two signals with the same pulse width.
Further, the voltage of Vout is adjusted by the pulse widths of the UP signal and the DOWN signal before the phase locked loop is in a stable locked state.
Further, the pulse width of the UP signal is greater than that of the DOWN signal, at this time, the P-type MOS transistor M4 is turned on, the N-type MOS transistor M6 is turned off, the I1 current of Iref charges the output Vout through the P-type MOS transistor M4 and the P-type MOS transistor M5, at this time, Vout rises linearly, and the rising of Vout decreases the pulse width of the UP signal through system feedback and increases the pulse width of the DOWN signal at the same time until the pulse widths of the UP and the DOWN are equal, the output Vout of the charge pump is not charged continuously, so that the voltage value is stabilized at a certain voltage value, and the phase-locked loop enters a locked state.
Further, the pulse width of the UP signal is smaller than that of the DOWN signal, at this time, the P-type MOS transistor M4 is turned off, the N-type MOS transistor M6 is turned on, the I2 current with the magnitude of Iref discharges the output Vout through the N-type MOS transistor M6, the N-type MOS transistor M7 and the N-type MOS transistor M8, at this time, Vout linearly drops, the drop of Vout increases the pulse width of the UP signal through system feedback while decreasing the pulse width of the DOWN signal until the pulse widths of UP and DOWN are equal, the output Vout of the charge pump is not continuously discharged, so that the voltage value is stabilized at a certain voltage value, and the phase-locked loop enters a locked state
The charge pump for relieving the negative bias temperature instability has the function of converting an UP signal and a DOWN signal output by a phase frequency detector into current signals, and generating a continuously changing voltage signal through a low-pass filter so as to control the oscillation frequency of a voltage-controlled oscillator. In designing a charge pump circuit, in order to reduce the influence of these adverse factors on the circuit as much as possible, it is necessary to increase the output impedance as much as possible while reducing the voltage range of the linear resistance region as much as possible.
Usually, an operational amplifier is added to the charge pump to ensure accurate mirroring of the mirrored current source. As shown in fig. 2, the current source Iref represents a reference current source, and is connected to a cascode structure through two N-type MOS transistors M2 and M3, so as to increase the output impedance of the current source. For the same purpose, the two N-type MOS transistors M7, M8 are connected in a cascode structure, and the two N-type MOS transistors M12, M13 are connected in a cascode structure. The several same cascode structures improve the matching degree and stability of the currents Iref and I3 and I4, thereby reducing noise or jitter introduced by the current sources and reducing the current mismatch rate of the charge pump. By adding the operational amplifier, the voltage of the X point can be always equal to Vout, thereby ensuring the accurate image of the image current source. When a current source and a current sink are simultaneously conducted (UP is '0', DN is '1'), and an Iref I2 are ensured under the conditions that an N-type MOS transistor M2, an N-type MOS transistor M7, an N-type MOS transistor M12, an N-type MOS transistor M3, an N-type MOS transistor M8N, an N-type MOS transistor M13, an N-type MOS transistor M1, an N-type MOS transistor M6, an N-type MOS transistor M11, a P-type MOS transistor M4, an M9 and a P-type MOS transistor M5, a P-type MOS transistor M10.
As shown in fig. 2, the gate of the P-type MOS transistor M9 is connected to the input UP. During normal operation, the phase-locked loop is in a locked state, the output Vout of the charge pump is stabilized at a certain voltage value, and two input signals UP and DOWN of the charge pump are two signals with the same pulse width. The voltage of Vout is regulated by the pulse widths of the UP signal and the DOWN signal before the phase locked loop is in a stable locked state. If the pulse width of the UP signal is larger than that of the DOWN signal, the P-type MOS transistor M4 is conducted at the moment, the N-type MOS transistor M6 is closed, I1 current with the size of Iref charges the output Vout through the N-type MOS transistor M4 and the N-type MOS transistor M5, the Vout rises linearly at the moment, the rising of the Vout can reduce the pulse width of the UP signal and increase the pulse width of the DOWN signal through system feedback, and the output Vout of the charge pump cannot be continuously charged until the pulse widths of the UP and the DOWN are equal, so that the voltage value is stabilized at a certain voltage value, and the phase-locked loop enters a locked state. Similarly, if the pulse width of the UP signal is smaller than that of the DOWN signal, the P-type MOS transistor M4 is turned off, the N-type MOS transistor M6 is turned on, the I2 current with the magnitude of Iref discharges the output Vout through the N-type MOS transistor M6, the N-type MOS transistor M7 and the N-type MOS transistor M8, and at this time Vout linearly drops, and the drop of Vout increases the pulse width of the UP signal through system feedback and simultaneously decreases the pulse width of the DOWN signal until the pulse widths of UP and DOWN are equal, and the output Vout of the charge pump is not continuously discharged, so that the phase-locked loop is stabilized at a certain voltage value and enters a locked state.
Meanwhile, since the gate of the P-type MOS transistor M9 is connected to the input UP, the P-type MOS transistor is prevented from being constantly biased negatively (i.e., Vgs ═ Vdd). In the case described in this patent, the gate voltage of the PMOS transistor M9 and the gate voltage of the P-type MOS transistor M4 are kept synchronized. During the stable operation of the charge pump, UP is a signal with a very narrow pulse, and the gates of the P-type MOS transistor M9 and the P-type MOS transistor M4 are at the level of 0 only during the pulse width, and it can be considered that during the stable operation of the charge pump, the condition that the P-type MOS transistor M9 and the P-type MOS transistor M4 are biased negatively (i.e., Vgs — Vdd) occurs only during the UP pulse, so that the time for the PMOS transistor M9 to generate the Negative Bias Temperature Instability (NBTI) effect is greatly shortened, and the reliability of the circuit is improved. Even under the long-time use, the situation that the electrical performance of the P-type MOS tube M9 and the P-type MOS tube M4 is different is avoided, so that the charging and discharging current of the charge pump is a constant value and is more accurately matched with the charge pump current.
The current stability and matching degree of the charge pump provided by the invention are greatly optimized, and the output ripple amplitude of the traditional charge pump is greatly improved. Thereby further optimizing the phase noise of the charge pump and also optimizing the reference spurs of the phase locked loop.
The charge pump circuit for relieving the negative bias temperature instability can solve the NBTI effect caused by the P-type MOS transistor M9, can still ensure the accurate matching of the charging current and the discharging current of the charge pump even after long-time use, and improves the reliability of the circuit.
Furthermore, it should be noted that in the present specification, "include" or any other variation thereof is intended to cover a non-exclusive inclusion, so that a process, a method, an article or an apparatus including a series of elements includes not only those elements but also other elements not explicitly listed, or further includes elements inherent to such process, method, article or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
It should be understood that although the present description refers to embodiments, not every embodiment contains only a single technical solution, and such description is for clarity only, and those skilled in the art should take the description as a whole, and the technical solutions in the embodiments may be appropriately combined to form other embodiments understood by those skilled in the art.
Claims (6)
1. A charge pump circuit for relieving negative bias temperature instability is characterized by comprising an N-type MOS tube M1, an N-type MOS tube M2, an N-type MOS tube M3, an N-type MOS tube M6, an N-type MOS tube M7, an N-type MOS tube M8, an N-type MOS tube M11, an N-type MOS tube M12, an N-type MOS tube M13, a P-type MOS tube M4, a P-type MOS tube M5, a P-type MOS tube M9, a P-type MOS tube M10 and an operational amplifier, wherein a current source Iref is a reference current source, the two N-type MOS tubes M2 and M3 are connected to form a cascode structure, the two N-type MOS tubes M7 and M8 are connected to form a cascode structure, the two N-type MOS tubes M12 and M13 are connected to form a cascode structure, and the grid electrode of the P-type MOS tube M9 is connected to an input end UP.
2. The charge pump circuit of claim 1, wherein: the MOS transistor width-to-length ratio N-type MOS transistor M2 is N-type MOS transistor M7 is N-type MOS transistor M12, N-type MOS transistor M3 is N-type MOS transistor M8 is N-type MOS transistor M13, N-type MOS transistor M1 is N-type MOS transistor M6 is N-type MOS transistor M11, P-type MOS transistor M4 is P-type MOS transistor M9, and P-type MOS transistor M5 is P-type MOS transistor M10.
3. The charge pump circuit of claim 1, wherein: during normal operation, the phase-locked loop is in a locked state, the output Vout of the charge pump is stabilized at a certain voltage value, and two input signals UP and DOWN of the charge pump are two signals with the same pulse width.
4. The charge pump circuit of claim 1, wherein: before the phase-locked loop is in a stable locking state, the voltage of Vout is regulated through the pulse width of the UP signal and the DOWN signal.
5. The charge pump circuit of claim 1, wherein: the pulse width of the UP signal is larger than that of the DOWN signal, at the moment, the P-type MOS transistor M4 is conducted, the N-type MOS transistor M6 is closed, I1 current with the size of Iref charges the output Vout through the P-type MOS transistor M4 and the P-type MOS transistor M5, at the moment, the Vout rises linearly, the rising of the Vout can reduce the pulse width of the UP signal through system feedback and increase the pulse width of the DOWN signal at the same time, until the pulse widths of the UP and the DOWN are equal, the output Vout of the charge pump cannot be continuously charged, and therefore the voltage value is stabilized at a certain voltage value, and the phase-locked.
6. The charge pump circuit of claim 1, wherein: the pulse width of the UP signal is smaller than that of the DOWN signal, at the moment, the P-type MOS transistor M4 is cut off, the N-type MOS transistor M6 is conducted, I2 current with the size of Iref discharges the output Vout through the N-type MOS transistor M6, the N-type MOS transistor M7 and the N-type MOS transistor M8, at the moment, the Vout linearly drops, the dropping of the Vout increases the pulse width of the UP signal through system feedback and simultaneously reduces the pulse width of the DOWN signal until the pulse widths of the UP signal and the DOWN signal are equal, the output Vout of the charge pump cannot be continuously discharged, so that the voltage value is stabilized at a certain voltage value, and the phase-locked loop.
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| CN202010470198.5A CN111786670A (en) | 2020-05-28 | 2020-05-28 | Charge pump circuit for relieving negative bias temperature instability |
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| CN202010470198.5A CN111786670A (en) | 2020-05-28 | 2020-05-28 | Charge pump circuit for relieving negative bias temperature instability |
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| CN111786670A true CN111786670A (en) | 2020-10-16 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010470198.5A Withdrawn CN111786670A (en) | 2020-05-28 | 2020-05-28 | Charge pump circuit for relieving negative bias temperature instability |
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| CN (1) | CN111786670A (en) |
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- 2020-05-28 CN CN202010470198.5A patent/CN111786670A/en not_active Withdrawn
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