CN111725287A - Display panel, display device, and manufacturing method of display panel - Google Patents

Abstract

The invention discloses a display panel, a display device and a manufacturing method of the display panel. The display panel is provided with a first display area and a second display area, the light transmittance of the first display area is greater than that of the second display area, and the display panel comprises a driving array layer, a first insulating layer, a light-emitting element array layer, a first auxiliary lead and a second auxiliary lead; the driving array layer comprises a first pixel circuit and a second pixel circuit which are positioned in the second display area; the light emitting element array layer includes a first light emitting unit and a second light emitting unit in the first display region; at least part of the first auxiliary wire is positioned on the substrate-facing side of the first insulating layer, and the first electrode of each first light-emitting element in one first light-emitting unit is electrically connected with the first transistor of the first pixel circuit; at least part of the second auxiliary wire is positioned on the side of the first insulating layer, which faces away from the substrate, and the second electrode of each second light emitting element in one second light emitting unit is electrically connected with the second transistor of the second pixel circuit.

Description

Display panel, display device, and manufacturing method of display panel

technical field

The present invention relates to the field of display panels, in particular to a display panel, a display device and a manufacturing method of the display panel.

Background technique

Organic Light Emitting Diode (OLED) display panel is an active light-emitting display panel, which has become the mainstream flat panel display technology due to its advantages of simple preparation process, low cost, high contrast ratio, wide viewing angle, and low power consumption. .

The manufacturing process of the display panel is roughly a process of sequentially forming various film layers on the substrate. In the process of making each film layer, patterning processing needs to be performed through a mask. Therefore, the more film layers of the display panel, the more difficult the manufacturing process of the display panel will be.

SUMMARY OF THE INVENTION

The present invention provides a display panel, a display device and a manufacturing method of the display panel, which can reasonably arrange the display panel to reduce the number of film layers of the display panel, thereby reducing the difficulty of the manufacturing process of the display panel.

In a first aspect, an embodiment of the present invention provides a display panel having a first display area and a second display area adjacent to each other, the light transmittance of the first display area is greater than the light transmittance of the second display area, and the display panel includes a substrate, a driving array layer, a first insulating layer, a light-emitting element array layer, a first auxiliary wire and a second auxiliary wire;

Wherein, the drive array layer is located on the substrate, the drive array layer includes a plurality of pixel drive circuits located in the second display area, the pixel drive circuit includes a first pixel circuit and a second pixel circuit, and the first pixel drive circuit includes a first transistor, The second pixel circuit includes a second transistor; the first insulating layer is located on the side of the driving array layer away from the substrate; the light-emitting element array layer is located at the side of the first insulating layer away from the substrate, and the light-emitting element array layer includes a plurality of A light-emitting unit and a plurality of second light-emitting units, the first light-emitting units are connected with the first pixel circuits in a one-to-one correspondence, and the second light-emitting units are connected with the second pixel circuits in a one-to-one correspondence; each first light-emitting unit includes at least one first light-emitting unit. Light-emitting elements, each first light-emitting element includes a first electrode, each second light-emitting unit includes at least one second light-emitting element, and each second light-emitting element includes a second electrode; at least part of the first auxiliary wire is located in the first insulating The layer faces the substrate side, and the first auxiliary wires electrically connect each first electrode in a first light-emitting unit with the first transistor of the first pixel circuit; at least part of the second auxiliary wires are located on the side of the first insulating layer away from the substrate and the second auxiliary wires electrically connect each second electrode in a second light-emitting unit with the second transistor of the second pixel circuit.

In a second aspect, an embodiment of the present invention provides a display device, including the display panel described in the first aspect.

In a third aspect, an embodiment of the present invention provides a method for fabricating a display panel for fabricating the display panel according to the first aspect, the fabrication method comprising: forming a driving array layer on a substrate; and forming a driving array layer on the driving array layer Covering the first wire layer; patterning the first wire layer to form a plurality of first auxiliary wires; forming a first insulating layer covering the first auxiliary wires; forming a second auxiliary wire and a light-emitting element array layer on the first insulating layer.

According to the display panel, the display device, and the manufacturing method of the display panel according to the embodiments of the present invention, at least one first light-emitting element in the first light-emitting unit located in the first display area can be connected with the light-emitting element located in the second display area through the first auxiliary wire. The first transistor in the first pixel circuit is connected, and at least one second light-emitting element in the second light-emitting unit in the first display area is connected with the second light-emitting element in the second pixel circuit in the second display area through the second auxiliary wire. Two transistors are connected to complete the wiring connection between the plurality of light-emitting elements in the first display area and the plurality of transistors in the second display area by using double auxiliary wires in two film layers. The auxiliary wires are reasonably arranged in the film layer, and then the display panel is arranged reasonably, so as to reduce the number of film layers of the display panel and reduce the difficulty of the manufacturing process of the display panel.

Description of drawings

Other features, objects and advantages of the present invention will become more apparent by reading the following detailed description of non-limiting embodiments with reference to the accompanying drawings, wherein the same or similar reference numerals denote the same or similar features, and Figures are not drawn to actual scale.

1 is a schematic top view of a display panel provided according to an embodiment of the present invention;

2 is a schematic top view of a display panel provided according to another embodiment of the present invention;

FIG. 3 is a schematic cross-sectional view along the A-A direction in FIG. 1 according to an exemplary embodiment;

FIG. 4 is a schematic cross-sectional view along the A-A direction in FIG. 1 according to another exemplary embodiment;

FIG. 5 is a schematic cross-sectional view along the A-A direction in FIG. 1 according to yet another exemplary embodiment;

FIG. 6 is a schematic cross-sectional view along the A-A direction in FIG. 1 according to yet another exemplary embodiment;

FIG. 7 is a schematic cross-sectional view along the A-A direction in FIG. 1 according to yet another exemplary embodiment;

FIG. 8 is a schematic cross-sectional view along the A-A direction in FIG. 1 according to yet another exemplary embodiment;

FIG. 9 is a schematic cross-sectional view along the A-A direction in FIG. 1 according to yet another exemplary embodiment;

FIG. 10 is a schematic cross-sectional view along the A-A direction in FIG. 1 according to yet another exemplary embodiment;

11 is a schematic cross-sectional view of a first electrode provided according to an embodiment of the present invention;

12 is a schematic top view of a display panel provided according to still another embodiment of the present invention;

13 is a schematic top view of a display panel provided according to still another embodiment of the present invention;

FIG. 14 is a schematic cross-sectional view of the direction B-B in FIG. 12 according to an exemplary embodiment;

15 is a schematic flowchart of a method for fabricating a display panel according to an embodiment of the present invention;

16 is a schematic flowchart of a method for fabricating a display panel according to another embodiment of the present invention;

17 is a schematic flowchart of a method for fabricating a display panel according to another embodiment of the present invention;

18 is a schematic flowchart of a method for fabricating a display panel according to still another embodiment of the present invention;

FIG. 19 is a schematic diagram of a process flow of a display panel according to an embodiment of the present invention.

Detailed ways

The features and exemplary embodiments of various aspects of the present invention will be described in detail below. In order to make the objectives, technical solutions and advantages of the present invention more clear, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only configured to explain the present invention, and are not configured to limit the present invention. It will be apparent to those skilled in the art that the present invention may be practiced without some of these specific details. The following description of the embodiments is only intended to provide a better understanding of the present invention by illustrating examples of the invention.

It should be noted that, in this document, relational terms such as first and second are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any relationship between these entities or operations. any such actual relationship or sequence exists.

It will be understood that, in describing the structure of a component, when a layer or region is referred to as being "on" or "over" another layer or region, it can be directly on the other layer or region, or Other layers or regions are also included between it and another layer, another region. And, if the part is turned over, that layer, one area, will be "below" or "beneath" another layer, another area.

An embodiment of the present invention provides a display panel, and the display panel may be an OLED display panel. The display panel of the embodiment of the present invention may be presented in various forms, some examples of which will be described below.

FIG. 1 is a schematic top view of a display panel according to an embodiment of the present invention. FIG. 2 is a schematic top view of a display panel according to another embodiment of the present invention.

As shown in FIGS. 1 and 2 , the display panel 100 has a first display area AA1 and a second display area AA2 adjacent to each other, and a third display area AA3 surrounding the first display area AA1 and the second display area AA2. The second display area AA2 at least partially surrounds the first display area AA1. The lower part of the first display area AA1 is used for placing a camera. In order to ensure that the camera can image clearly, the light transmittance of the first display area AA1 is greater than that of the second display area AA2.

The display panel 100 may include a plurality of light emitting units PU arranged in an array in the first display area AA1 and the third display area AA3, each light emitting unit PU includes at least one light emitting element, and the light emitting element is the smallest unit for displaying images. The light emitting element may emit light of any one of red, green and blue, but is not limited to this in the embodiment of the present invention. For example, the light-emitting element may emit light of any one of cyan, magenta, yellow, white, and the like.

For example, the plurality of light-emitting elements may be arranged in an array of multiple rows and multiple columns in the first display area AA1 and the third display area AA3, respectively. In some embodiments, the first display area AA1 and the third display area AA3 may have the same density of light-emitting elements, that is, the arrangement of the light-emitting elements in the first display area AA1 and the third display area AA3 are completely the same. In other embodiments, the density of light emitting elements in the first display area AA1 may be lower than the density of light emitting elements in the third display area AA3, as shown in FIG. 1 and FIG. 2 , which is not limited herein.

The display panel 100 may further include a plurality of pixel driving circuits DC and a plurality of wires arranged in the second display area AA2 and the third display area AA3 in an array. Each pixel driving circuit DC can provide a signal for the light-emitting element, and the light-emitting element can be connected to the corresponding pixel driving circuit DC through a wire, so as to receive the signal of the pixel driving circuit DC, so that the light-emitting element can emit light according to the signal.

Specifically, each light emitting unit PU located in the first display area AA1 is connected to each pixel driving circuit DC located in the second display area AA2 in a one-to-one correspondence, and each light emitting unit PU located in the third display area AA3 is connected to each pixel driving circuit DC located in the second display area AA2. The pixel driving circuits DC in the three display areas AA3 are connected in a one-to-one correspondence.

In some embodiments of the present invention, as shown in FIG. 1 , each light-emitting unit PU in the first display area AA1 may be one-to-one with the pixel driving circuit DC in the side of the second display area AA2 close to the light-emitting unit PU, respectively. Correspondingly connected, and the projections of each row of the wires for connecting the pixel driving circuit DC of the same side of the second display area AA2 to the light emitting unit PU in the first display area AA1 can be overlapped.

In some embodiments of the present invention, as shown in FIG. 2 , each light-emitting unit PU in the first display area AA1 may be one-to-one with the pixel driving circuit DC in the side of the second display area AA2 close to the light-emitting unit PU, respectively. Correspondingly connected, and the projections of each row of the wires for connecting the pixel driving circuit DC of the same side of the second display area AA2 to the light emitting unit PU in the first display area AA1 can be staggered.

For the convenience of description, the following will take the display panel shown in FIG. 1 as an example for detailed description.

FIG. 3 is a schematic cross-sectional view along the line A-A in FIG. 1 , according to an exemplary embodiment. As shown in FIG. 3 , the display panel 100 may include a substrate 110 , a driving array layer 120 , a first insulating layer 130 , a light emitting element array layer, a first auxiliary wire and a second auxiliary wire.

The light-emitting element array layer, the first insulating layer 130 , the driving array layer 120 and the substrate 110 may be stacked and disposed along the thickness direction of the display panel 100 . The driving array layer 120 is located on the substrate 110. Specifically, a buffer layer 170 may be disposed on the substrate 110 first, and then the driving array layer 120 may be disposed on the buffer layer 170, so that the driving array layer 120 may be firmly disposed on the substrate 110 on the bottom. The first insulating layer 130 is located on the side of the driving array layer 120 away from the substrate 110 . Specifically, the first insulating layer 130 may be disposed on the driving array layer 120 through the fourth insulating layer 180 , that is, the fourth insulating layer 180 is located on the driving array layer 120 On the side facing away from the substrate 110 , the first insulating layer 130 is located on the side facing away from the substrate 110 of the fourth insulating layer 180 . The light-emitting element array layer is located on the side of the first insulating layer 130 away from the substrate 110. Specifically, the light-emitting element array layer may be directly disposed on the first insulating layer 130, or may be disposed on the first insulating layer 130 through other film layers. This does not limit.

In some embodiments, the substrate 110 may be a single layer substrate.

In other embodiments, the substrate 110 may also be a multi-layer substrate composed of an organic layer and an inorganic layer spaced apart. For example, the substrate 110 may include a first organic layer 111 , a first inorganic layer 112 , a second organic layer 113 and a second inorganic layer 114 that are stacked in a thickness direction thereof.

In some embodiments, the buffer layer 170 may be made of an inorganic material, for example, the buffer layer 170 may be made of silicon nitride.

The driving array layer 120 may include a plurality of pixel driving circuits DC located in the second display area AA2, the pixel driving circuit DC may include a first pixel circuit and a second pixel circuit, the first pixel driving circuit may include a first transistor T1, a second pixel driving circuit The pixel circuit may include a second transistor T2.

The first transistor T1 may include a first active layer N1, a first gate G1, a first source electrode S1 and a first drain electrode D1, and the second transistor T2 may include a second active layer N2, a second gate G2, the second source electrode S2 and the second drain electrode D2.

In some embodiments, the first transistor T1 and the second transistor T2 may be silicon transistors, respectively, and accordingly, the first active layer N1 and the second active layer N2 may be silicon active layers, respectively. For example, the silicon transistor may be a Low Temperature Poly-Silicon (LTPS) transistor.

In other embodiments, the first transistor T1 and the second transistor T2 may be oxide transistors, respectively, and correspondingly, the first active layer N1 and the second active layer N2 may be oxide active layers, respectively. For example, the oxide transistor may be an Indium Gallium Zinc Oxide (IGZO) transistor.

In other embodiments, the first transistor T1 and the second transistor T2 may be respectively other types of transistors, and accordingly, the first active layer N1 and the second active layer N2 may be respectively the other types of active layers, This is not limited.

In the embodiment of the present invention, the first gate G1 , the first source electrode S1 , the first drain electrode D1 , the second gate G2 , the second source electrode S2 and the second drain electrode D2 may be respectively made of metal materials.

Continuing to refer to FIG. 3 , the driving array layer 120 may include a semiconductor layer, a first interlayer insulating layer 121 , a first metal layer, a second interlayer insulating layer 122 , and a second metal layer stacked along its thickness direction.

Wherein, the semiconductor layer may be located on the substrate 110 , and specifically, the semiconductor layer may be located on the buffer layer 170 . The semiconductor layer may include a first active layer N1 of the first transistor T1 and a second active layer N2 of the second transistor T2. The first interlayer insulating layer 121 may be located on the side of the semiconductor layer away from the substrate 110 . The first metal layer may be located on the side of the first interlayer insulating layer 121 away from the substrate 110 . The first metal layer may include a first gate G1 of the first transistor T1 and a second gate G2 of the second transistor T2. The orthographic projection of the first gate G1 toward the substrate 110 is located on the first active layer N1, and the first interlayer insulating layer 121 insulates and separates the first gate G1 from the first active layer N1. The orthographic projection of the second gate G2 toward the direction of the substrate 110 is located on the second active layer N2, and the first interlayer insulating layer 121 insulates the second gate G2 from the second active layer N2. The second interlayer insulating layer 122 may be located on the side of the first metal layer away from the substrate 110 . The second metal layer may be located on the side of the second interlayer insulating layer 122 away from the substrate 110, and the second metal layer may include a first source electrode S1, a first drain electrode D1, a second source electrode S2 and a second drain electrode S2, wherein , the first source electrode S1 and the first drain electrode D1 can be respectively connected to the via holes of the first active layer N1, and the second source electrode S2 and the second drain electrode S2 can be respectively connected to the via holes of the second active layer N2.

In some embodiments, the first transistor T1 may further include a first capacitor, the second transistor T2 may further include a second capacitor, the first capacitor may include a first capacitor electrode C1 and a second capacitor electrode C2, and the second capacitor may include The third capacitive electrode C3 and the fourth capacitive electrode C4.

The first metal layer further includes a first capacitor electrode C1 and a third capacitor electrode C3, that is, the first capacitor electrode C1 and the third capacitor electrode C3 are arranged in the same layer as the first gate G1 and the second gate G2.

In these embodiments, optionally, the driving array layer 120 may further include a third interlayer insulating layer 123 and a third metal layer, the third interlayer insulating layer 123 is located on the side of the first metal layer away from the substrate 110, and the third The metal layer is located on the side of the third interlayer insulating layer 123 away from the substrate 110 , and the second interlayer insulating layer 122 is located on the side of the third metal layer away from the substrate 110 .

The third metal layer may include a second capacitive electrode C2 and a fourth capacitive electrode C4. The orthographic projection of the second capacitor electrode C2 toward the substrate 110 is located on the first capacitor electrode C1, and the first interlayer insulating layer 121 insulates the first capacitor electrode C1 and the second capacitor electrode C2 at intervals. The orthographic projection of the fourth capacitor electrode C4 toward the substrate 110 is located on the third capacitor electrode C3 , and the first interlayer insulating layer 121 insulates the third capacitor electrode C3 and the fourth capacitor electrode C4 at intervals.

In other embodiments, the driving array layer 120 may further include a fourth interlayer insulating layer 124 . The fourth interlayer insulating layer 124 may be located on the side of the third interlayer insulating layer 123 away from the substrate 110 , and the second metal layer may be located on the side of the fourth interlayer insulating layer 124 away from the substrate 110 .

In the embodiment of the present invention, the first interlayer insulating layer 121 , the second interlayer insulating layer 122 , the third interlayer insulating layer 123 and the fourth interlayer insulating layer 124 may be made of inorganic materials, for example, may be made of nitride Made of silicon and/or silicon oxide.

Continuing to refer to FIG. 3 , the light-emitting element array layer may include a plurality of light-emitting units PU located in the first display area AA1, and the plurality of light-emitting units PU include a plurality of first light-emitting units and a plurality of second light-emitting units, and the first light-emitting unit and the first light-emitting unit The pixel circuits are connected in a one-to-one correspondence, and the second light-emitting units are connected with the second pixel circuits in a one-to-one correspondence. Each first light emitting unit includes at least one first light emitting element PX1, each first light emitting element PX1 includes a first electrode RE1, each second light emitting element includes at least one second light emitting element PX2, and each second light emitting element PX2 A second electrode RE2 is included.

In some embodiments, the side of the light-emitting element array layer away from the substrate 110 may further be provided with a pixel definition layer 190 . The pixel definition layer 190 may be provided with a plurality of openings 191, and each opening 191 may be used for accommodating one light-emitting element.

In other embodiments, the pixel definition layer 190 may further be provided with a cathode 210 of the light emitting element, and the cathode 210 may cover the pixel definition layer 190 and each light emitting element. Among them, the transmittance of the cathode 210 is about 50%.

At least part of the first auxiliary wire is located on the side of the first insulating layer 130 facing the substrate 110 , and the first auxiliary wire can electrically connect each first electrode RE1 in a first light emitting unit with the first transistor T1 of the first pixel circuit. At least part of the second auxiliary wire is located on the side of the first insulating layer 130 away from the substrate 110 , and the second auxiliary wire electrically connects each second electrode RE2 in a second light emitting unit with the second transistor T2 of the second pixel circuit.

Optionally, the first auxiliary wire may be connected to the first drain electrode D1 of the corresponding first transistor T1, and the second auxiliary wire may be connected to the second drain electrode D2 of the corresponding second transistor T2.

In these embodiments, optionally, the first auxiliary wire and the second auxiliary wire may be transparent metal wires, respectively. For example, the transparent metal wires may be indium tin oxide (Indium Tin Oxides, ITO) wires or indium zinc oxide (Indium Zinc Oxide, IZO) wires. In addition, the camera located under the first display area AA1 may be a large aperture camera to improve the problem of low transmittance.

In some embodiments of the present invention, the first auxiliary wire may include a first wire body 151, and the first wire body 151 is located on the side of the first insulating layer 130 facing the substrate 110. In this case, the first electrode RE1 may directly connect with the first wire The main body 151 is connected to via holes, and the first wire main body 151 may be directly connected to the first drain electrode D1 via via holes or connected to the same layer.

In other embodiments of the present invention, the second auxiliary wire may include a second wire body 161, and the second wire body 161 is located on the side of the first insulating layer 130 away from the substrate 110. In this case, the second electrode RE2 may be directly connected to the second wire body 161. The lead body 161 is connected with a via hole, and the second lead body 161 can be directly connected with the second drain electrode D2 via a hole.

Continuing to refer to FIG. 3 , in some embodiments, the display panel 100 may further include a third insulating layer 220 , the third insulating layer 220 may be located between the second auxiliary wires and the light-emitting element array layer, and the third insulating layer 220 may serve as a flat surface chemical layer.

The first insulating layer 130 , the fourth insulating layer 180 and the third insulating layer 220 may be organic insulating layers, respectively.

To sum up, in the embodiment of the present invention, at least one first light-emitting element in the first light-emitting unit in the first display area and the first light-emitting element in the first pixel circuit in the second display area can be connected through the first auxiliary wire transistors are connected, and at least one second light-emitting element in the second light-emitting unit in the first display area is connected with the second transistor in the second pixel circuit in the second display area through a second auxiliary wire, so as to utilize the double auxiliary The wires complete the wiring connection between the multiple light-emitting elements in the first display area and the multiple transistors in the second display area in two film layers, so the auxiliary wires can be reasonably arranged in fewer film layers , and then reasonably layout the display panel, so as to reduce the number of film layers of the display panel and reduce the difficulty of the manufacturing process of the display panel.

FIG. 4 is a schematic cross-sectional view along the A-A direction in FIG. 1 according to another exemplary embodiment. As shown in FIG. 4 , the display panel 100 may include a substrate 110 , a driving array layer 120 , a first insulating layer 130 , a light emitting element array layer, a first auxiliary wire and a second auxiliary wire.

Wherein, the substrate 110 , the driving array layer 120 , the first insulating layer 130 and the light-emitting element array layer are similar to the display panel shown in FIG. 3 , and will not be repeated here.

In some embodiments, the first auxiliary wire may include a first wire body 151 and a first conductive structure 152 connected to each other, the first wire body 151 may be located on the side of the first insulating layer 130 facing the substrate 110 , and the first conductive structure 152 At least part of the first insulating layer 130 may be located on the side of the first insulating layer 130 away from the substrate 110, the first conductive structure 152 may be connected to the first conductive body 151 via vias, and the first conductive structure 152 may be connected to each first electrode in a first light emitting unit RE1 is electrically connected. Specifically, each first electrode RE1 in the first light emitting unit may be directly connected to the corresponding first conductive structure 152 via via hole, and the first wire body 151 may be directly connected to the corresponding first drain electrode D1 of the first transistor T1 via via hole connect.

In other embodiments, the second auxiliary wire may include a second wire body 161 and a second conductive structure 162 connected to each other, the second wire body 161 may be located on the side of the first insulating layer 130 away from the substrate 110 , and the second conductive structure At least part of the 162 may be located on the side of the driving array layer 120 away from the substrate 110, the second conductive structure 162 may be connected to the second conductive body 161 via vias, and the second conductive structure 162 may be electrically connected to the second transistor T2. Specifically, each second electrode RE2 in the second light emitting unit may be directly connected to the second wire body 161 via vias, and the second conductive structures 162 may be directly connected to the corresponding second drain electrodes D2 of the second transistor T2 via vias.

Therefore, in the embodiment of the present invention, the first conductive structure 152 connected to the first wire body 151 and the second conductive structure 162 connected to the second wire body 161 can be added to avoid excessively deep via holes. As a result, the processing difficulty of the display panel is relatively high, which reduces the processing difficulty of the display panel.

FIG. 5 is a schematic cross-sectional view along the line A-A in FIG. 1 according to yet another exemplary embodiment. As shown in FIG. 5 , the display panel 100 may include a substrate 110 , a driving array layer 120 , a first insulating layer 130 , a light emitting element array layer, a first auxiliary wire and a second auxiliary wire.

The substrate 110 , the driving array layer 120 , the first insulating layer 130 , the first auxiliary wires and the second auxiliary wires are similar to the display panel shown in FIG. 4 , and are not described here.

In some embodiments, the light-emitting element array layer may include a plurality of light-emitting units PU located in the first display area AA1, and the plurality of light-emitting units PU include a plurality of first light-emitting units and a plurality of second light-emitting units, and the first light-emitting units and The first pixel circuits are connected in a one-to-one correspondence, and the second light-emitting units are connected with the second pixel circuits in a one-to-one correspondence. Each first light emitting unit includes two first light emitting elements PX1, each first light emitting element PX1 includes a first electrode RE1, each second light emitting element includes two second light emitting elements PX2, and each second light emitting element PX2 A second electrode RE2 is included.

The first auxiliary wire may electrically connect the two first electrodes RE1 to the first transistor T1 of the first pixel circuit, and the second auxiliary wire may electrically connect the two second electrodes RE2 to the second transistor T2 of the second pixel circuit.

Therefore, in the embodiment of the present invention, one first transistor T1 can be connected to two or more than two first electrodes RE1 through one first auxiliary wire, and one second transistor T2 can be connected to the two or more first electrodes RE1 through one second auxiliary wire. The connection of two or more second electrodes RE2 can reduce the number of transistors, reduce the area of the second display area AA2 of the display panel 100, and further improve the display effect of the display panel.

It should be noted that, in some embodiments, as shown in FIG. 5 , two or more first light emitting elements PX1 in each first light emitting unit may share one first electrode RE1 . In other embodiments, two or more first light emitting elements PX1 in each first light emitting unit may also have an independent first electrode RE1, which is not limited herein.

FIG. 6 is a schematic cross-sectional view along the A-A direction in FIG. 1 according to yet another exemplary embodiment. As shown in FIG. 6 , the display panel 100 may include a substrate 110 , a driving array layer 120 , a first insulating layer 130 , a light emitting element array layer, a first auxiliary wire and a second auxiliary wire.

The substrate 110 , the driving array layer 120 , the first insulating layer 130 , the light-emitting element array layer and the second auxiliary wires are similar to the display panel shown in FIG. 4 , and will not be repeated here.

In some embodiments, the first auxiliary wire may include a first wire body 151 and a third conductive structure 153 that are connected to each other, the first wire body 151 and at least part of the third conductive structure 153 are disposed in the same layer, and the first wire body 151 The third conductive structure 153 may be directly connected between the first insulating layer 130 and the fourth insulating layer 180, the first wire body 151 is located on the side of the first insulating layer 130 facing the substrate 110, and at least part of the third conductive structure 153 is located on the side of the first insulating layer 130 facing the substrate 110. On the side of the driving array layer 130 facing away from the substrate 110 , the first conductive structure is electrically connected to the first transistor. Specifically, the third conductive structure 153 may be directly connected to the via hole of the first drain electrode D1 of the corresponding first transistor T1.

In one example, each of the first electrodes RE1 in the first light emitting unit may be directly connected to the corresponding first wire body 151 via vias.

In another example, the first auxiliary wire may further include a first conductive structure 152 connected to the first wire body 151 , and at least part of the first conductive structure 152 may be located on the side of the first insulating layer 130 away from the substrate 110 . The conductive structure 152 may be electrically connected to each of the first electrodes RE1 in one first light emitting unit. Specifically, each of the first electrodes RE1 in the first light emitting unit may be directly connected to the corresponding first conductive structure 152 via via holes.

In other embodiments, the display panel 100 may further include a signal line 230, wherein the signal line 230 may include at least one of a scan line, a reference voltage signal line and a power supply signal line. The signal wire 230 may be disposed on the same layer as the first wire body 151 .

Therefore, in the embodiment of the present invention, the resistance of the first auxiliary wire can be reduced by increasing the third conductive structure 153 connected to the first wire body 151, thereby improving the reliability of the display panel.

FIG. 7 is a schematic cross-sectional view along the line A-A in FIG. 1 according to yet another exemplary embodiment. As shown in FIG. 7 , the display panel 100 may include a substrate 110 , a driving array layer 120 , a first insulating layer 130 , a light emitting element array layer, a first auxiliary wire and a second auxiliary wire.

The substrate 110 , the driving array layer 120 , the light-emitting element array layer, the first auxiliary wire and the second auxiliary wire are similar to the display panel shown in FIG. 4 , and will not be repeated here.

In some embodiments, the first insulating layer 130 may include a first sub-insulating layer 131 and a second sub-insulating layer 132, the second sub-insulating layer 132 is located on the side of the first sub-insulating layer 131 away from the substrate 110, and the first sub-insulating layer 132 The layer 131 is located on the side of the first auxiliary wire away from the substrate 110 , and the second auxiliary wire is located at the side of the second sub-insulating layer 132 away from the substrate 110 . Wherein, at least part of the first auxiliary wire (eg, the first wire body 151 ) is located on the side of the first sub-insulation layer 131 facing the substrate 110 , and at least part of the second auxiliary wire (eg, the second wire body 161 ) is located on the second sub-insulation layer Layer 132 is on the side facing away from substrate 110 .

In other embodiments, the display panel 100 may further include signal lines 230, wherein the signal lines 230 may include at least one of scan lines, reference voltage signal lines, light control signal lines and power supply signal lines. The signal line 230 may be disposed between the first sub-insulating layer 131 and the second sub-insulating layer 132, so that the first sub-insulating layer 131 separates the signal line 230 from the first auxiliary wire, and the second sub-insulating layer 132 separates the signal line 230 from the first auxiliary wire. The signal wire 230 is isolated from the second auxiliary wire.

FIG. 8 is a schematic cross-sectional view along the line A-A in FIG. 1 according to yet another exemplary embodiment. As shown in FIG. 8 , the display panel 100 may include a substrate 110 , a driving array layer 120 , a first insulating layer 130 , a light emitting element array layer, a first auxiliary wire and a second auxiliary wire.

The substrate 110 , the driving array layer 120 , the first insulating layer 130 and the light-emitting element array layer are similar to the display panel shown in FIG. 7 , and will not be repeated here.

In some embodiments, the first conductive structure 152 of the first auxiliary wire may include a first conductive substructure 1521 and a second conductive substructure 1522, and at least part of the first conductive substructure 1521 is located on the backing liner of the first sub-insulation layer 131 On the bottom 110 side, at least part of the second conductive sub-structure 1522 may be located on the side of the second sub-insulating layer 132 away from the substrate 110 . Specifically, each first electrode RE1 in the first light-emitting unit can be directly connected to the corresponding first conductive substructure 1521 via via hole, and the first conductive substructure 1521 can be directly connected to the corresponding second conductive substructure 1522 via via hole, The second conductive substructure 1522 may be directly connected to the corresponding first wire body 151 via via holes.

In other embodiments, the second conductive structure 162 of the second auxiliary wire may include a third conductive substructure 1621 and a fourth conductive substructure 1622 , and at least part of the third conductive substructure 1621 is located away from the first sub-insulating layer 131 On the side of the substrate 110 , at least a portion of the fourth conductive substructure 1622 may be located on the side of the second sub-insulating layer 132 away from the substrate 110 . Specifically, each second electrode RE2 in the second light-emitting unit can be directly connected to the corresponding third conductive sub-structure 1621 via via hole, and the third conductive sub-structure 1621 can be directly connected to the corresponding fourth conductive sub-structure 1622 via via hole, The fourth conductive sub-structure 1622 may be directly connected to the corresponding second wire body 161 via via holes.

Therefore, in this embodiment of the present invention, the first conductive structure 152 can be subdivided into two independent structures, the first conductive substructure 1521 and the second conductive substructure 1522, and the second conductive structure 162 can be subdivided into two independent structures. The third conductive sub-structure 1621 and the fourth conductive sub-structure 1622 are divided into two independent structures to further reduce the resistance of the first auxiliary wire and the second auxiliary wire, thereby improving the reliability of the display panel.

FIG. 9 is a schematic cross-sectional view along the line A-A in FIG. 1 according to yet another exemplary embodiment. As shown in FIG. 9 , the display panel 100 may include a substrate 110 , a driving array layer 120 , a first insulating layer 130 , a light emitting element array layer, a first auxiliary wire and a second auxiliary wire.

The substrate 110 , the driving array layer 120 , the first insulating layer 130 and the light-emitting element array layer are similar to the display panel shown in FIG. 4 , and will not be repeated here.

In some embodiments, the display panel 100 may further include a second insulating layer 240, the second insulating layer 240 may be located between the driving array layer 120 and the first insulating layer 130, and at least part of the first auxiliary wires may be located on the second insulating layer The layer 240 faces away from the substrate 110 side.

Specifically, the fourth insulating layer 180 is located on the side of the driving array layer 120 facing away from the substrate 110 , and the second insulating layer 240 may be located on the side of the fourth insulating layer 180 facing away from the substrate 110 .

In some embodiments, the second insulating layers 240 may be organic insulating layers, respectively.

In some embodiments, the first auxiliary wire may include a first wire body 151 , a first conductive structure 152 and a fourth conductive structure 154 connected in sequence, and the first wire body 151 may be located between the first insulating layer 130 and the second insulating layer 240, at least part of the first conductive structure 152 may be located on the side of the first insulating layer 130 away from the substrate 110, at least part of the fourth conductive structure 154 is located between the second insulating layer 240 and the fourth insulating layer 180, the first The conductive structure 152 can be connected with the via holes of each first electrode RE1 in a first light emitting unit, the first conductive structure 152 can be connected with the via holes of the first conductive body 151, and the first wire body 151 can be directly connected with the fourth conductive structure 154 Via connection, the fourth conductive structure 154 may be directly connected to the via hole of the corresponding first drain electrode D1 of the first transistor T1.

In other embodiments, the second auxiliary wire may include a second wire body 161, a second conductive structure 162, and a fifth conductive structure 163 connected in sequence, the second wire body 161 may be located on the second wire body 161, and the second wire body 161 may be located on the An insulating layer 130 faces away from the substrate 110, at least part of the second conductive structure 162 may be located between the first insulating layer 130 and the second insulating layer 240, and at least part of the fifth conductive structure 163 may be located between the second insulating layer 240 and the second insulating layer 240. Between the fourth insulating layer 180 , each second electrode RE2 in the second light emitting unit can be directly connected to the second wire body 161 via vias, the second conductive structure 162 can be directly connected to the fifth conductive structure 163 via vias, and the fifth conductive structure 163 The conductive structure 163 may be directly connected to the via hole of the second drain electrode D2 of the corresponding second transistor T2.

Therefore, in the embodiment of the present invention, the fourth conductive structure 154 connected to the first wire body 151 and the fifth conductive structure 163 connected to the second conductive structure 162 can be added to avoid excessively deep via holes. As a result, the processing difficulty of the display panel is relatively high, which reduces the processing difficulty of the display panel.

FIG. 10 is a schematic cross-sectional view along the A-A direction in FIG. 1 according to yet another exemplary embodiment. As shown in FIG. 10 , the display panel 100 may include a substrate 110 , a driving array layer 120 , a first insulating layer 130 , a light emitting element array layer, a first auxiliary wire and a second auxiliary wire.

The substrate 110 , the driving array layer 120 , the first insulating layer 130 , the light-emitting element array layer, and the first auxiliary wires are similar to the display panel shown in FIG. 3 , and will not be repeated here.

In some embodiments, the second electrode RE2 may include a first conductive layer 251 , a second conductive layer 252 and a third conductive layer 253 stacked along the thickness direction of the display panel 100 , and a portion of the third conductive layer 253 forms the second auxiliary layer wire.

The material of the first conductive layer 251 and the third conductive layer 253 may be ITO, and the material of the second conductive layer 252 may be silver (Argentum, Ag).

In other embodiments, the first auxiliary wires are transparent metal wires. For example, the transparent metal wire may be an ITO wire or an IZO wire.

11 is a schematic cross-sectional view of a first electrode provided according to an embodiment of the present invention.

In some embodiments of the present invention, as shown in FIG. 11 , the first electrode RE1 may also include a seventh conductive layer 281 , an eighth conductive layer 282 and a ninth conductive layer 283 stacked along the thickness direction of the display panel 100 . The material of the seventh conductive layer 281 and the ninth conductive layer 283 may be ITO, and the material of the eighth conductive layer 282 may be Ag.

Therefore, in the embodiment of the present invention, the third conductive layer 253 of the second electrode RE2 can be reused as the second auxiliary wire to further reduce the number of film layers, so as to further reduce the number of film layers of the display panel, thereby reducing the number of film layers of the display panel. the difficulty of the production process.

FIG. 12 is a schematic top view of a display panel according to still another embodiment of the present invention. FIG. 13 is a schematic top view of a display panel according to still another embodiment of the present invention.

As shown in FIG. 12 , the display panel 100 has a first display area AA1 and a second display area AA2 adjacent to each other, and a third display area AA3 surrounding the first display area AA1 and the second display area AA2.

The structure of the display panel 100 is similar to that shown in FIG. 1 , and details are not described here.

In some embodiments of the present invention, as shown in FIG. 12 , each light-emitting unit PU in the first display area AA1 may be one-to-one with the pixel driving circuit DC in the side of the second display area AA2 close to the light-emitting unit PU, respectively. Correspondingly connected, and the projections of each row of the wires for connecting the pixel driving circuit DC of the same side of the second display area AA2 to the light emitting unit PU in the first display area AA1 can be overlapped.

In some embodiments of the present invention, as shown in FIG. 13 , each light-emitting unit PU in the first display area AA1 may be one-to-one with the pixel driving circuit DC in the side of the second display area AA2 close to the light-emitting unit PU, respectively. Correspondingly connected, and the projections of each row of the wires for connecting the pixel driving circuit DC of the same side of the second display area AA2 to the light emitting unit PU in the first display area AA1 can be staggered.

For the convenience of description, the following will take the display panel shown in FIG. 12 as an example for detailed description.

FIG. 14 is a schematic cross-sectional view along the direction B-B in FIG. 12 according to an exemplary embodiment. As shown in FIG. 14 , the display panel 100 may include a substrate 110 , a driving array layer 120 , a first insulating layer 130 , a light emitting element array layer, a first auxiliary wire and a second auxiliary wire.

The substrate 110 , the first insulating layer 130 , the first auxiliary wires and the second auxiliary wires are similar to the display panel shown in FIG. 3 , and will not be described in detail here.

In some embodiments, the pixel driving circuit DC driving the array layer 120 may further include a third pixel circuit, and the third pixel circuit includes a third transistor T3.

The third transistor T3 may include a third active layer N3, a third gate G3, a third source electrode S3 and a third drain electrode D3. The materials of the third active layer N3 are similar to those of the first active layer N1 and the second active layer N2 , which are not repeated here. The third active layer N3 may be disposed in the same layer as the first active layer N1 and the second active layer N2, the third gate G3 may be disposed in the same layer as the first gate G1 and the second gate G2, and the third source The electrode S3 and the third drain electrode D3 may be provided in the same layer as the first source electrode S1, the first drain electrode D1, the second source electrode S2 and the second drain electrode D2.

In some embodiments, the third transistor T3 may further include a third capacitor, and the first capacitor may include a fifth capacitor electrode C5 and a sixth capacitor electrode C6. The fifth capacitor electrode C5 is provided on the same layer as the first gate G1 and the third grid G3, and the sixth capacitor electrode C6 is provided on the same layer as the second capacitor electrode C2 and the fourth capacitor electrode C4.

In some embodiments, the light-emitting unit PU of the light-emitting element array layer may further include a plurality of third light-emitting units, the third light-emitting units are connected to the third pixel circuits in a one-to-one correspondence, and each third light-emitting unit may include at least one third light-emitting unit. The light emitting elements PX3, each of the third light emitting elements PX3 may include a third electrode RE3.

In some embodiments, the display panel 100 may further include a third insulating layer 220, the third insulating layer 220 may be located between the second auxiliary wires and the light emitting element array layer, and the third insulating layer 220 may serve as a planarization layer.

In some embodiments, the display panel 100 may further include third auxiliary wires, at least part of the third auxiliary wires may be located on the side of the third insulating layer 330 away from the substrate 110 , and the third auxiliary wires may Each of the third electrodes RE3 is electrically connected to the third transistor T3 of the third pixel circuit.

Optionally, the third auxiliary wire may include a third wire body, the third electrode RE3 may be directly connected to the via hole of the third wire body, and the third wire body may be directly connected to the via hole of the third drain electrode D3 of the third transistor T3. .

In other embodiments, the third electrode RE3 may include a fourth conductive layer 271 , a fifth conductive layer 272 and a sixth conductive layer 273 stacked along the thickness direction of the display panel 100 , and a portion of the sixth conductive layer 273 forms the third conductive layer 271 . Auxiliary lead.

The material of the fourth conductive layer 271 and the sixth conductive layer 273 may be ITO, and the material of the fifth conductive layer 272 may be Ag.

In still other embodiments, the first auxiliary wires and the second auxiliary wires may be transparent metal wires. For example, the transparent metal wire may be an ITO wire or an IZO wire.

In some embodiments of the present invention, the structures and materials of the first electrode RE1 and the second electrode RE2 are similar to those of the first electrode shown in FIG. 11 , and details are not described herein.

Therefore, in the embodiment of the present invention, the sixth conductive layer 273 of the third electrode RE3 can be multiplexed into the third auxiliary wire 260 to reduce the number of film layers, thereby reducing the number of film layers of the display panel and reducing the cost of the display panel. The difficulty of the production process.

An embodiment of the present invention also provides a display device, which may include the display panel in the embodiments shown in FIGS. 1 to 14 , so as to reduce the difficulty of the manufacturing process of the display device, improve the manufacturing efficiency of the display device, and reduce the cost of the display device. production cost.

Embodiments of the present invention further provide a method for manufacturing a display panel, which is used to manufacture the display panel in the embodiments shown in FIGS. 1 to 14 .

FIG. 15 is a schematic flowchart of a method for fabricating a display panel according to an embodiment of the present invention.

As shown in FIG. 15 , the manufacturing method of the display panel may include:

Step S1510, forming a driving array layer on the substrate.

Wherein, step S1510 may specifically include: sequentially forming a semiconductor layer, a first interlayer insulating layer, a first metal layer, a third interlayer insulating layer, a third metal layer, and a second interlayer in the array driving layer on the substrate an insulating layer and a second metal layer. Wherein, the semiconductor layer may include the first active layer of the first transistor and the second active layer of the second transistor, and the first metal layer may include the first gate of the first transistor, the first gate of the first transistor, the second active layer of the first capacitor of the first transistor a capacitor electrode, the second gate of the second transistor and the third capacitor electrode of the second capacitor of the second transistor, the second metal layer may include the first source electrode and the first drain electrode of the first transistor and the The second source electrode and the second drain electrode, and the third metal layer may include a second capacitor electrode of the first capacitor of the first transistor and a fourth capacitor electrode of the second capacitor of the second transistor.

Specifically, first, a semiconductor layer can be deposited on the substrate, and the semiconductor layer can be patterned by etching to form a first active layer and a second active layer; then, the substrate, the first active layer can be formed A first interlayer insulating layer and a first metal layer are sequentially deposited on the surfaces of the source layer and the second active layer, and the first metal layer is patterned by etching to form a first gate electrode, a first capacitor electrode, the second gate electrode and the third capacitor electrode; then, a third interlayer insulating layer may be sequentially deposited on the surfaces of the first interlayer insulating layer, the first gate electrode, the first capacitor electrode, the second gate electrode and the third capacitor electrode. layer and the third metal layer, and the third metal layer is patterned by etching to form the second capacitor electrode and the fourth capacitor electrode; A second interlayer insulating layer and a second metal layer are sequentially deposited on the surface of the four capacitor electrodes, and the second metal layer is patterned by etching to form a first source electrode, a first drain electrode, and a second source electrode and the second drain electrode.

Step S1520, covering the first wire layer on the driving array layer.

Specifically, the first wire layer may be deposited on the surface of the driving array layer on the side away from the substrate.

Step S1530 , patterning the first wire layer to form a plurality of first auxiliary wires.

Specifically, the first conductive line layer may be patterned by etching to form a plurality of first auxiliary conductive lines.

Step S1540, forming a first insulating layer covering the first auxiliary wire.

Specifically, a first insulating layer may be deposited on the surfaces of the driving array layer and the first auxiliary wires.

Step S1550 , forming a second auxiliary wire and a light-emitting element array layer on the first insulating layer.

Therefore, in the embodiment of the present invention, the display panel of the embodiment shown in FIG. 3 can be prepared, and in the manufacturing process, the number of film layers of the display panel can be reduced, the cost of the display panel can be saved, and the process of the display panel can be optimized. process, thereby reducing the difficulty of the manufacturing process of the display panel.

In some embodiments of the present invention, before step S1510, the manufacturing method of the display panel may further include: manufacturing a substrate.

Wherein, the specific method of fabricating the substrate may include: sequentially depositing a first organic layer, a first inorganic layer, a second organic layer and a second inorganic layer on the substrate substrate.

In other embodiments of the present invention, before step S1510, the method for fabricating the display panel may further include: depositing and forming a fourth insulating layer on the surface of the substrate.

Correspondingly, step S1510 may specifically include:

A driving array layer is formed on the fourth insulating layer.

Therefore, in the embodiment of the present invention, the driving array layer can be firmly disposed on the substrate.

In some embodiments of the present invention, after step S1550, the manufacturing method of the display panel may further include:

A pixel definition layer is deposited on the surfaces of the second auxiliary wires and the light-emitting element array layer.

The pixel definition layer is patterned in a variable manner to form a plurality of openings, each of which can be used to accommodate a light-emitting element.

The cathode of each light-emitting element is formed by deposition on the surface of the pixel-defining layer and the light-emitting element.

FIG. 16 is a schematic flowchart of a method for fabricating a display panel according to another embodiment of the present invention.

As shown in FIG. 16, in other embodiments of the present invention, before step S1550, the manufacturing method of the display panel may further include:

Step S1560 , patterning the first insulating layer, and forming a plurality of first via holes in the first insulating layer. Specifically, the first insulating layer may be patterned by etching to form a plurality of first via holes.

Correspondingly, step S1550 may specifically include:

Step S1551 , forming a second wire layer covering the first insulating layer. Specifically, the second wire layer may be deposited on the surface of the first insulating layer.

Step S1552 , patterning the second wire layer to form a plurality of second auxiliary wires. Specifically, the second wire layer may be patterned by etching to form a plurality of second auxiliary wires.

Step S1553, forming a third insulating layer covering the second auxiliary wire. Specifically, a third insulating layer may be deposited on the surfaces of the first insulating layer and the second auxiliary wire.

Step S1554, forming a light-emitting element array layer on the third insulating layer.

Therefore, in the embodiment of the present invention, the display panel of the embodiment shown in FIG. 3 can be prepared, and during the production process, the process flow can be optimized, and the existing insulating layer can be used to reduce the number of film layers of the display panel, The cost of the display panel is saved, and the process flow of the display panel is optimized, thereby reducing the difficulty of the manufacturing process of the display panel.

FIG. 17 is a schematic flowchart of a method for fabricating a display panel according to yet another embodiment of the present invention.

As shown in FIG. 17 , in still other embodiments of the present invention, step S1550 may further specifically include:

Step S1555, forming a light-emitting element array layer on the first insulating layer.

Step S1556 , patterning the first insulating layer, and forming a plurality of first via holes in the first insulating layer. Specifically, the first insulating layer may be patterned by etching to form a plurality of first via holes.

Step S1557, forming a second wire layer covering the light-emitting element array layer. Specifically, the second wire layer may be deposited on the surface of the light-emitting element array layer and the first insulating layer.

Step S1558 , patterning the second wire layer to form a plurality of second auxiliary wires. Specifically, the second wire layer may be patterned by etching to form a plurality of second auxiliary wires.

Therefore, in the embodiment of the present invention, the display panel of the embodiment shown in FIG. 3 can be prepared, and during the production process, the process flow can be optimized, and after the light-emitting element array layer is fabricated, the second auxiliary wire is fabricated, not only The annealing process is saved, and since the second wire layer covers the light-emitting element array layer, it can also avoid over-etching to the light-emitting element array layer when the second auxiliary wire is etched.

FIG. 18 is a schematic flowchart of a method for fabricating a display panel according to still another embodiment of the present invention.

As shown in FIG. 18, in some further embodiments of the present invention, before step S1550, the manufacturing method of the display panel may further include:

Step S1570 , patterning the first insulating layer, and forming a plurality of first via holes in the first insulating layer. Specifically, the first insulating layer may be patterned by etching to form a plurality of first via holes.

Correspondingly, step S1550 may specifically include:

Step S1581, forming a second wire layer covering the first insulating layer. Specifically, the second wire layer may be deposited on the surface of the first insulating layer.

Step S1582 , patterning the second wire layer to form a plurality of second auxiliary wires. Specifically, the second wire layer may be patterned by etching to form a plurality of second auxiliary wires.

Step S1583, annealing the plurality of second auxiliary wires.

Step S1584, forming a light-emitting element array layer on the second auxiliary wire.

Therefore, in the embodiment of the present invention, the display panel of the embodiment shown in FIG. 10 can be prepared, and in the manufacturing process, the process flow can be optimized, and the existing insulating layer can be used, which further reduces the number of film layers of the display panel , thereby further reducing the difficulty of the manufacturing process of the display panel.

In still other embodiments of the present invention, when the second electrode includes a first conductive layer, a second conductive layer, and a third conductive layer that are stacked along the thickness direction of the display panel, and a portion of the third conductive layer forms a second auxiliary wire Next, step S1550 may also specifically include:

The first insulating layer is patterned, and a plurality of first via holes are formed in the first insulating layer. Specifically, the first insulating layer may be patterned by etching to form a plurality of first via holes.

A third conductive metal layer is formed overlying the first insulating layer. Specifically, a third conductive metal layer may be deposited on the surface of the first insulating layer.

The third conductive metal layer is patterned to form a plurality of third conductive layers, and parts of the third conductive layers form second auxiliary wires. Specifically, the third conductive metal layer can be patterned by etching to form a plurality of third conductive layers, and the third conductive layers can be multiplexed into the second auxiliary wires.

A second conductive metal layer is formed overlying the third conductive layer. Specifically, the second conductive metal layer may be deposited on the surfaces of the first insulating layer and the third conductive layer.

The second conductive metal layer is patterned to form a plurality of second conductive layers. Specifically, the second conductive metal layer may be patterned by etching to form a plurality of second conductive layers.

A first conductive metal layer is formed overlying the second conductive layer. Specifically, the first conductive metal layer may be deposited on the surfaces of the first insulating layer, the third conductive layer and the second conductive layer.

The first conductive metal layer is patterned to form a plurality of first conductive layers. Specifically, the first conductive metal layer may be patterned by etching to form a plurality of first conductive layers.

It should be noted that, while forming the three-layer conductive layer of the second electrode, the three-layer conductive layer of the first electrode may also be formed, which will not be repeated here.

Therefore, in the embodiment of the present invention, the display panel of the embodiment shown in FIG. 14 can be prepared, and in the manufacturing process, the bottom conductive layer of the second electrode can be multiplexed into the second auxiliary wire, so that the display panel can be Has a higher pixel density.

In still other embodiments of the present invention, the semiconductor layer includes a third active layer of a third transistor, the first metal layer includes a third gate of the third transistor, and the second metal layer includes a third source electrode of the third transistor and the third drain electrode and the third electrode include a fourth conductive layer, a fifth conductive layer and a sixth conductive layer that are stacked along the thickness direction of the display panel, and a portion of the sixth conductive layer forms a third auxiliary wire, in step Before S1550, the manufacturing method of the display panel may further include:

The first insulating layer is patterned, and a plurality of first via holes are formed in the first insulating layer. Specifically, the first insulating layer may be patterned by etching to form a plurality of first via holes.

Correspondingly, step S1550 may specifically include:

A second wiring layer is formed overlying the first insulating layer. Specifically, the second wire layer may be deposited on the surface of the first insulating layer.

The second wire layer is patterned to form a plurality of second auxiliary wires. Specifically, the second wire layer may be patterned by etching to form a plurality of second auxiliary wires.

A third insulating layer covering the second auxiliary wire is formed. Specifically, a third insulating layer may be deposited on the surfaces of the first insulating layer and the second auxiliary wire.

The third insulating layer is patterned, and a plurality of second via holes are formed in the third insulating layer. Specifically, the third insulating layer may be patterned by etching to form a plurality of third via holes.

A third conductive metal layer is formed overlying the third insulating layer. Specifically, the third conductive metal layer may be deposited on the surface of the third insulating layer.

The third conductive metal layer is patterned to form a plurality of sixth conductive layers, and parts of the sixth conductive layers form third auxiliary wires. Specifically, the third conductive metal layer may be patterned by etching to form a plurality of sixth conductive layers, so that the sixth conductive layers are multiplexed into third auxiliary wires.

A second conductive metal layer is formed overlying the sixth conductive layer. Specifically, the second conductive metal layer may be deposited on the surfaces of the third insulating layer and the sixth conductive layer.

The second conductive metal layer is patterned to form a plurality of fifth conductive layers. Specifically, the second conductive metal layer may be patterned by etching to form a plurality of fifth conductive layers.

A first conductive metal layer is formed overlying the fifth conductive layer. Specifically, the first conductive metal layer may be deposited on the surfaces of the third insulating layer, the sixth conductive layer and the fifth conductive layer.

The first conductive metal layer is patterned to form a plurality of fourth conductive layers. Specifically, the first conductive metal layer may be patterned by etching to form a plurality of fourth conductive layers.

It should be noted that, when the three-layer conductive layer of the third electrode is formed, the three-layer conductive layer of the first electrode and the second electrode may also be formed, which will not be described here.

Therefore, in the embodiment of the present invention, the bottom conductive layer of the third electrode can be multiplexed into the third auxiliary wire, so that the display panel has a higher pixel density.

FIG. 19 is a schematic diagram of a process flow of a display panel according to an embodiment of the present invention.

As shown in Figure 19, the process flow of the display panel is as follows:

Throwing in the substrate → making the substrate → forming the fourth insulating layer → forming the first active layer and the second active layer → forming the first interlayer insulating layer → forming the first gate, the first capacitor electrode and the second gate electrode and third capacitor electrode→form third interlayer insulating layer→form second capacitor electrode and fourth capacitor electrode→form second interlayer insulating layer→form first source electrode, first drain electrode, second source electrode and second drain electrode → forming a fourth interlayer insulating layer → forming a second insulating layer → forming a second conductive structure → forming a first wire body → forming a first insulating layer → forming a first conductive structure and a second wire body → forming a first wire body Three insulating layers→forming a first electrode and a second electrode→forming a pixel definition layer→forming a cathode.

The display panel of the embodiment shown in FIG. 4 can be prepared according to the above-mentioned process flow of the display panel.

To sum up, the embodiments of the present invention can reasonably arrange the display panel to reduce the number of film layers of the display panel, save the cost of the display panel, and optimize the process flow of the display panel, thereby reducing the difficulty of the manufacturing process of the display panel.

In accordance with the embodiments of the present invention as described above, these embodiments do not exhaustively describe all the details and do not limit the invention to only the specific embodiments described. Obviously, many modifications and variations are possible in light of the above description. This specification selects and specifically describes these embodiments in order to better explain the principle and practical application of the present invention, so that those skilled in the art can make good use of the present invention and modifications based on the present invention. The present invention is to be limited only by the claims and their full scope and equivalents.

Claims (21)

1. A display panel comprising a first display area and a second display area adjacent to each other, the light transmittance of the first display area is greater than the light transmittance of the second display area, wherein the display Panels include: substrate; A driving array layer, located on the substrate, the driving array layer comprising a plurality of pixel driving circuits in the second display area, the pixel driving circuits comprising a first pixel circuit and a second pixel circuit, the first pixel circuit a pixel driving circuit includes a first transistor, the second pixel circuit includes a second transistor; a first insulating layer, located on the side of the driving array layer away from the substrate; A light-emitting element array layer, located on the side of the first insulating layer away from the substrate, the light-emitting element array layer comprising a plurality of first light-emitting units and a plurality of second light-emitting units located in the first display area, the The first light-emitting unit is connected with the first pixel circuit in a one-to-one correspondence, and the second light-emitting unit is connected with the second pixel circuit in a one-to-one correspondence; each of the first light-emitting units includes at least one first light-emitting element, Each of the first light-emitting elements includes a first electrode, each of the second light-emitting units includes at least one second light-emitting element, and each of the second light-emitting elements includes a second electrode; a first auxiliary wire, at least a part of the first auxiliary wire is located on the side of the first insulating layer facing the substrate, and the first auxiliary wire connects each of the first electrodes in one of the first light-emitting units electrically connected to the first transistor of the first pixel circuit; A second auxiliary wire, at least a part of the second auxiliary wire is located on the side of the first insulating layer away from the substrate, the second auxiliary wire connects each of the second electrodes in one of the second light-emitting units is electrically connected to the second transistor of the second pixel circuit. 2 . The display panel according to claim 1 , wherein the first auxiliary wire comprises a first wire body, and the first wire body is located on the side of the first insulating layer facing the substrate. 3 . 3 . The display panel according to claim 1 , wherein the first auxiliary wire comprises a first wire body and a first conductive structure that are connected to each other, and the first wire body is located in the direction of the first insulating layer. 4 . on the substrate side, at least part of the first conductive structure is located on the side of the first insulating layer away from the substrate; Wherein, the first conductive structure is electrically connected to each of the first electrodes in one of the first light-emitting units. 4 . The display panel according to claim 1 , wherein the second auxiliary wire comprises a second wire body and a second conductive structure that are connected to each other, and the second wire body is located away from the first insulating layer. 5 . on the substrate side, at least part of the second conductive structure is located on the side of the driving array layer away from the substrate; Wherein, the second conductive structure is electrically connected to the second transistor. 5 . The display panel according to claim 1 , wherein the first auxiliary wire comprises a first wire body and a third conductive structure that are connected to each other, and the first wire body is located in the direction of the first insulating layer. 6 . on the substrate side, at least part of the third conductive structure is located on the side of the driving array layer away from the substrate; Wherein, the first conductive structure is electrically connected to the first transistor. 6 . The display panel according to claim 1 , wherein the first insulating layer comprises a first sub-insulating layer and a second sub-insulating layer, and the second sub-insulating layer is located in the the side of the first sub-insulating layer facing away from the substrate; Wherein, at least part of the first auxiliary wire is located on the side of the first sub-insulating layer facing the substrate, and at least part of the second auxiliary wire is located on the side of the second sub-insulating layer facing away from the substrate. 7. The display panel according to any one of claims 1 to 5, wherein the display panel further comprises: A second insulating layer is located between the driving array layer and the first insulating layer, and at least part of the first auxiliary wires is located on the side of the second insulating layer facing away from the substrate. 8 . The display panel according to claim 1 , wherein the second electrode comprises a first conductive layer, a second conductive layer and a third conductive layer that are stacked along a thickness direction of the display panel, and the first conductive layer Portions of the three conductive layers form the second auxiliary wires. 9 . The display panel of claim 8 , wherein the first auxiliary wires are transparent metal wires. 10 . 10. The display panel according to claim 1, wherein the display panel further comprises: A third insulating layer is located between the second auxiliary wire and the light-emitting element array layer. 11. The display panel according to claim 10, wherein, The pixel driving circuit further includes a third pixel circuit, and the third pixel circuit includes a third transistor; The light-emitting element array layer further includes a plurality of third light-emitting units located in the first display area, the third light-emitting units are connected to the third pixel circuits in a one-to-one correspondence, and each of the third light-emitting units includes at least one third light-emitting element, each of the third light-emitting elements including a third electrode; Wherein, the display panel further includes: a third auxiliary wire, at least a part of the third auxiliary wire is located on the side of the third insulating layer away from the substrate, the third auxiliary wire connects each of the third electrodes in one of the third light-emitting units is electrically connected to the third transistor of the third pixel circuit. 12 . The display panel according to claim 11 , wherein the third electrode comprises a fourth conductive layer, a fifth conductive layer and a sixth conductive layer stacked along a thickness direction of the display panel, and the first conductive layer is 12 . Portions of the six conductive layers form the third auxiliary wire. 13. The display panel according to claim 11 or 12, wherein the first auxiliary wire and the second auxiliary wire are transparent metal wires. 14. The display panel of claim 1, wherein the first transistor comprises a first active layer, a first gate, a first source electrode and a first drain electrode, and the second transistor comprises a first two active layers, a second gate electrode, a second source electrode and a second drain electrode; Wherein, the drive array layer includes: a semiconductor layer on the substrate, the semiconductor layer including the first active layer and the second active layer; a first interlayer insulating layer, located on the side of the semiconductor layer away from the substrate; a first metal layer, located on the side of the first interlayer insulating layer away from the substrate, the first metal layer including the first gate and the second gate; a second interlayer insulating layer, located on the side of the first metal layer away from the substrate; A second metal layer, located on the side of the second interlayer insulating layer away from the substrate, the second metal layer includes the first source electrode, the first drain electrode, the second source electrode and the the second drain electrode; The first auxiliary wire is connected to the corresponding first drain electrode of the first transistor, and the second auxiliary wire is connected to the corresponding second drain electrode of the second transistor. 15. A display device, comprising the display panel according to any one of claims 1 to 14. 16. A method for manufacturing a display panel as claimed in claim 1, characterized in that, comprising: forming a driving array layer on the substrate; covering a first wire layer on the driving array layer; patterning the first wire layer to form a plurality of first auxiliary wires; forming a first insulating layer covering the first auxiliary wire; A second auxiliary wire and a light-emitting element array layer are formed on the first insulating layer. 17. The method according to claim 16, wherein before the forming the second auxiliary wires and the light-emitting element array layer on the first insulating layer, the method further comprises: patterning the first insulating layer to form a plurality of first via holes in the first insulating layer; The forming of the second auxiliary wires and the light-emitting element array layer on the first insulating layer includes: forming a second wire layer covering the first insulating layer; patterning the second wire layer to form a plurality of the second auxiliary wires; forming a third insulating layer covering the second auxiliary wire; The light-emitting element array layer is formed on the third insulating layer. 18. The method according to claim 16, wherein the forming the second auxiliary wires and the light-emitting element array layer on the first insulating layer comprises: forming the light-emitting element array layer on the first insulating layer; patterning the first insulating layer to form a plurality of first via holes in the first insulating layer; forming a second wire layer covering the light-emitting element array layer; The second wire layer is patterned to form a plurality of the second auxiliary wires. 19. The method according to claim 16, wherein before the forming the second auxiliary wires and the light-emitting element array layer on the first insulating layer, the method further comprises: patterning the first insulating layer to form a plurality of first via holes in the first insulating layer; The forming of the second auxiliary wires and the light-emitting element array layer on the first insulating layer includes: forming a second wire layer covering the first insulating layer; patterning the second wire layer to form a plurality of the second auxiliary wires; annealing a plurality of the second auxiliary wires; On the second auxiliary wire, the light-emitting element array layer is formed. 20. The method according to claim 16, wherein the forming the second auxiliary wires and the light-emitting element array layer on the first insulating layer comprises: patterning the first insulating layer to form a plurality of first via holes in the first insulating layer; forming a third conductive metal layer covering the first insulating layer; patterning the third conductive metal layer to form a plurality of third conductive layers, and parts of the third conductive layers form the second auxiliary wires; forming a second conductive metal layer covering the third conductive layer; patterning the second conductive metal layer to form a plurality of the second conductive layers; forming a first conductive metal layer covering the second conductive layer; The first conductive metal layer is patterned to form a plurality of the first conductive layers. 21. The method according to claim 16, wherein before forming the second auxiliary wires and the light-emitting element array layer on the first insulating layer, the method further comprises: patterning the first insulating layer to form a plurality of first via holes in the first insulating layer; The forming of the second auxiliary wires and the light-emitting element array layer on the first insulating layer includes: forming a second wire layer covering the first insulating layer; patterning the second wire layer to form a plurality of the second auxiliary wires; forming a third insulating layer covering the second auxiliary wire; patterning the third insulating layer to form a plurality of second via holes in the third insulating layer; forming a third conductive metal layer covering the third insulating layer; patterning the third conductive metal layer to form a plurality of sixth conductive layers, and parts of the sixth conductive layers form the third auxiliary wires; forming a second conductive metal layer covering the sixth conductive layer; patterning the second conductive metal layer to form a plurality of the fifth conductive layers; forming a first conductive metal layer covering the fifth conductive layer; The first conductive metal layer is patterned to form a plurality of the fourth conductive layers.

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