CN111679933A - Extended EDAC (electronic design automation) calibration circuit for externally extending Flash program storage area and read-write method - Google Patents
Extended EDAC (electronic design automation) calibration circuit for externally extending Flash program storage area and read-write method Download PDFInfo
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- G06—COMPUTING OR CALCULATING; COUNTING
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- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1068—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices in sector programmable memories, e.g. flash disk
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/0614—Improving the reliability of storage systems
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0629—Configuration or reconfiguration of storage systems
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0646—Horizontal data movement in storage systems, i.e. moving data in between storage devices or systems
- G06F3/0652—Erasing, e.g. deleting, data cleaning, moving of data to a wastebasket
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0673—Single storage device
- G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/38—Response verification devices
- G11C29/42—Response verification devices using error correcting codes [ECC] or parity check
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- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
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Abstract
The invention discloses an extended Flash program storage area extended EDAC (electronic design automation) calibration circuit and a read-write method, wherein a bus driver, an AND gate, an OR gate and a NOT gate are added between a processor interface and an extended FLASH to realize the read-write operation of the extended FLASH 2; the data lines D [0:7] and the check bits PD [0:7] are connected with the data lines of the FLASH through a bus driver, and in order to prevent the data lines from colliding, the OE enabling end of the bus driver is controlled through GPIO5, GPIO6 and combined logic of an AND gate, an OR gate and a NOT gate to be gated; the method can be applied to the external expansion of the EDAC function of the FLASH inside the miniaturized SIP module of the space computer, can effectively improve the single event upset resistance of the FLASH as a program storage area space, greatly improves the single event upset resistance of the FLASH as the program storage area in the space environment on the premise of meeting the functional performance of the whole computer, improves the reliability of the whole computer, and meets the requirements of design standardization, miniaturization and localization of the space computer.
Description
Technical Field
The invention belongs to the field of application of space embedded computers, and particularly relates to an extended EDAC (electronic design automation) calibration circuit for an extended Flash program storage area and a read-write method.
Background
Miniaturization is a development trend of a space embedded computer, and a processor system and a functional module in the computer are built by adopting discrete devices at present, so that the computer is large in size and heavy in weight. The development and application of the SIP technology provide technical support for the miniaturization design of the space embedded computer. The current SIP module LSCCU01RH which is applied to a space computer and flies successfully enables the size, weight, power consumption and the like of the computer to be greatly reduced, and the module works stably, is good in performance and mature in technology.
The SIP module LSCCU01RH integrates resources such as CPU, SRAM, FLASH and interface circuit, i.e. CPU board function is integrated in one SIP module, the space computer design is realized by taking CPU as core, SRAM as data memory and FLASH as program memory, thus the SIP module can form the minimum system of processor as core function of space computer. In order to improve the adaptability of a space environment, a CPU And an SRAM in the SIP realize an EDAC (error Detection And correction) function of 32-bit data lines And 8-bit check bits, realize 'one check And two check', And can improve the single event upset resistance of the space, but the FLASH serving as a program memory only has 32-bit data lines And no check bits due to the complexity of operation And the limitation of the internal space of the SIP, cannot realize the EDAC function, And has a single event upset risk in the space application environment as the program memory.
Disclosure of Invention
In order to solve the problems, the invention provides an extended Flash program storage area extended EDAC calibration circuit and a read-write method, which realize that a piece of FLASH and a peripheral circuit are extended outside an SIP (Session initiation protocol) to be used as an 8-bit calibration bit memory and are combined with an internal FLASH to form an EDAC function of a 32-bit data line and an 8-bit calibration bit, and can effectively improve the single-event upset resistance of a space computer program storage area, thereby greatly improving the space environment adaptability and the application reliability of a space computer.
In order to solve the problems in the prior art, the invention provides an extended Flash program storage area extended EDAC calibration circuit, which realizes that a piece of FLASH and a peripheral circuit are extended outside an SIP (Session initiation protocol) to be used as an 8-bit calibration bit memory and are combined with an internal FLASH to form an EDAC function of a 32-bit data line and an 8-bit calibration bit, and can effectively improve the single-event upset resistance of a space computer program storage area, thereby greatly improving the space environment adaptability and the application reliability of a space computer.
In order to achieve the purpose, the invention adopts the technical scheme that the extended Flash program storage area extended EDAC check circuit comprises a processor and an extended FLASH2, wherein the extended FLASH2 is used for storing EDAC codes; the data line of the external expansion FLASH2 is connected with the data line D [0:7] and the check bit PD [0:7] through a bus driver, the output ends of the ROMCS0 and the first OR gate are connected with the input end of the first AND gate, and the output end of the first AND gate is respectively connected with the FLASHCS of the processor and the CE of the external expansion FLASH 2;
the RAMCS1 and the GPIO6 are connected with the input end of a first OR gate, and the output end of the first OR gate is respectively connected with the input end of the first AND gate, the input end of the second OR gate and the input end of the second AND gate; the GPIO5 and the output end of the first OR gate are connected with the input end of the second OR gate, and the output end of the second OR gate is connected with 1OE of the bus driver; the GPIO5 is connected with the input end of a NOT gate, the output end of the NOT gate and the output end of a second AND gate are connected with the input end of a third OR gate, and the output end of the third OR gate is connected with 2OE of a bus driver; the output of the first or gate and ROMCS0 are connected to the input of the second and gate.
D [0:7] of the processor is connected with 1A [1:8] of the bus driver, 1B [1:8] of the bus driver is connected with D [0:7] of the external expansion FLASH 2; d [0:7] of the external FLASH2 is connected with 2B [1:8] of the bus driver, and 2A [1:8] of the bus driver is connected with PD [0:7] of the processor.
The read-write signal interface of the processor is respectively connected with the read-write signal interface of the externally expanded FLASH2, and simultaneously, the read signal OE interface is connected with the PD [0:7] direction control end 2DIR of the bus driver; during write operation, the read signal OE is high, and 2A to 2B data transmission is realized; during a read operation, the read signal OE is low, and the data transfer from 2B to 2A is realized.
The processor 1 works in the RAM area and turns on EDAC enable; setting 1OE of GPIO5 and GPIO6 to enable bus driver 3 to be low; 2OE is high; performing a write sequence according to the external FLASH2 erase operation;
setting GPIO5 and GPIO6 to enable the 1OE of the bus driver to be high and 2OE to be low;
performing a write operation to the outward extension FLASH 2; the processor switches the working area into a ROM area;
the processor begins a read operation.
The read-write method of the EDAC calibration circuit comprises the following steps:
1) when the SRCTRL configuration register of the processor is operated to configure the memory size before the EDAC code is written, the capacity of the RAM area is configured to be 4 MB;
2) when the processor writes data into the externally extended FLASH2 through the RAMCS1, the processor firstly erases the externally extended FLASH2, sets the directions of the GPIO5 and the GPIO6 of the processor as output, and outputs 0, at this time, writes a FLASH erasing sequence into a base address 0x40400000 of the RAMCS1 area, and finishes erasing the externally extended FLASH 2;
3) after the external expansion FLASH2 is erased, when the processor writes data to the external expansion FLASH2, a write sequence needs to be written first when each 32-bit word is written, and then the data is written to a corresponding address; before writing the write sequence, outputting 0 to the GPIO 5; before data is written, GPIO5 is output as 1;
4) the processor writes data into a space with an address range of 0x 40400000-0 x407F FFFF, namely, the program writing operation of a program area with an EDAC function and an external FLASH2 is completed; then outputting 1 to GPIO5 and GPIO 6;
5) the processor completes normal read operation on the program area and the external FLASH2 by reading the space with the address range of 0x 00000000-0 x003F FFFF.
The address ranges of ROMCS0 and RAMCS1 are:
| address space | Chip selection | Address range | |
| PROM area | ROMCS0 | 0x0000 0000～0x003F FFFF | 4MB, LSCCU01RH internal Flash |
| SRAM region | RAMCS1 | 0x4040 0000～0x407F FFFF | 4MB |
。
The FLASH erase sequence is as follows:
The write sequence of the outer extension FLASH2 is as follows:
Compared with the prior art, the invention has at least the following beneficial effects: the invention realizes the function of expanding the EDAC outside the FLASH inside the miniaturized SIP module of the space computer, the function can effectively improve the single event upset resistance of the FLASH as a program storage area space, and the design standardization, miniaturization and localization requirements of the space computer are met. The functions realized by the invention have the characteristics of universality, standardization, high reliability and the like, and the computer system constructed by the method greatly improves the single-particle-upset resistance of FLASH as a program storage area in a space environment and improves the reliability of the whole computer on the premise of meeting the functional performance of the whole computer. The invention can be widely applied to the field of LSCCU01RH as a processor star ship computer product, can improve the adaptability of product space environment on the basis of miniaturization, and has good economic benefit and social benefit.
Drawings
Fig. 1 is a functional block diagram of an internal FLASH expansion EDAC of a module.
Fig. 2 is a schematic diagram of the EDAC principle of FLASH expansion inside the space computer LSCCU01 RH.
Detailed Description
The present invention will be described in detail with reference to examples
EDAC (error detection and correction), which is a basic function of an internal processor of the LSCCU01RH, can realize 'one correction and two detection', and can form a Flash memory area circuit with an EDAC (error detection and correction) checking function by expanding a Flash memory circuit for storing EDAC codes outside a module; as shown in figure 1. The embodiment of the invention provides a circuit for checking an EDAC (electronic design automation) by using an internal FLASH of an LSCCU01RH module as a program storage area and externally expanding the FLASH, and the principle design is as shown in FIG. 2, wherein the circuit comprises an LSCCU01RH processor 1, an externally expanded FLASH2 for the EDAC, a bus driver 3, a first AND gate 4, a first OR gate 5, a NOT gate 6, a second OR gate 7, a second AND gate 8 and a third OR gate 9.
The external interface of the processor 1 used in the implementation of the invention comprises a data line D [0:7], a check bit PD [0:7], an address signal A [2:21], a read signal OE, a write signal WR, a RAM area chip selection signal RAMCS1, a ROM area chip selection signal ROMCS0, an internal FLASH chip selection FLASHCS, a general IO interface GPIO5 and a GPIO 6.
The bus driver 3, the first and gate 4, the first or gate 5, the not gate 6, the second or gate 7, the second and gate 8 and the third or gate 9 are added between the processor 1 and the external extension FLASH2 for realizing the read-write operation of the external extension FLASH 2.
The data lines D [0:7] and the check bits PD [0:7] are connected with the data lines of the external FLASH2 through the bus driver 3, and in order to prevent data line conflicts, the OE enabling end of the bus driver 3 is controlled through the GPIO5, the GPIO6, and the combined logic of the first AND gate 4, the first OR gate 5, the NOT gate 6, the second OR gate 7, the second AND gate 8 and the third OR gate 9 to gate.
The processor 1 is connected with the external expansion FLASH2 to realize that the EDAC function needs to perform erasing operation, EDAC code writing operation and reading operation, the CPU does not support the EDAC writing operation of the program storage space ROM area, the EDAC writing of the external expansion FLASH2 is realized by using the data storage area RAM chip selection RAMS 1, and then the ROM chip selection ROMCS is switched to be used as the program storage area EDAC code in application to finish EDAC verification in the program loading process of the processor 1.
The read-write signal interface of the processor 1 is respectively connected with the read-write signal interface of the externally expanded FLASH2, and simultaneously, the read signal OE is connected with the PD [0:7] direction control end 2DIR of the bus driver 3; during write operation, the read signal OE is high, and 2A to 2B data transmission is realized; during a read operation, the read signal OE is low, and the data transfer from 2B to 2A is realized.
The operation flow of the processor 1 to the extension FLASH2 is as follows: processor 1 works in RAM region and opens EDAC enable → set GPIO5, GPIO6 enables bus driver 3 with 1OE low and 2OE high → write sequence by extend FLASH2 erase operation → set GPIO5, GPIO6 enables bus driver 3 with 1OE high and 2OE low to write valid program code into extend FLASH2 → processor 1 switches working region to ROM region → processor 1 starts read operation.
The outputs of ROMCS0 and the first OR gate 5 are connected with the input end of the first AND gate 4, and the output end of the first AND gate 4 is respectively connected with the FLASHCS of the processor 1 and the CE of the external extension FLASH 2;
the RAMCS1 and the GPIO6 are connected with the input end of a first OR gate 5, and the output end of the first OR gate 5 is respectively connected with the input end of a first AND gate 4, the input end of a second OR gate 7 and the input end of a second AND gate 8;
the GPIO5 and the output end of the first OR gate 5 are connected with the input end of the second OR gate 7, and the output end of the second OR gate 7 is connected with 1OE of the bus driver 3;
the GPIO5 is connected with the input end of the NOT gate 6, the output end of the NOT gate 6 and the output end of the second AND gate 8 are connected with the input end of the third OR gate 9, and the output end of the third OR gate 9 is connected with 2OE of the bus driver 3; the output of the first or gate 5 and the ROMCS0 are connected to the input of the second and gate 8;
d [0:7] of the processor 1 → 1B [1:8] of the bus driver 3 → D [0:7] of the outward expansion FLASH 2; d [0:7] of the extension FLASH2 → 2B [1:8] of the bus driver 3 → PD [0:7] of the processor 1;
d [0:7] of the processor is connected with 1A [1:8] of the bus driver, 1B [1:8] of the bus driver is connected with D [0:7] of the external expansion FLASH 2; d [0:7] of the external FLASH2 is connected with 2B [1:8] of the bus driver, and 2A [1:8] of the bus driver is connected with PD [0:7] of the processor.
The read and write operations of the processor 1 on the EDAC verification circuit are as follows:
1) when the SRCTRL configuration register of the processor 1 is operated to configure the memory size before writing EDAC code, the capacity of the RAM area needs to be configured to 4 MB. The address ranges of ROMCS0 and RAMCS1 are shown in Table 1 below.
TABLE 1 chip select signal address assignment table
| Address space | Chip selection | Address range | Description of the invention |
| PROM area | ROMCS0 | 0x0000 0000～0x003F FFFF | 4MB, LSCCU01RH internal Flash |
| SRAM region | RAMCS1 | 0x4040 0000～0x407F FFFF | 4MB |
2) When the processor 1 writes data to the extension FLASH2 through the RAMCS1, the extension FLASH2 needs to be erased first. The GPIO5 and GPIO6 directions of the processor 1 are set as outputs and both output 0, at which time the FLASH erase sequence shown in table 2 is written to the RAMCS1 region base address 0x40400000, completing the erase of the extension FLASH 2.
Table 2 extension FLASH2 erase sequence
3) After the external FLASH2 is erased, when the processor 1 writes data to the external FLASH2, it needs to write a write sequence first and then write the data to a corresponding address every time a 32-bit word is written. The write sequence is shown in table 3.
Table 3 extension FLASH2 write sequence
Before writing the write sequence, outputting 0 to the GPIO 5; before writing data, GPIO5 is output with a 1.
4) The processor 1 writes data into a space with an address range of 0x 40400000-0 x407F FFFF, namely, completes program writing operation of the external expansion FLASH2 with the EDAC function. Finally, GPIO5 and GPIO6 are output 1 to prevent error operation of FLASH by RAMCS 1.
5) The processor 1 completes normal read operation on the program area and the extension FLASH2 by performing read operation on the space with the address range of 0x 00000000-0 x003F FFFF.
The embodiments of the present invention are merely illustrative of the spirit of the present invention, and those skilled in the art can modify the described embodiments or substitute them with similar ones without departing from the spirit of the present invention.
Claims (8)
1. An external Flash program storage area extension EDAC check circuit is characterized by comprising a processor (1) and an external FLASH2, wherein the external FLASH2 is used for storing EDAC codes; the data line of the external expansion FLASH2 is connected with a data line D [0:7] and check bits PD [0:7] through a bus driver (3), the output ends of the ROMCS0 and the first OR gate (5) are connected with the input end of the first AND gate (4), and the output end of the first AND gate (4) is respectively connected with a FLASHCS of the processor (1) and a CE of the external expansion FLASH 2;
the RAMCS1 and the GPIO6 are connected with the input end of a first OR gate (5), and the output end of the first OR gate (5) is respectively connected with the input end of a first AND gate (4), the input end of a second OR gate (7) and the input end of a second AND gate (8); the GPIO5 and the output end of the first OR gate (5) is connected with the input end of the second OR gate (7), and the output end of the second OR gate (7) is connected with 1OE of the bus driver (3); the GPIO5 is connected with the input end of the NOT gate (6), the output end of the NOT gate (6) and the output end of the second AND gate (8) are connected with the input end of a third OR gate (9), and the output end of the third OR gate (9) is connected with 2OE of the bus driver (3); the output of the first or gate (5) and ROMCS0 are connected to the input of the second and gate (8).
2. The outstretched Flash program memory area extension EDAC check circuit according to claim 1, characterized in that D [0:7] of the processor (1) is connected to 1A [1:8] of the bus driver (3), 1B [1:8] of the bus driver (3) is connected to D [0:7] of the outstretched Flash 2; d [0:7] of the external FLASH2 is connected with 2B [1:8] of the bus driver (3), and 2A [1:8] of the bus driver (3) is connected with PD [0:7] of the processor (1).
3. The extended Flash program storage area extension EDAC check circuit according to claim 1, characterized in that the read-write signal interface of the processor (1) is connected to the read-write signal interface of the extended Flash2, respectively, while the read signal OE interface is connected to the PD [0:7] direction control terminal 2DIR of the bus driver (3); during write operation, the read signal OE is high, and 2A to 2B data transmission is realized; during a read operation, the read signal OE is low, and the data transfer from 2B to 2A is realized.
4. The extended Flash program storage area extension EDAC check circuit according to claim 1, wherein processor 1 works in RAM area and turns on EDAC enable; setting 1OE of GPIO5 and GPIO6 to enable bus driver 3 to be low; 2OE is high; performing a write sequence according to the external FLASH2 erase operation;
setting 1OE of GPIO5 and GPIO6 to enable bus driver (3) to be high, and 2OE to be low;
performing a write operation to the outward extension FLASH 2; the processor (1) switches the working area to a ROM area;
the processor (1) starts a read operation.
5. Method of reading and writing EDAC verification circuits according to claim 1,
1) when the SRCTRL configuration register of the processor (1) is operated to configure the memory size before the EDAC code is written, the capacity of the RAM area is configured to be 4 MB;
2) when the processor (1) writes data into the externally extended FLASH2 through the RAMCS1, firstly erasing the externally extended FLASH2, setting the directions of the GPIO5 and the GPIO6 of the processor (1) as output, and outputting 0, at this time, completing the erasing of the externally extended FLASH2 by a FLASH erasing sequence written into the base address 0x40400000 of the RAMCS1 region;
3) after the external expansion FLASH2 is erased, when the processor (1) writes data to the external expansion FLASH2, a write sequence needs to be written first when each 32-bit word is written, and then the data is written to a corresponding address; before writing the write sequence, outputting 0 to the GPIO 5; before data is written, GPIO5 is output as 1;
4) the processor (1) writes data into a space with an address range of 0x 40400000-0 x407F FFFF, namely, the program writing operation of a program area with an EDAC function and an external FLASH2 is completed; then outputting 1 to GPIO5 and GPIO 6;
5) the processor (1) completes normal read operation on the program area and the extension FLASH2 by performing read operation on the space with the address range of 0x 00000000-0 x003F FFFF.
6. The method for reading and writing EDAC verification circuits according to claim 5, wherein the address ranges of ROMCS0 and RAMCS1 are:
。
7. The method of claim 5, wherein the FLASH erase sequence is as follows:
GPIO5 outputs 0; GPIO6 outputs a 0.
8. The method of claim 5, wherein the external FLASH2 write sequence is as follows:
GPIO5 outputs 0; GPIO6 outputs a 0.
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|---|---|---|---|---|
| CN114385410A (en) * | 2022-01-12 | 2022-04-22 | 西安微电子技术研究所 | EDAC (electronic design automation) checking circuit and method for PROM (programmable read only memory) program storage area extension |
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| CN111679933B (en) | 2023-03-31 |
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