CN111666106A - Data offload acceleration from multiple remote chips - Google Patents

Abstract

Embodiments of the present disclosure relate to data offload acceleration from multiple remote chips. The data offload accelerator offloads data from the plurality of remote chips to the processor. A specification of a plurality of addresses for retrieving data from a plurality of remote chips is received into an address buffer bank of a data offload accelerator. A command to initiate capture of data from a plurality of remote chips is received into an offload control device of a data offload accelerator. Data from multiple remote chips is captured in parallel into a data buffer bank of a data offload accelerator, and the processor is interrupted via an offload control device to pass at least a portion of the data to the processor.

Description

Data offload acceleration from multiple remote chips

Background technique

Application-specific integrated circuit (ASIC) chips typically include sideband interface slave ports for device configuration, management, and runtime status and monitoring functions. The interface may be defined by a proprietary physical/logical protocol or an industry guideline such as Peripheral Component Interconnect Express (PCIe). A processor such as a microprocessor or baseboard management controller (BMC) can initiate transactions through this sideband ASIC interface to access and manipulate addressable devices such as control and status registers (CSRs) and memory-mapped data structures in the ASIC .

Description of drawings

Features of the present disclosure are shown by way of example, and not limitation, in the following drawings, in which like numerals refer to like elements, and in the drawings:

1 depicts a system architecture within which a data offload accelerator for offloading data from multiple remote chips to a processor may be implemented in accordance with one or more examples of the present disclosure;

2 depicts a system architecture within which a data offload accelerator for offloading data from a plurality of remote chips to a processor may be implemented in accordance with one or more examples of the present disclosure;

3 depicts a system architecture within which a data offload accelerator for offloading data from a plurality of remote chips to a processor may be implemented in accordance with one or more examples of the present disclosure;

4 depicts a system architecture within which a data offload accelerator for offloading data from a plurality of remote chips to a processor may be implemented in accordance with one or more examples of the present disclosure;

5 depicts a system architecture within which a data offload accelerator for offloading data from a plurality of remote chips to a processor may be implemented in accordance with one or more examples of the present disclosure;

6 depicts a system architecture within which an initialization accelerator for launching a plurality of remote chips may be implemented, according to one or more examples of the present disclosure;

7 depicts a system architecture within which a data offload accelerator for offloading data from a plurality of remote chips to a processor may be implemented in accordance with one or more examples of the present disclosure;

8 depicts a flowchart of a method for offloading data from a plurality of remote chips to a processor in accordance with one or more examples of the present disclosure; and

9 depicts a flow diagram of another method for offloading data from multiple remote chips to a processor in accordance with one or more examples of the present disclosure.

Detailed ways

A data collection solution, such as that used to collect telemetry, implements a loop in the BMC firmware that reads one CSR or memory-mapped data element across one to several BMC-to-ASIC management communication interfaces at a time . In order for the BMC to perform the retrieval of a single CSR, the firmware is designed to set the request, start the transaction and retrieve the data from the hardware when notified. During setup, the firmware formats the transaction and performs multiple separate writes to the hardware to prepare it for execution. The firmware then initiates the request with another hardware write. Once the hardware completes the transaction, the firmware is notified of the completion status via an asynchronous hardware interrupt and any response data is available. Finally, the firmware performs multiple individual reads of the hardware to retrieve the return data. To collect the entire data set, this process is performed in a loop that individually requests each CSR or memory-mapped data element. This serialization process is considered slow due to the overhead (software, operating system, firmware, drivers, storage resources, etc.) involved in initiating requests sequentially and servicing each response.

This configuration is sufficient if the BMC has local access to the ASIC and can maintain the expected performance (bandwidth, latency, sustained vs burst, etc.) as dictated by the high level requirements of the system. However, this configuration does not address performance expectations for some system topologies.

A system and method related to data offload acceleration, such as for a one-to-many BMC-ASIC interface topology, is disclosed. A hardware data offload accelerator, eg, within an integrated circuit (IC) such as a Field Programmable Gate Array (FPGA) or ASIC, reads, stores and transfers data, such as telemetry data, from multiple chips, eg multiple ASICs, each ASIC There are multiple chiplets with similar addressable memory and CSR structures. The data offload accelerator offloads the data to processors remote from multiple chips, such as the BMC. As used herein, "offloading" data means sending or transferring data between one or more processors and one or more chips. The data offload accelerator includes a set of registers that allows the processor to control the data offload, one or more address buffers, and one or more data buffers to implement data offload. The processor may specify a remote memory address, such as a CSR address or other mapped memory address location, for offloading. The processor may specify these addresses in one or more address buffers. The processor may specify non-contiguous addresses at any independent location within the predefined address space of the accelerator-attached ASIC.

In one example, the data offload accelerator includes "fast" and "slow" address buffers (and corresponding "fast" and "slow" data buffers). For example "fast" means that data is offloaded to the processor at some relatively fast refresh rate (eg 100Hz). And "slow" means that data, which may be a larger set of data than the former, is offloaded to the processor at a relatively slow refresh rate (eg, 1 Hz). After one or more address buffers have been initialized, the processor can initiate data capture by writing a single write to the registers within the data offload accelerator. When the data offload accelerator observes that its "start" bit is valid, it will issue a chip read for each of the specified addresses. These reads can be performed in parallel across multiple chip interfaces. As each chip responds, the data offload accelerator fills the appropriate data buffers in parallel with the associated response data. After storing some or all of the response data, the data offload accelerator will interrupt the processor. The processor then retrieves the stored data from the data offload accelerator.

Example benefits include improved speed of data collection from multiple chips, as reading and writing of data from chips, and particularly multiple CSRs within, for example, tens or hundreds of chips, can be performed in parallel. Additionally, speed is improved by significantly reducing transaction overhead. That is, a single write by the processor to the data offload accelerator can replace the overhead (software, OS, firmware, drivers, storage resources, etc.) involved in the processor initiating a request to each CSR and servicing each response. This triggers the data offload accelerator to issue multiple read requests in hardware in parallel and save the responses into the appropriate response data buffers in parallel.

In a particular example, a data offload accelerator offloads large amounts of telemetry data from multiple chips within multiple remote ICs. For example, each of the chips within each remote IC may contain hundreds or thousands of CSRs (or other memory-mapped locations) from which telemetry data can be offloaded. In this example, when the processor issues a single write command, the data offload accelerator may issue multiple read requests to multiple chips in parallel to retrieve the first multiple data responses in parallel from the first multiple specified addresses, and storing the first plurality of data responses in one or more data buffers in parallel. The data offload accelerator can optimize the ordering request size of these read requests to increase the efficiency of data transfer over the IC interface. For example, if the data offload accelerator identifies blocks of contiguous memory in a processor-defined address buffer, it can group discrete addresses into a single read request, where the transactional read response is sized to cover multiple blocks contained in the contiguous range. discrete addresses. Additionally, the data offload accelerator can sort the address buffer contents to facilitate such spatial locality optimizations. Without receiving additional commands from the processor or incurring additional overhead, the data offload accelerator can repeat the parallel capture of data (including issuing another multiple read requests to the chip in parallel, receiving from another multiple specified addresses in parallel another multiple data responses, and store multiple data responses in parallel to one or more data buffers) until data from all specified addresses has been captured. Thus, in the case of data offload accelerators offloading large amounts of remote data (such as telemetry), significant overhead savings can be achieved.

Turning now to the drawings, FIG. 1 depicts a system architecture 100 in which a data offload accelerator 112 may be implemented for transferring data from a plurality of ICs 106-1 to 106- of the system architecture 100 in accordance with one or more examples of the present disclosure. Multiple remote chips 1 through M in N are offloaded to processor 102 . In this case, M and N are integers whose values depend on the design of the system architecture 100 . The integers M or N may be the same or different.

The system architecture 100 also includes a data offload accelerator device 104 that includes a data offload accelerator 112 and is coupled to the processor 102 and the plurality of chips 1 through M of the plurality of ICs 106-1 through 106-N. Chips 1 through M are "remote" from processor 102 and data offload accelerator device 104 , meaning that chips 1 through M are at least included on a different chipset or die than processor 102 and data offload accelerator device 104 . In a particular example, ICs 106-1 through 106-N, each including "remote" chips 1 through M, are formed on a different semiconductor than the one or more semiconductor substrates on which processor 102 and data offload accelerator device 104 are formed on the substrate.

In one example, the processor 102 is a baseboard management controller (BMC). In another example, the processor 102 is a microprocessor. In another example, system architecture 100 may include multiple processors. For example, system architecture 100 may include processor 130 to which data offload accelerator 112 may also offload data from multiple chips 1 through M within multiple ICs 106-1 through 106-N. In yet another example, the system architecture 100 may include a plurality of data offload accelerator devices 104 mounted on one or more printed circuit assemblies coupled to one or more processors.

As shown, each of ICs 106-1 through 106-N is an ASIC; therefore, ICs 106-1 through 106-N are also labeled in Figure 1 (and Figures 2-6), and are used herein Called ASICs 1 to N. ASICs 1 through N may have very large scale integration (VLSI) designs. For example, ASICs 1-N may each have multiple chiplets 1-M (as shown), and may be fabricated using Silicon Stacked Interconnect (SSI) or other three-dimensional IC design techniques, where multiple ASIC dies are embedded in in a single substrate or IC package. As further shown, chiplets 1 through M each include one or more addressable CSRs, each of which is a 64-bit register in one example. Although only two are shown, the N ASICs may include more than two ASICs. Although only two are shown, the M chiplets may include more than two chiplets. In another example, system architecture 100 may include a single ASIC with chiplets 1-M. In another example, system architecture 100 may include ASICs 1 through N each having a single chiplet.

In an example, the data offload accelerator 112 is used to offload telemetry data from the CSR to the processor 102 . In certain examples, ASICs 1 through N at least partially form a switched fabric network, and processor 102 may monitor telemetry data from the CSR for certain conditions. For example, the processor 102 can monitor telemetry data so that responsive or corrective action can be taken to prevent unwanted problems within the switched fabric network.

The data offload accelerator device 104 is a hardware device with various hardware components, as described below. In one example, the data offload accelerator device 104 is an IC. For example, the data offload accelerator device 104 is an FPGA. Alternatively, the data offload accelerator device 104 is an ASIC. An example benefit of implementing the data offload accelerator device 104 as an FPGA is improved flexibility in design, as it can be appropriately programmed, eg, in the field or in the factory. Another example benefit of implementing the data offload accelerator device 104 as an FPGA is that the data offload accelerator algorithm used therein can be optimized and/or changed based on user requirements or hardware changes within the system architecture 100 .

The data offload accelerator device 104 also includes an interface bridge 110 that couples the processor 102 to the data offload accelerator 112 . Data offload accelerator device 104 also includes interfaces 122, 124-1 through 124-N, and 126-1 through 126-N, which couple data offload accelerator 112 to chiplets 1 through M within ASICs 1 through N. Where there are multiple processors within system architecture 100 , such as processors 102 and 130 , interface bridge 110 may connect all processors to data offload accelerator 112 .

Interface bridge 110 may include any suitable interface, such as an interface that enables serial transfer of data between data offload accelerator 112 and processor 102 . The interface within interface bridge 110 may further allow for the transfer of commands (or requests) and interrupts or any other suitable messaging or information between processor 102 and data offload accelerator 112 . An example interface bridge 110 includes a PCIe industrial interface. Where there are multiple processors (eg, processors 102 and 130 ) within system architecture 100 , interface bridge 110 may include multiple PCIe interfaces, where each PCIe interface is coupled to one of the processors and data offload accelerator 112 . Alternatively, interface bridge 110 may include a PCIe switch coupled to each processor and data offload accelerator 112 .

In one example, interfaces 122, 124-1 through 124-N, and 126-1 through 126-N allow transaction-based communication between data offload accelerator 112 and chiplets 1 through M of ASICs 1 through N. Transaction-based communications or "transactions" may include, for example, requests to configure (eg, during initialization or at some subsequent time) and memory reads and writes, as well as responses to requests, eg, data, such as telemetry data. As shown, interfaces 124-1 through 124-N are connected between interface 122 and chiplets 1 through M of ASIC 1, respectively. Similarly, interfaces 126-1 through 126-N connect between interface 122 and chiplets 1 through M of ASIC N, respectively, to access one or more CSRs within the chiplets.

As further shown, interfaces 124-1 to 124-N and 126-1 to 126-N each include physical, link, and protocol (higher) layers. Additionally, as shown, interface 122 serves as a protocol layer interface between data offload accelerator 112 and interfaces 124-1 through 124-N and 126-1 through 126-N. In one example, interface 122 includes transaction buffers and routers. In a particular example, interfaces 124-1 through 124-N and 126-1 through 126-N are each proprietary interfaces, and interface 122 includes multiple transaction first-in-first-out (FIFO) routers. In this example, data offload accelerator device 104 may function as a protocol bridge between processor 102 and chiplets 1-M if interface bridge 110 includes PCIe, for example. Alternatively, interfaces 124-1 through 124-N and 126-1 through 126-N are PCIe interfaces, and interface 122 includes multiple PCIe transaction FIFO routers.

This example arrangement of interfaces 122, 124-1 to 124-N, and 126-1 to 126-N enables parallel transfer of transactions (eg, requests) from data offload accelerator 112 to chiplets 1 to M of ASICs 1 to N. Likewise, this example arrangement of interfaces 122, 124-1 to 124-N, and 126-1 to 126-N enables transactions (eg, responses to requests) from ASICs 1 to N chiplets 1 to M to data offload accelerators 112 parallel transfers. For example, after processor 102 receives a single write command, data offload accelerator 112 may send read requests in parallel to chiplets 1 through M in ASICs 1-N, with one read request at interfaces 124-1 through 124- N and are transmitted on each of interfaces 126-1 through 126-N. Additionally, in response to read requests, chiplets 1 through M within ASICs 1 through N may send data responses to the data offload accelerators in parallel, with one data response at interfaces 124-1 through 124-N and interfaces 126-1 through 126 -N are sent on each of them.

The data offload accelerator 112 includes an offload control device 114, an address buffer bank with a single address buffer 116, a response data buffer bank with a single response data buffer 120, and FSM transaction (TXN) processing logic 118 (referred to herein as as transaction logic). In the example shown, address buffer 116 is implemented as block random access memory (BRAM), but may be implemented using any suitable memory technology to store multiple addresses. Address buffer 116 is coupled to processor 102, eg, via a BRAM interface (I/F). Address buffer 116 is also coupled to transaction logic 118, eg, using a hardware connection. More specifically, the processor 102 may specify an address in the address buffer 116, such as an address of a CSR, to access one or more of the chips 106-1 through 106-N and from the address in the chips 106-1 through 106-N. One or more retrieved data. In one example, the addresses are linear or sequential. In this example, the processor 102 may indicate the starting address and address range in the address buffer 116 . Alternatively, these addresses may be non-linear or heterogeneous, non-discrete addresses, which may provide greater flexibility than using linear addresses. In this alternative example, address buffer 116 may implement a list feature that allows processor 102 to write a list of non-linear addresses to address buffer 116 .

In the example shown, the response data buffer 120 is implemented as a BRAM, but may be implemented using any suitable memory technology to store multiple addresses. Response data buffer 120 is coupled to processor 102, eg, via BRAM I/F. Response data buffer 120 is also coupled to transaction logic 118 . Transaction logic 118 may forward the data it retrieves from chips 106-1 through 106-N to response data buffer 120 in parallel. Parallel lines between transaction logic (eg, 118 ) and one or more data buffers (eg, 120 ) represent multiple hardware connections to enable parallel forwarding of information (including data responses) from chiplets 1 through M, In some examples, transactions are sent to chiplets 1 through M to initialize the CSR. As shown, the data response buffer 120 is a monolithic buffer. Alternatively, and as described with respect to one or more of the example data offload accelerators disclosed herein, the response data buffer library may include multiple data buffers, such as multiple sets of data buffers, where each set has multiple data buffer.

Offload control device 114 is coupled to both processor 102 and transaction logic 118 . Offload control device 114 may include any suitable circuitry that enables: processor 102 to provide status indications (eg, commands or other inputs) to control the functions of data offload accelerator 112 to retrieve data from chiplets 1 through M; transaction logic 118 provide one or more status indications as a result of requesting, receiving, storing and/or processing data from chiplets 1 through M; and processor 102 reads one or more status indications from data offload accelerator 112, such as by a transaction One or more status indications provided by logic 118 are processed.

The offload control device 114 includes a plurality of status indicator circuits, such as one or more bit registers, that enable different status indications. As shown, the offload control device 114 includes accelerator (Accel) ready, start, in progress (InProg), data available (DataAvail), error, address (Addr) control (Cnt), buffer offset/size, and performance Counter (Cntrs) status indicator circuit. For example, the offload control device 114 may have more or less status indicator circuits depending on the information indicated by the processor 102 and the data offload accelerator 112 .

The accelerator ready status indicator circuit enables data offload accelerator 112 to indicate to processor 102 that it is ready. For example, the accelerator ready status indicator circuit enables the data offload accelerator 112 to indicate that it has come out of reset and that all links to chiplets 1 through M have been initialized. The start status indicator circuit enables the processor 102 to indicate to the data offload accelerator 112 to begin processing the address specified in the address buffer 116 . The processor 102 may issue a single write command to initiate data capture from the chiplets 1-M of one or more of the ASICs 1-N, eg, using the start status indicator circuit. Data capture or capturing data includes receiving data from a remote chip and storing that data. In one example, data capture includes sending a data request, receiving a data response including the data, and forwarding the data to one or more response data buffers. The in-progress status indicator circuit enables transaction logic 118 to indicate to processor 102 that a data fetch from the address indicated in address buffer 116 is in progress. The data availability status indicator circuit enables the transport processing logic 118 to indicate to the processor 102 that data is available for offloading. For example, the data availability status indicator circuit enables the data offload accelerator 112 to interrupt the processor 102 to offload at least a portion of the retrieved data to the processor 102 . Error status indicator circuitry enables transaction logic 118 to indicate to processor 102 various errors that may occur. Example errors include, for example, a read timeout or the connection to the ASIC was interrupted in the transaction. The address control status indicator circuit enables processor 102 to indicate to transaction logic 118 how many addresses are indicated in address buffer 116 . The buffer offset/size status indicator circuit enables transaction logic 118 to indicate to processor 102 where the retrieved data is located within response data buffer 120 . The buffer offset/size status indicator circuit also enables the data offload accelerator 112 to indicate to the processor 102 the size of the address buffer 116 and/or the response data buffer 120 . The performance counter status indicator circuit enables transaction logic 118 to indicate to processor 102 various parametric data indicative of performance, such as how long it took to retrieve and store data.

Transaction logic 118 may be coupled to interface 122 to process transactions between data offload accelerator 112 and chiplets 1-M of ASICs 1-N. In a particular example, the transaction processing logic 118 is implemented in hardware as a finite state machine (FSM) to perform various functions. For example, transaction logic 118: reads addresses from address buffer 116; constructs read requests in a format suitable for interfaces 122, 124-1 to 124-N and 126-1 to 126-N, and chiplets 1 to M and sends A read request is sent to those addresses; data is received in response to the read request; the data is stored in an appropriate response data buffer, in this example the response data buffer 120 . Transaction logic 118 may also handle errors and provide status indications, eg, as described above. In other examples, transaction logic 118 may perform other functions, such as comparing the retrieved data to one or more criteria, and performing actions based on the comparison. In another example, transaction logic 118 may send requests to read to at least some of the plurality of addresses specified in address buffer 116 in parallel. Transaction logic 118 may also receive data from multiple addresses in parallel.

2 depicts a system architecture 200 in which a data offload accelerator 212 may be implemented for transferring data from ASICs 1 to N of multiple remote chiplets of the system architecture 200 in accordance with one or more examples of the present disclosure 1 to M are offloaded to processor 102 . The system architecture 200 also includes a data offload accelerator device 204 that includes a data offload accelerator 212 and that is coupled to both the processor 102 and the plurality of chiplets 1 to M of the ASICs 1 to N . The processor 102 and ASICs 1 to N may be implemented similarly as described above with reference to FIG. 1 . Additionally, system architecture 200 may include multiple processors.

The data offload accelerator device 204 includes an interface bridge 110 , which may be implemented similarly as described above with reference to FIG. 1 and similarly coupled to the processor 102 . As described above with reference to FIG. 1, data offload accelerator device 204 also includes interfaces 122, 124-1 to 124-N and 126-1 to 126-N, interfaces 122, 124-1 to 124-N and 126-1 to 126-N N can be similarly implemented and similarly coupled to chiplets 1-M of ASICs 1-N.

Data offload accelerator 212 is shown coupled to both interface bridge 110 and interface 122 . As shown, the data offload accelerator 212 includes: a plurality of accelerator registers 214; and an address buffer bank, which includes a slow address buffer 208 and a fast address buffer 202; and a data buffer bank, which includes a plurality of slow responses a data buffer 210, a plurality of fast response data buffers 216, and a plurality of fast response data buffers 206; and transaction logic 218. Transaction logic 218 may be implemented in hardware as a finite state machine and coupled to interface 122, accelerator registers 214, slow address buffer 208 and fast address buffer 202 and a plurality of slow response data buffers 210, a plurality of A fast response data buffer 206 and a plurality of fast response data buffers 216 .

Slow address buffer 208 and fast address buffer 202 and each data buffer within plurality of slow response data buffers 210, plurality of fast response data buffers 206, and plurality of fast response data buffers 216 are shown as The BRAM with BRAM I/F is used to couple the data buffer to the processor 102, but may be implemented as any suitable storage device. Transaction logic 218 may function similarly to transaction logic 118 described with reference to FIG. 1 . However, transaction logic 218 may read addresses from multiple, eg, "slow" and "fast" address buffers 208 and 202, respectively, rather than from a single address buffer. Additionally, transaction logic 218 may write to multiple (eg, "slow" and "fast") response data buffers 210 and 206, 216 in parallel, respectively, rather than writing to a single response data buffer.

As shown, the accelerator registers 214 include accelerator ready, slow/fast start, slow/fast in progress, slow/fast data available, slow/fast error, slow/fast address control, buffer offset/ Size and performance counter status registers, which may be similar to the acceleration ready, start, in progress, data available, error, address control, buffer offset/size, and performance counter status indicators of the offload control device 114 described above with reference to FIG. 1 circuit works. However, instead of a single address buffer, the accelerator registers 214 are capable of implementing indications for multiple, eg, "slow" and "fast" address buffers 208 and 202, respectively. Furthermore, the accelerator registers 214 can enable indications for multiple, eg, "slow" and "fast" response data buffers 210 and 206, 216, respectively, rather than for a single response data buffer.

Using the data offload accelerator 212, the processor 102 may indicate an address, such as an address of a CSR, in both the slow address buffer 208 and the fast address buffer 202 to access chiplet 1 of one or more of ASICs 1 through N to M and retrieve data from chiplets 1 to M of one or more of ASICs 1 to N. Transaction logic 218 reads addresses from address buffers 202 and 208; constructs read requests and sends read requests to these addresses; receives data in response to the read requests; Forwards the data it retrieves from chiplets 1 through M of ASICs 1 through N.

As shown, data offload accelerator 212 includes buffers of different performance classes or priorities, in this case "fast" buffers (eg, 202, 206, and 216) and "slow" buffers (eg, 208 and 216). 210) Enable data to be offloaded to the processor 102 at different rates. In one example, a "fast" buffer enables certain data to be retrieved and unloaded at a faster rate (eg, 100 times) than a "slow" buffer. In this example, there are two performance classes or priority buffers. However, there may be additional performance categories or priorities for buffers based on data collection specifications, eg based on expected result quality or specific CSR segmentation. For example, multiple performance classes or priorities may indicate different data refresh rates, different bandwidths of data captured by data offload accelerator 212 and/or passed to processor 102, data captured by data offload accelerator 212 and/or passed to processing different rates of the device 102, etc. In a particular example, each performance class or priority is associated with its own separate address buffer and response data buffer.

Additionally, slow address buffer 208, fast address buffer 202, multiple slow response data buffers 210, multiple fast response data buffers 206 and multiple fast response data buffers 216 may have different the size of. In one example, the amount of data captured at the faster rate is less than the amount of data captured at the slower rate. Therefore, the fast address buffer 202 may be smaller than the slow address buffer 208 to store fewer addresses. Likewise, the number of fast response data buffers 206 and the number of fast response data buffers 216 may be smaller than the number of slow response data buffers 210 to store less data. In certain examples, transaction logic 218 may perform an arbitration scheme to determine how often multiple fast response data buffers 206 and 216 are filled relative to multiple slow response data buffers 210 .

Another feature of data offload accelerator 212 is the use of multiple sets of fast response data buffers (eg, 206 and 216). For example, data offload accelerator 212 may send requests to chips 106-1 through 106-N to retrieve data in parallel, and may fill a given response data buffer with data in parallel. However, the processor 102 may serially read data from the filled response data buffer. Therefore, offloading the data to the processor 102 may take many times longer than capturing and writing the data. In this case, the use of multiple fast response data buffers can support higher speeds. For example, when the processor 102 reads data from the FastA response data buffer 216 , the transaction processing logic 218 may collect the data and populate the FastB response data buffer 206 . Similarly, when processor 102 reads data from FastB response data buffer 206 , transaction logic 218 may collect the data and populate FastA response data buffer 216 . In another example, the data offload accelerator 212 includes additional fast-response data buffers, the number of which may depend, at least in part, on the relative speed at which the transaction logic 218 captures and populates the data to the processor 102 that reads the data.

3 depicts a system architecture 300 within which a data offload accelerator 312 may be implemented for transferring data from a plurality of remote small ASICs 1 to N of the system architecture 300 in accordance with one or more examples of the present disclosure. Chips 1 to M are offloaded to processor 102 . The system architecture 300 also includes a data offload accelerator device 304 that includes a data offload accelerator 312, and the data offload accelerator device 304 is coupled to the processor 102 and to the plurality of chiplets 1 to M of the ASICs 1 to N. By. The processor 102 and the ASICs 1 to N may be implemented similarly as described above with reference to FIG. 1 . Additionally, system architecture 300 may include multiple processors.

As described above with reference to FIG. 1 , data offload accelerator device 304 includes interface bridge 110 , which may be similarly implemented and similarly coupled to processor 102 . As described above with reference to FIG. 1, data offload accelerator device 304 also includes interfaces 122, 124-1 to 124-N and 126-1 to 126-N, interfaces 122, 124-1 to 124-N and 126-1 to 126-N N can be similarly implemented and similarly coupled to chiplets 1-M of ASICs 1-N.

Data offload accelerator 312 is shown coupled to both interface bridge 110 and interface 122 . As shown, the data offload accelerator 312 includes: a plurality of accelerator registers 314; an address buffer bank, which includes the address buffer 302; a data buffer bank, which includes a plurality of response data buffers 310; transaction logic 318; and marker circuit 306; and marker circuit 308. Transaction logic 318 may be implemented in hardware as a finite state machine and coupled to interface 122 , accelerator registers 314 , address buffer 302 , multiple response data buffers 310 , comparator circuit 306 , and action circuit 308 .

Address buffer 302 and each data buffer in plurality of response data buffers 310 are shown as having a BRAM with a BRAM I/F for coupling the data buffer to processor 102, but any suitable storage technique may be used to fulfill. Transaction logic 318 may function similarly to transaction logic 118 described with reference to FIG. 1 . However, rather than writing to a single response data buffer, transaction logic 318 may write to multiple response data buffers 310 in parallel. Additionally, in the example shown, the transaction logic 318 also provides input to the comparator circuit 306 and provides an indication based on the result of the action circuit 308 .

As shown, accelerator registers 314 include accelerator ready, start, in progress, data available, error, address control, buffer offset/size, and performance counter status registers, which are similar to offload control as described above with reference to FIG. 1 The accelerator ready, starting, in progress, data available, error, address control, buffer offset/size, and performance counter status indicator circuits of device 114 function. Accelerator registers 314 also include address/data (A/D) first-in, first-out (FIFO) control (Cnt)/status registers that enable transaction logic 318 to provide one or more states to processor 102 based on the results of action circuit 308 instruct. Furthermore, the accelerator register 314 can enable indication of multiple response data buffers 310 rather than a single response data buffer.

In an example case, the data from chiplets 1-M of ASICs 1-N may not change frequently. Therefore, to further improve efficiency, once transaction logic 318 writes data to response data buffer 310 for the first time (eg, data set n-1), transaction logic 318 updates the response data buffer 310 when there is a change data, and the changed data may be flagged and passed to the processor 102 instead of passing the complete data set. Comparator circuit 306 and marker circuit 308 enable this feature. In an example, tag circuit 308 is implemented as a set of "tag address/data FIFO" registers.

As shown, the comparator circuit 306 implements the comparison function using, for example, a combinational logic circuit. In one example, when transaction logic 318 retrieves data set-n, it may provide each data point (value) in data set-n to comparator circuit 306. The compare function may then compare each data point in data set n with the corresponding data point in data set n-1 for a given address location of response data buffer 310. When the compare function outputs a difference to the tag circuit 308, the tag circuit 308 may store the difference and/or the actual data value as the "tag value" and also store the corresponding address location of the response data buffer 310 as the "tag address" in mark the address/data FIFO register. In an example, the contents of the tag address/data FIFO registers of tag circuit 308 are accessible by processor 102 . In a particular example, the data offload accelerator 312 uses the A/D FIFO control/status register to provide the processor 102 with an indication that the content is available for transfer from the tag address/data FIFO register.

Thus, only a portion of the data, such as the tag data value at a given address location and/or the tag difference between the data set n value and the data set n-1 value, is offloaded to the processor 102, rather than the entire data set-n and data set n-1. This speeds up the data read by the processor 102, which can be important, for example, where there are thousands of CSRs from which data is to be read. Furthermore, the data offload accelerator 312 can monitor in its hardware for significant changes to the data. This monitoring may be performed more efficiently than if the data were first passed to the processor 102 to perform the comparison function.

4 depicts a system architecture 400 in which a data offload accelerator 412 may be implemented to offload data from ASICs 1 to N of multiple remote chiplets 1 of the system architecture 400 in accordance with one or more examples of the present disclosure To M is offloaded to processor 102 . The system architecture 400 also includes a data offload accelerator device 404 that includes a data offload accelerator 412 and is coupled to the processor 102 and the plurality of chiplets 1 to M of the ASICs 1 to N. The processor 102 and ASICs 1 to N may be implemented similarly as described above with reference to FIG. 1 . Additionally, system architecture 400 may include multiple processors.

The data offload accelerator device 404 includes an interface bridge 110 that may be similarly implemented and similarly coupled to the processor 102 as described above with reference to FIG. 1 . As described above with reference to FIG. 1, data offload accelerator device 404 also includes interfaces 122, 124-1 through 124-N, and 126-1 through 126-N, which may be similarly implemented and similarly coupled to ASICs 1 through N Chiplets 1 to M.

Data offload accelerator 412 is shown coupled to both interface bridge 110 and interface 122 . As shown, data offload accelerator 412 includes: a plurality of accelerator registers 414; a plurality of address buffer banks, including address buffers 402; a data buffer bank, including a plurality of response data buffers 410; transaction logic 418 ; comparator circuit 406 ; and flag circuit 408 . Transaction logic 418 may be implemented in hardware as a finite state machine and coupled to interface 122 , accelerator registers 414 , address buffer 402 , multiple response data buffers 410 , comparator circuit 406 and flag circuit 408 .

Each data buffer within address buffer 402 and plurality of response data buffers 410 is shown as having a BRAM with a BRAM I/F for coupling the data buffer to processor 102, but may be implemented as any suitable memory technology. The marker circuit 408 may function similarly to the marker circuit 308 described with reference to FIG. 3 . Transaction logic 418 may function similarly to transaction logic 118 described with reference to FIG. 1 . However, transaction logic 418 may write to multiple response data buffers 410 in parallel rather than a single response data buffer. Furthermore, in the example shown, transaction logic 418 also provides an indication based on the results of action circuit 408 .

As shown, accelerator registers 414 include accelerator ready, start, in progress, data available, error, address control, buffer offset/size, and performance counter status registers, which are similar to the offload control device as described above with reference to FIG. 1 The accelerator ready, starting, in progress, data available, error, address control, buffer offset/size and performance counter status indicator circuits of 114 function. Accelerator registers 414 also include A/D FIFO control/status registers, which enable transaction logic 418 to provide one or more status indications to processor 102 based on the results of flag circuit 408 . Furthermore, the accelerator register 414 enables indication of multiple response data buffers 410 rather than a single response data buffer.

In another example scenario, the comparison and monitoring functions of the example of FIG. 4 may be more complex than those described with reference to FIG. 3 . For example, comparator circuit 406 may include a plurality of data set criteria and pattern match registers, which allow data retrieved from chiplets 1 through M of one or more of ASICs 1 through N to be compared to one or more criteria. In one example, the processor 102 programs one or more criteria into the data set criteria and pattern match registers of the comparator circuit 406, to which the retrieved data is compared. As shown, the processor 102 may program criteria including, but not limited to, bit range fields, pattern match types, and pattern match values. The bit range field may indicate, for example, the bit range of interest from the CSR for comparison. The pattern match type can indicate the type of comparison to perform, such as equals, greater than, less than. A pattern match value may indicate one or more values to which the retrieved data is compared using the pattern match type. In one example, the comparator circuit 406 may monitor certain conditions of interest based on defined telemetry response targets.

If one or more (pattern matching) criteria are met, the tag circuit 408 may store a "tag value", such as the value of the data or some other value related to the data, and also the corresponding address location of the response data buffer 410 as The "tag address" is stored in the tag address/data FIFO register. In an example, the contents of the tag address/data FIFO registers of tag circuit 408 are accessible by processor 102 . In a particular example, the data offload accelerator 412 uses the A/D FIFO control/status register to provide the processor 102 with an indication that content is available for offloading from the marked address/data FIFO register. Accordingly, only a portion of the data, such as the tagged data values and/or other values associated with the data value at a given address location, is offloaded to the processor 102, rather than the entire data set-n and data set n-1.

5 depicts a system architecture 500 in which a data offload accelerator 512 may be implemented for transferring data from ASICs 1 to N of multiple remote chiplets of the system architecture 500 in accordance with one or more examples of the present disclosure 1 to M are offloaded to processor 102 . The system architecture 500 also includes a data offload accelerator device 504 that includes a data offload accelerator 512 and is coupled to the processor 102 and the plurality of chiplets 1 to M of the ASICs 1 to N. The processor 102 and the ASICs 1 to N may be implemented similarly as described above with reference to FIG. 1 . Additionally, system architecture 500 may include multiple processors.

The data offload accelerator device 504 includes an interface bridge 110 that may be implemented similarly as described above with reference to FIG. 1 and similarly coupled to the processor 102 . The data offload accelerator device 404 also includes interfaces 122, 124-1 to 124-N, and 126-1 to 126-N, which may be implemented similarly as described above with reference to FIG. 1 and similarly coupled to the ASICs 1 to N. Chiplets 1 to M.

Data offload accelerator 512 is shown coupled to both interface bridge 110 and interface 122 . As shown, the data offload accelerator 512 includes: a plurality of accelerator registers 514; and an address buffer bank, which includes an address buffer 502; a data buffer bank, which includes a plurality of response data buffers 510; transaction logic 518; a comparator circuit 506; and an action circuit 508. Transaction logic 518 may be implemented in hardware as a finite state machine and coupled to interface 122 , accelerator registers 514 , address buffer 502 , multiple response data buffers 510 , comparator circuit 506 , and action circuit 508 .

Each data buffer within address buffer 402 and plurality of response data buffers 410 is shown as a BRAM with a BRAM I/F for coupling the data buffer to processor 102, but may be implemented as any suitable memory technology. Transaction logic 518 may function similarly to transaction logic 118 described with reference to FIG. 1 . However, transaction processing logic 518 may write to multiple response data buffers 510 in parallel rather than a single response data buffer. Furthermore, in the example shown, the transaction logic 518 also provides an indication based on the results of the action circuit 508 .

As shown, the accelerator registers 514 include accelerator ready, start, in progress, data available, error, address control, buffer offset/size, and performance counter status registers, which are similar to the offload control device as described above with reference to FIG. 1 The accelerator ready, starting, in progress, data available, error, address control, buffer offset/size and performance counter status indicator circuits of 114 function. Accelerator registers 514 also include a criterion/action CSR status register, which enables transaction logic 518 to provide one or more status indications to processor 102 based on the results of flag circuit 508 . Furthermore, the accelerator register 514 enables indication of multiple response data buffers 510 rather than a single response data buffer.

In another example scenario, the comparison and monitoring functions of the example of FIG. 5 may be more complex than those described with reference to FIG. 3 . For example, comparator circuit 406 may include a plurality of data set criteria and pattern match registers that allow data retrieved from chiplets 1 through M of one or more of ASICs 1 through N to be compared to one or more criteria. In one example, the processor 102 programs one or more criteria into the data set criteria and pattern match registers of the comparator circuit 506, to which the retrieved data is compared. As shown, the processor 102 may program criteria including, but not limited to, bit range fields, pattern matching types, pattern matching values, and criteria categories. The bit range field, pattern match type and pattern match value registers may function similar to those described with reference to FIG. 4 . However, the Criterion Class Register includes additional criteria against which the retrieved data is compared. In one example, the standard category is used to determine whether the retrieved data value is from a CSR within the specified CSR category.

For example where ASICs 1 to N are formed or included in a switched network, the collected telemetry data can be processed to find or monitor specific performance signatures. When an abnormal signature is found, the data offload accelerator 512 can take action to recover from the condition while the switching network continues to operate. In this context, by way of non-limiting example, the data offload accelerator 512 may: seek conditions that indicate structural paths are no longer operational; characterize new silicon and new exchange paradigms; ports that do not pass it to the destination; identify "brick walls", i.e. ports that never accept data; etc.

If one or more criteria are met or a signature is found, in this example scenario, the action circuit 508 may take some action, such as some corrective action. For example, the action circuit 508 may take one or more actions within the response data buffer 510 for the chiplet, particularly for a CSR within the chiplet, or the like. As shown, the action circuit 508 includes a plurality of accelerated action response registers, including action class, action type, action range, action state, and action performance (Perf.) counter registers, which provide responses to satisfying one or more criteria And the flexibility of the actions that the action circuit can take. These actions can be delineated by the class, type, and scope in the corresponding registers. An indication of the action taken and the result or other status related to the action taken may be recorded in an action status register. Also, any performance metrics associated with actions can be stored in action performance counter registers. Such actions may include, but are not limited to, writing specific values to addresses in the CSR or response data buffer 510, changing the routing table for the CSR to avoid black hole or brick wall network routing conditions, and the like.

In an example, the processor 120 may access the contents of an accelerated action response register of the action circuit 508 . In a particular example, the data offload accelerator 512 uses the criteria/action CRS registers to provide the processor 102 with an indication that content can be viewed and passed from one or more action response registers of the action circuit 508 . In yet another example, the data in response data buffer 510 is also transferred to processor 102 . If all data from chiplets 1 to M of ASICs 1 to N must first be serially offloaded to processor 102 for analysis, then action circuit 508 can implement the action to be taken faster than the action to be taken to Resolve or mitigate conditions in the network.

6 depicts a system architecture 600 in which an initialization accelerator 612 may be implemented for initializing a plurality of remote chiplets 1 through M of ASICs 1 through N of the system architecture 600 in accordance with one or more examples of the present disclosure . System architecture 600 also includes initialization accelerator device 604, which includes initialization accelerator 612, and which is coupled to processor 102 and a plurality of chiplets 1-M of ASICs 1-N. The processor 102 and the ASICs 1 to N may be implemented similarly as described above with reference to FIG. 1 . Additionally, system architecture 600 may include multiple processors.

Initialization accelerator device 604 includes interface bridge 110 , which may be similarly implemented and similarly coupled to processor 102 as described above with reference to FIG. 1 . Initialization accelerator device 604 also includes interfaces 122, 124-1 to 124-N, and 126-1 to 126-N, which may be implemented similarly as described above with reference to FIG. Chips 1 to M.

Initialization accelerator 612 is shown coupled to both interface bridge 110 and interface 122 . As shown, the initialization accelerator 612 includes: a plurality of accelerator registers 614; an address buffer bank, which includes the address buffer 602; a data buffer bank, which includes a plurality of output data buffers 606; and transaction logic 618. Transaction logic 618 may be implemented in hardware as a finite state machine and coupled to interface 122 , accelerator registers 614 , address buffer 602 , and multiple output data buffers 606 .

As shown, the accelerator registers 614 include accelerator ready, start, in progress, data available, error, address control, buffer offset/size, and performance counter status registers, which are similar to the offload control device as described above with reference to FIG. 1 The accelerator ready, starting, in progress, data available, error, address control, buffer offset/size and performance counter status indicator circuits of 114 function. In addition, accelerator registers 614 can enable indications regarding multiple output data buffers 606 . In another example, the accelerator register 614 can enable indication of a single output data buffer.

Each data buffer within address buffer 602 and plurality of output data buffers 606 is illustrated as a BRAM with a BRAM I/F for coupling the data buffer to processor 102, but may be implemented as any suitable memory technology. Transaction logic 618 may function similarly to transaction logic 118 described with reference to FIG. 1 to retrieve and store data from chips 106-1 through 106-N. In this case, the outbound data buffer 606 would act as a response data buffer to store the retrieved data.

However, in some examples, transaction logic 618 writes initialization data from output data buffer 606 into chiplets 1 through M of one or more of ASICs 1 through N, eg, into chiplets 1 through M within chiplets 1 through M. CSR. Initialization data may be written in parallel on interfaces 122, 124-1 to 124-N, and 126-1 to 126-N. In an example, processor 102 may specify multiple addresses in address buffer 602 as part of initializing the chiplet. The processor 102 may correspondingly fill the outbound data buffer 106 with initialization data to initialize the chiplets at those addresses. Transfer processing logic 618 then writes the initialization data from outbound data buffer 606 to the chiplet at the stored address upon receiving an indication from processor 102, eg, using a start register within accelerator register 614. Thus, transaction logic 618 may perform simultaneous initialization of chiplets by using hardware to send write requests to chiplets in parallel. The initialization time can be greatly reduced compared to the processor 102 initializing each chiplet one at a time.

In another example, transaction logic 618 may write other types of data to chiplets 1-M of one or more of ASICs 1-N. For example, transaction logic may write configuration data to the chiplet at a later time than initialization to change the value within the CSR.

7 depicts a system architecture 700 within which a data offload accelerator 712 may be implemented for offloading data from a plurality of ICs 730-1 through 730-N of the system architecture 700 in accordance with one or more examples of the present disclosure The plurality of remote chips 1 to M are offloaded to the processor 102 . ICs 730-1 to 730-N are also referred to herein as ICs 1 to N. The system architecture 700 also includes a data offload accelerator device 704 that includes a data offload accelerator 712 and is coupled to both the processor 102 and the plurality of chips 106-1 through 106-N. Processor 102 and chips 1 through M may be any type of chip that includes memory-mapped address locations that contain data for offloading to processor 102 . Additionally, system architecture 700 may include multiple processors.

The data offload accelerator device 704 includes an interface bridge 110 , which may be implemented similarly as described above with reference to FIG. 1 and similarly coupled to the processor 102 . Data offload accelerator device 704 also includes interfaces 122, 124-1 to 124-N, and 126-1 to 126-N, which may be implemented similarly as described above with reference to FIG. 1 and similarly coupled to chips of IC1 to N 1 to M.

Data offload accelerator 712 is illustrated coupled to both interface bridge 110 and interface 122 . As shown, data offload accelerator 712 includes transaction processing logic 718 that is coupled to the remaining components of data offload accelerator 712 . Transaction logic 718 may include at least some of the functionality described above with reference to FIGS. 1 , 2 , 3 , 4 , and 6 . The data offload accelerator 712 also includes a plurality of accelerator registers 714 that may function similarly to the accelerator registers 114 described with reference to FIG. 1 . Data offload accelerator 712 also includes an address buffer bank with slow address buffer 708 and fast address buffer 702, which may function similarly to slow address buffer 208 and fast address buffer 202 described with reference to FIG. The data offload accelerator 712 also includes a data buffer bank with a plurality of slow response data buffers 710, a plurality of fast response data buffers 722, and a plurality of fast response data buffers 706, which are similar to the slow response data buffers described with reference to FIG. Response data buffer 210, fast response data buffer 216, and fast response data buffer 206 function. The data offload accelerator 712 further includes a comparator circuit 716 and an action circuit 720 , which may function similarly to the comparator circuit 406 and the action circuit 408 described with reference to FIG. 4 . In certain examples, the processor 102 may program the data offload accelerator to function in different modes to trigger various functions therein.

8 depicts a flowchart of a method 800 for offloading data from multiple remote chips to a processor in accordance with one or more examples of the present disclosure. The example method 800, or portions thereof, may be performed by the example data offload accelerators 112, 212, 312, 412, 512, 612, and 712 shown in FIGS. 1-7, respectively. By way of example, however, method 800 is described with reference to data offload accelerator 112 of FIG. 1 . According to example method 800, an indication of a plurality of addresses for retrieving data from a plurality of remote chiplets 1-M of one or more of ASICs 1-N is received (802) into an address buffer bank, the addresses The buffer bank in this case is the address buffer 116 . A command to initiate the offloading of data is received (804) into offload control device 114. Transaction logic 118 captures (806) the data in parallel to data buffer bank 120, in this case response data buffer 120. Once the response data buffer 120 is at least partially or completely filled with data, the transaction processing logic 118 interrupts (808) the processor 102 to transfer at least a portion of the data.

In one example, transaction logic 118 retrieves data based on one or more policies programmed within transaction logic 118 . In one example, transaction logic 118 retrieves data from some but not all of ACIS 1 through ACIS N. In another example, transaction logic 118 retrieves data from some but not all of chips 1-M from one or more of ASICs 1-N. In another example, transaction logic 118 retrieves data from some but not all of the CSRs within one or more of chips 1 through M in one or more of ASICs 1 through N. In another example, transaction logic 118 retrieves data of different sizes, eg, different sized bits or bytes of data. In another example, each transaction may retrieve data of different sizes.

9 depicts a flowchart of a method 900 for offloading data from multiple remote chips to a processor in accordance with one or more examples of the present disclosure. Example method 900, or portions thereof, may be performed by example data offload accelerators 112, 212, 312, 412, 512, 612, and 712 and example ASIC initialization accelerator 612, as shown in FIGS. 1-7. Illustratively, however, method 900 is described with reference to data offload accelerator 712 of FIG. 7 .

According to the example method 900, indications of multiple addresses for providing or retrieving data from multiple remote chips 1 through M in one or more of ICs 1 through N are received to multiple addresses of the address buffer bank buffers 702, 708. In particular, a first portion of the memory address is received (902) in a first address buffer, eg, fast address buffer 702, and a second portion of the memory address is received (904) in a second address buffer, eg, slow address buffer 710. Depending on the configuration of the data offload accelerator (eg, where data offload accelerator 612 is configured similar to FIG. 6), transaction logic 712 may initialize (906) one or more of ICs 1 through N in parallel at the indicated address. Multiple remote chips 1 to M in each IC. In one example, the response data buffer bank contains initialization data that transaction logic 718 may write to remote chips 1-M of one or more of ICs 1-N to initialize or configure a chip, such as IC 1 CSRs within chips 1 to M of one or more of N to N. In another example, the processor uses accelerator registers to trigger transaction logic 718 to initialize the CSR.

A command to initiate offloading of data is received (908) into the offload control device, in this case the accelerator register 714. Transaction logic 718 captures (910) the first portion of the data into the first set of data buffers of the data buffer bank and captures (912) the second portion of the data into the second portion of the data buffer bank. For example, transaction logic 718 requests and receives data from remote chips 106-1 through 106-N in parallel. Transaction logic 718 then forwards or writes the first portion of the data in parallel to the fast response data buffers 706 and 722 of the data buffer bank, and writes the second portion of the data in parallel to the slow response data of the data buffer bank buffer 710. In one example, once one or more of response data buffers 706, 722, or 710 are at least partially or fully populated with data, transaction logic 718 interrupts (918) processor 102 to unload at least a portion of the data. For example, once one of the fast response data buffers, eg, 722 , is filled, the transaction logic 718 interrupts the processor 102 to unload data from one fast response data buffer 722 while the transaction logic 718 fills the other response data buffer 706 .

7, the data offload accelerator includes a comparator circuit (eg, 716) and a circuit (eg, 720), and the comparator circuit 716 can compare the captured data with the subsequently retrieved data or one or more pattern matching criteria. Compare (914). At block 916, depending on how it is configured, the circuit 720 may flag subsequent data that differs from the captured data, or may take action based on whether the data meets one or more criteria. In another example, some but not all of the data that satisfies one or more criteria or is flagged is passed 918 to the processor 102 . In another example, circuit 720 (eg, if configured similarly to action circuit 508 ) takes corrective action 916 when at least some of the data satisfy one or more criteria.

For simplicity and illustrative purposes, the present disclosure is primarily described by reference to examples of the present disclosure. In the above description, numerous specific details are set forth in order to provide a thorough understanding of the present disclosure. It will be apparent, however, that the present disclosure may be practiced without being limited to these specific details. For example, examples illustrate the practice of the present disclosure using different hardware configurations and hardware combinations of data offload accelerators. However, the present disclosure may be practiced using other combinations and configurations of data offload accelerators or different configurations of ASIC initialization accelerators not described herein. Additionally, some of the depicted elements may be removed and/or modified without departing from the scope of the described examples. In other instances, some methods and structures have not been described in detail so as not to unnecessarily obscure the present disclosure. As used herein, the term "including" means including but not limited to, and the term "comprising" means including but not limited to. Additionally, the term "having" means having, but not limited to, and the term "containing" means including, but not limited to. As used herein, the term "about" when applied to a value generally means within the tolerance of the equipment used to generate the value, or in some examples, plus or minus 10%, or plus or minus 5%, or Plus or minus 1% unless explicitly stated otherwise.

Claims (20)

1. A method for offloading data from a plurality of remote chips to a processor, the method comprising: receiving a specification of a plurality of addresses for retrieving the data from the plurality of remote chips into an address buffer bank of a data offload accelerator; receiving a command for initiating capture of the data from the plurality of remote chips into an offload control device of the data offload accelerator; capturing the data from the plurality of remote chips in parallel into a data buffer bank of the data offload accelerator; and The processor is interrupted via the offload control device to pass at least a portion of the data to the processor. 2. The method of claim 1, wherein capturing the data from the plurality of remote chips comprises capturing multiple data from within each of the remote chips of the plurality of remote chips Telemetry data for control and status registers. 3. The method of claim 1, comprising: receiving, into the address buffer bank, a specification of a first portion of the plurality of addresses for retrieving a first portion of the data from the plurality of remote chips; receiving, into the address buffer bank, a specification of a second portion of the plurality of addresses for retrieving a second portion of the data from the plurality of remote chips; capturing the first portion of the data into the data buffer bank; capturing the second portion of the data into the data buffer bank; and Passing the first portion of the data to the processor is based on at least one different criterion than passing the second portion of the data to the processor. 4. The method of claim 3, comprising: receiving the specification of the first portion of the plurality of addresses into a first address buffer of the address buffer bank; receiving the specification of the second portion of the plurality of addresses into a second address buffer of the address buffer bank; capturing the first portion of the data into a first data buffer of the data buffer bank; and capturing the second portion of the data into a second data buffer of the data buffer bank for transferring the first portion of the data and the second portion of the data to The at least one different criterion for the processor includes one or both of a different rate or a different bandwidth. 5. The method of claim 1, wherein capturing the data from the plurality of remote chips into the data buffer bank in parallel comprises: Sending a plurality of requests for the data in parallel from the data offload accelerator's transaction processing logic to a plurality of remote chips; receiving, in parallel by the transaction logic, a plurality of responses including the data from the plurality of remote chips; and The data is forwarded from the transaction logic into the data buffer bank in parallel. 6. The method of claim 1, comprising writing data to the plurality of remote chips in parallel. 7. The method of claim 6, wherein writing the data to the plurality of remote chips in parallel comprises initializing the plurality of remote chips prior to capturing the data. 8. The method of claim 1, comprising: receive subsequent data from the plurality of remote chips, comparing the captured data with subsequent data; and The subsequent data that is different from the captured data is marked. 9. The method of claim 8, comprising passing the subsequent data to the processor that is different from the captured data. 10. The method of claim 1, comprising: comparing the data to one or more criteria; An action is performed based on a determination that at least some of the data satisfies the one or more criteria. 11. A data offload accelerator for offloading data from a plurality of remote chips to a processor, the data offload accelerator comprising: An address buffer bank for receiving a specification of a plurality of addresses for retrieving the data from the plurality of remote chips; An offload control device coupled to the processor, the offload control device for receiving a command to initiate capture of the data from the plurality of remote chips, and interrupting the processor to convert the At least a portion of the data is passed to the processor. transaction logic coupled to the address buffer bank and the offload control device, the transaction logic for retrieving the data from the plurality of remote chips; and A data buffer library is coupled to the transaction processing logic via a plurality of physical couplings, the data buffer library for receiving the data in parallel from the transaction processing logic. 12. The data offload accelerator of claim 11, wherein the data buffer bank comprises: a first data buffer for receiving a first portion of the data for delivery to the processor; and a second data buffer for receiving the second portion of the data based on at least one different criterion than passing the first portion of the data to the processor to passed to the processor. 13. The data offload accelerator of claim 12, wherein the address buffer bank comprises: a first address buffer for receiving a specification of a first portion of the plurality of addresses for retrieving the first portion of the data; and A second address buffer for receiving a specification of a second portion of the plurality of addresses for retrieving the second portion of the data. 14. The data offload accelerator of claim 11, wherein the offload control device comprises: a first register for receiving from the processor a message for initiating data traffic from the plurality of remote chips. the command of the capture of the data. 15. The data offload accelerator of claim 14, wherein the offload control device further comprises: a second register for interrupting the processor. 16. The data offload accelerator of claim 11, comprising a comparator circuit coupled to the data buffer bank, the comparator circuit for making a comparison and providing an output based on the comparison. 17. The data offload accelerator of claim 16, wherein the comparator circuit comprises: logic for: comparing the data received in the data buffer bank with subsequent data captured from the plurality of remote chips; and An output is provided indicating a difference between the data received in the data buffer bank and the subsequent data captured from the plurality of remote chips. 18. The data offload accelerator of claim 17, comprising: at least one register coupled to the comparator circuit and the transaction logic, the at least one register for flagging receipt of the data buffer the difference between the data in the library and the subsequent data captured from the plurality of remote chips. 19. The data offload accelerator of claim 16, wherein the comparator circuit comprises: at least one register for: comparing the data to one or more criteria; and An output is provided indicating whether the data meets the one or more criteria. 20. The data offload accelerator of claim 19, comprising: an action circuit coupled to the comparator circuit and the transaction logic, the action circuit for when the data satisfies the one or more Actions are performed when the criteria are met.

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