CN111656369A - Neural-like circuits and methods of operation - Google Patents

Abstract

The neural circuit includes a synaptic circuit and a post-neuron circuit. The synapse circuit includes a phase change element and receives a first pulse signal and a second pulse signal. The back neuron circuit comprises an input end, an output end and an integrated end. The accumulating terminal charges to a membrane potential according to the first pulse signal. The post neuron circuit further comprises a first control circuit, a second control circuit, a first delay circuit and a second delay circuit. The first control circuit generates an excitation signal according to the membrane potential at the output terminal. The second control circuit is coupled to the output terminal and generates a first control signal according to the excitation signal. The first delay circuit delays the firing signal to generate a second control signal. The second delay circuit delays the second control signal to generate a third control signal. The first control signal and the third control signal control the voltage level of the integrated end and maintain the integrated end in a period of fixed voltage. The second control signal cooperates with the second pulse signal to control the state of the phase change element, thereby determining the weight of the neural circuit.

Description

Neural-like circuits and methods of operation

technical field

Embodiments described in the present disclosure relate to a circuit technology, particularly a neural-like circuit and an operation method.

Background technique

Living organisms contain neural network systems. A neural network system contains many neurons. Neurons were proposed by Heinrich Wilhelm Gottfried von Waldeyer-Hartz in 1891. Neurons are processing units that capture discrete information in the brain. In 1897, Charles Sherrington called the junction between two neurons a "synapse". The brain's discrete information flows through synapses in one direction. According to this direction, a distinction is made between "presynaptic neurons" and "postsynaptic neurons". Neurons fire "spikes" when they receive enough input to fire.

In theory, the captured experience is turned into conductance at synapses in the brain. Synaptic conduction varies over time according to the relative spike times of presynaptic and postsynaptic neurons. If the postsynaptic neuron fires before the presynaptic neuron fires, the synaptic conductance increases. If the order of the two firings is reversed, the synaptic conductance decreases. Also, this change will depend on the delay between the two events. The more delay, the smaller the magnitude of the change.

Artificial neural networks allow electronic systems to function in ways similar to biological brains. Neuronal systems can include various electronic circuits that model biological neurons.

The neural network system will affect the perception, choice, decision or other behaviors of the organism, so the neural network system plays a very important role in the organism. If circuits could be used to build neural network systems similar to those found in living organisms, it would have a critical impact on many fields.

For example, US Patent No. 9,830,981 or Chinese Patent No. 107111783 mentioned that phase change elements and other elements can be used to construct a neural network-like system.

SUMMARY OF THE INVENTION

Some embodiments of the present disclosure relate to a neural-like circuit comprising a synaptic circuit and a postneuronal circuit. The synapse circuit includes a phase change element and is used for receiving a first pulse signal and a second pulse signal. The postneuronal circuit is coupled to the synaptic circuit. The post-neuron circuit includes an input terminal, an output terminal and an accumulation terminal. The integrated terminal is charged to a membrane potential according to the first pulse signal. The post-neuron circuit further includes a first control circuit, a second control circuit, a first delay circuit and a second delay circuit. The first control circuit is coupled between the power accumulation terminal and the output terminal. The first control circuit is used for generating an excitation signal at the output end according to the film electric potential. The second control circuit is coupled to the output end and used for generating a first control signal according to the excitation signal. The first delay circuit is used for delaying the excitation signal to generate a second control signal. The second delay circuit is used for delaying the second control signal to generate a third control signal. The first control signal and the third control signal are used to control the voltage level of the power accumulation terminal and maintain the power accumulation terminal at a fixed voltage period. The second control signal is used to control the state of the phase change element in cooperation with the second pulse signal, thereby determining a weight of the neural-like circuit.

In some embodiments, the neuron-like circuit further includes a preneuron circuit. The preneuronal circuit is coupled to the synaptic circuit. The pre-neuron circuit is used for generating the first pulse signal and the second pulse signal, and transmitting the first pulse signal and the second pulse signal to the synapse circuit.

In some embodiments, the first control circuit includes a comparator and an entire wave circuit. The comparator is used for comparing the membrane potential with a voltage threshold to generate a comparison signal. The wave shaping circuit is used for generating the excitation signal according to the comparison signal.

In some embodiments, the post-neuron circuit further includes a first switch. The first switch is coupled between the second control circuit, a power supply voltage and the accumulation terminal. The first switch is controlled by the first control signal.

In some embodiments, the post-neuron circuit further includes a second switch and a third switch. The second switch is coupled between the accumulation terminal and a ground terminal. The third switch is coupled between the output terminal and the ground terminal. The second switch and the third switch are controlled by the third control signal.

In some embodiments, the second control circuit includes an inverter. The inverter is used for receiving the excitation signal to generate the first control signal.

In some embodiments, the second control circuit includes a filter circuit. The filter circuit is used for receiving the excitation signal to generate the first control signal.

In some embodiments, the second control circuit includes an inverter and a filter circuit. The inverter is used for receiving the excitation signal to generate an inverted signal. The filter circuit is used for generating the first control signal according to the inverted signal.

In some embodiments, the synaptic circuit further includes an axonal impulse switch and an axonal plasticity switch. A first end of the axon pulse switch is used for receiving the first pulse signal. A first end of the axon plastic switch is used for receiving a second pulse signal. A second end of the axonal pulse switch and a second end of the axonal plasticity switch are coupled to the phase change element. The phase change element is coupled to the post-neuron circuit.

Some embodiments of the present disclosure relate to a method of operation of a neural-like circuit. The operation method includes: receiving a first pulse signal and a second pulse signal through a synaptic circuit; generating an excitation signal according to the first pulse signal through a post-neuron circuit, and generating a first control signal according to the excitation signal, wherein The first control signal is used to control the voltage level of an accumulation terminal of the post-neuron circuit; the post-neuron circuit delays the excitation signal to generate a second control signal; and the post-neuron circuit delays the second control signal to generate a The third control signal, wherein the third control signal is used to control the voltage level of the accumulation terminal of the post-neuron circuit, wherein the second control signal is used to control the state of the phase change element in conjunction with the second pulse signal, thereby determining the neuron-like circuit of a weight.

In some embodiments, the post-neuron circuit includes a first control circuit, and generating the excitation signal includes: comparing the voltage level of the integrated terminal with a voltage threshold through a comparator of the first control circuit to generate a comparison signal ; and generating the excitation signal according to the comparison signal through a wave-forming circuit of the first control circuit.

In some embodiments, the post-neuron circuit includes a second control circuit, and the operation method further includes: generating a first control signal according to the excitation signal through the second control circuit; and controlling a switch of the post-neuron circuit according to the first control signal .

In some embodiments, generating the first control signal includes: receiving the excitation signal through a filter circuit of the second control circuit to generate the first control signal.

In some embodiments, generating the first control signal includes: receiving the excitation signal through an inverter of the second control circuit to generate the first control signal.

In some embodiments, generating the first control signal includes: receiving the excitation signal through an inverter of the second control circuit; and generating the first control signal according to the inverted excitation signal through a filter circuit of the second control circuit.

In some embodiments, generating the second control signal and the third control signal includes: delaying the excitation signal through a first delay circuit of the post-neuron circuit to generate the second control signal; and passing a second delay of the post-neuron circuit The circuit delays the second control signal to generate the third control signal.

To sum up, the neural-like circuit and operation method disclosed in the present disclosure can construct a neural network-like system by using the circuit.

Description of drawings

In order to make the above and other objects, features, advantages and embodiments of the present disclosure more clearly understood, the accompanying drawings are described as follows:

FIG. 1 is a schematic diagram of a type of neural circuit according to some embodiments of the present disclosure;

2A is a schematic diagram of a type of neural circuit according to some embodiments of the present disclosure;

2B is a schematic diagram of a type of neural circuit according to some embodiments of the present disclosure;

3A is a timing diagram of long-term enhancement of synaptic circuits of a class of neural circuits depicted in accordance with some embodiments of the present disclosure;

3B is a timing diagram of long-term inhibition of synaptic circuits of a class of neural circuits depicted in accordance with some embodiments of the present disclosure;

4 is a schematic diagram of a type of neural circuit according to some embodiments of the present disclosure;

5 is a schematic diagram of a type of neural circuit according to some embodiments of the present disclosure;

6 is a schematic diagram of a type of neural circuit according to some embodiments of the present disclosure;

FIG. 7 is a schematic diagram of a type of neural circuit according to some embodiments of the present disclosure; and

FIG. 8 is a flowchart of an operation method of a type of neural circuit according to some embodiments of the present disclosure.

Detailed ways

As used herein, the word "coupled" may also mean "electrically coupled," and the word "connected" may also mean "electrically connected." "Coupled" and "connected" may also mean that two or more elements cooperate or interact with each other.

Please refer to Figure 1. FIG. 1 is a schematic diagram of a neural-like circuit 1000 according to some embodiments of the present disclosure.

Taking the example of FIG. 1 as an example, the neuron-like circuit 1000 includes a synapse circuit 1200, a pre-synaptic neuron circuit 1300 (hereinafter referred to as “pre-neuron” 1300) and a post-synaptic neuron. A post-synaptic neuron circuit 1400 (hereinafter referred to as "post-neuron" 1400). Preneuron 1300 includes axon driver 1310 . The axonal drive 1310 includes a pulse generator G1 and a pulse signal generator G2. Postneuron 1400 includes dendrites and is used to receive signals. In some embodiments, the axonal drive 1310 of the anterior neuron 1300 sends a spike, via the synaptic circuit 1200 , to the dendrites of the posterior neuron 1400 to stimulate the posterior neuron 1400 . In this way, an effect similar to the signal transmission in the neural network system can be achieved.

The synaptic circuit 1200 includes a phase change element PCM, a switch (axonal pulse switch) D1, and a switch (axonal plasticity switch) SW2. The phase change element PCM contains a phase change material. Phase change materials have different phases based on the magnitude of the current. Messages can be stored in the corresponding phase. For example, when the phase change element PCM is in a crystal phase or a poly crystal phase, its resistance value is relatively small. When the phase change element PCM is in an amorphous phase, its resistance value is large. Based on the magnitude of the resistance value of the phase change element PCM, the phase change element PCM can store a logical value of 1 or 0.

Switch D1 is implemented as a diode. The switch SW2 is implemented with a transistor. In some other embodiments, the switch D1 can also be implemented by a transistor. The switch D1 includes a first terminal and a second terminal. The first end is the anode end and the second end is the cathode end. The first terminal of the switch D1 is coupled to the pulse generator G1 to receive the pulse signal PS1. The first end of the switch SW2 is coupled to the pulse generator G2 to receive the pulse signal PS2. The second end of the switch D1 and the second end of the switch SW2 are coupled to the first end of the phase change element PCM. The second end of the phase change element PCM is coupled to the rear neuron 1400 . The control terminal of the switch SW2 is coupled to the posterior neuron 1400 to receive the control signal CS2 from the posterior neuron 1400 .

The post neuron 1400 includes an input terminal, a power accumulation terminal CP, an output terminal OUT, a capacitor C1, a resistor R1, control circuits CTR1-CTR3, delay circuits TD1-TD2, and switches S1-S3. The first terminal of the capacitor C1, the first terminal of the resistor R1 and the first terminal of the switch S2 are coupled to the ground terminal GND. The second end of the phase change element PCM, the second end of the capacitor C1, the second end of the resistor R1, and the second end of the switch S2 are coupled to the accumulation terminal CP. The control circuit CTR1 is coupled between the power accumulation terminal CP and the output terminal OUT. The control circuit CTR2 is coupled between the output terminal OUT and the switch S1. The control circuit CTR3 is coupled between the input terminal IN and the power accumulation terminal CP. The switch S1 is coupled between the control circuit CTR2, the power supply voltage VDD and the power accumulation terminal CP. The delay circuit TD1 is coupled between the output terminal OUT and the control terminal of the switch SW2. The delay circuit TD2 is coupled between the output terminal of the delay circuit TD1 and the control terminals of the switch S2 and the switch S3. The switch S3 is coupled between the output terminal OUT and the ground terminal GND.

The capacitance C1 in the posterior neuron 1400 simulates the potential of the neuron cell membrane, and there are various charged ions inside and outside the neuron cell membrane. Because of the difference in the type and charge of charged ions inside and outside the cell membrane, the voltage difference Vp (also called membrane potential Vp) inside and outside the cell membrane will be reflected in the capacitance C1. Neuron cell membranes have channels of different sizes that control the in and out of charged ions. Charged ions inside and outside the cell membrane can pass through these channels and cause changes in the value of the membrane potential Vp. Resistor R1 simulates the electrical effect of charged ions traveling back and forth across the channel. The impulse signal sent from the axon of the pre-synaptic neuron is received by the dendrite of the post-neuron and changes the membrane potential Vp of the post-neuron cell membrane. The behavioral effect corresponding to the post-neuron 1400 is Charge capacitor C1.

If the intensity of the above-mentioned pulse signal is large enough, when the membrane potential Vp on the capacitor C1 exceeds the voltage threshold value _Vth , the posterior neuron 1400 will output the excitation signal FIRE. On the contrary, if the intensity of the pulse signal is not large enough, although the voltage on the capacitor C1 increases, but does not exceed the voltage threshold V _th , the posterior neuron 1400 will not output the excitation signal FIRE. In addition, the increased membrane potential Vp gradually decreases through the leakage of the resistor R1. Its behavior on neuron cells is that the post-neuron instantaneously changes the concentration of charged ions inside and outside the cell membrane due to the excitation signal of the pre-neuron, and then the charged ions diffuse through the channels on the cell membrane to balance, making the membrane potential of the post-neuron cell membrane. Vp returns to the equilibrium value. Accordingly, the electrical behavior of this path, which sends impulse signals from the anterior neuron to the capacitance C1 of the posterior neuron, is called leaky integration and fire (LIF). The neuronal membrane potential, Vp, is a function of the leakage product sum and excitation (LIF) (Vp=F(LIF)).

The firing signal of the anterior neuron affects the cell membrane potential of the posterior neuron 1400 via synapses (comprising the axons of the anterior neuron and the dendrites of the posterior neuron). However, even with the same excitation signal, different anterior neurons have different effects on the membrane potential of posterior neurons. It can be said that the size of the synaptic weight (weighting: W) is different between the front and rear neurons. Synaptic weights (W) are plastic (or adaptable). The size of the weight change (ΔW) is a function of the time difference between the pre-neuron firing time point (tpre) and the post neuron firing time point (tpost): ΔW=F(tpost-tpre). In other words, the magnitude of the synaptic weight change (ΔW) is related to the time difference between the time point tpre and the time point tpost, and the synaptic weight W is adaptively adjusted according to the value of the time difference. Thus, synaptic weights W relate to indicators of causal relationships between neurons. In this way, a characteristic index representing the change of weight (W) of synapse due to the relative relationship between the firing time of pre- and post-neuron is defined, which is called "Spike timing dependent plasticity" (STDP). Spike time-dependent plasticity (STDP) of synapses is also indirectly related to leakage product sum and excitation (LIF). This is because the leaky sum and firing (LIF) can determine the firing time point (tpost) of the posterior neuron. In one embodiment, the spiking time-dependent plasticity (STDP) of synapses represents the plasticity of synaptic current conductance. More specifically, in some embodiments, the spike time-dependent plasticity (STDP) of a synapse represents the magnitude of the synaptic resistance.

Please refer to FIG. 2A and FIG. 3A . 3A is a timing diagram of long-term enhancement of the synaptic circuit 1200 of the neural-like circuit 1000 shown in accordance with some embodiments of the present disclosure. Operationally, anterior neuron 1300 sends a spike to posterior neuron 1400 . The pulse generator G1 will send the pulse signal PS1. The pulse time of the pulse signal PS1 is from the time point t1 to the time point t2. In some embodiments, the pulse signal PS1 is also called “axonal pulse LIF”, and its pulse width is 0.1 milliseconds (ms), but the present disclosure is not limited thereto. In the initial state, the switch S1 of the post-neuron 1400 is in an off state, and the accumulation terminal CP is in a floating state. During the pulse time of the pulse signal PS1, the switch D1 is turned on. The pulse signal PS1 charges the power accumulation terminal CP through the switch D1, the phase change element PCM and the control circuit CTR3, so as to generate a voltage level (film potential) Vp at the power accumulation terminal CP. After the pulse signal PS1 ends, the control circuit CTR3 will cut off the electrical path between the posterior nerve 1400 and the synaptic circuit 1200 . At time point t2, the preneuron 1300 sends a pulse signal PS2, and the pulse time of the pulse signal PS2 is from time point t2 to time point t7. In some embodiments, the pulse signal PS2 is also called "axonal pulse STDP". The pulse time of the pulse signal PS2 is divided into two time intervals of equal time before and after. The pulses in the first time interval (td) gradually decrease from a high voltage, and the pulses in the latter time interval (td) instantaneously increase a voltage value (not marked), and then gradually increase the voltage. In some embodiments, the pulse signal PS2 period (2td) is 100 milliseconds (ms).

At the same time, the membrane potential Vp of the post-neuron 1400 is oscillatedly increased due to the interlaced influence of the pulse signal PS1 (axonal pulse LIF) of other pre-neurons (not shown) on the charging of the capacitor C1 and the discharge of the resistor R1. When the membrane potential Vp reaches the voltage threshold value V _th at the time point t3, the control circuit CTR1 generates the excitation signal FIRE at the output terminal OUT. In some embodiments, the above-mentioned excitation signal FIRE is also referred to as "Post-synaptic Neuron Axon Spike". The above-mentioned firing signal FIRE immediately generates the control signal CS1 through the control circuit CTR2 to turn on the switch S1, so the power supply voltage VDD charges the film potential Vp to the power supply voltage VDD. The excitation signal FIRE is delayed by the delay circuit TD1 and the delay circuit TD2 to generate the control signal CS3 to turn on the switch S2 and the switch S3. The voltage of the membrane potential Vp at this time decreases again to the ground value (the ground terminal GND) at the time point t8. In some embodiments, the delay time of the delay circuit TD1 and the delay circuit TD2 are both td, so the voltage of the membrane potential Vp is maintained at the power supply voltage VDD for 2td time (time point t3 to time point t8 ), during this time ( 2td), the posterior neuron 1400 cannot accept the firing of other neurons.

Next, please refer to FIGS. 2B and 3A at the same time. FIG. 3A is a timing diagram of long-term synaptic potentiation of the synaptic circuit 1200 of the neural-like circuit 1000 according to some embodiments of the present disclosure. When the control circuit CTR1 generates the firing signal FIRE at the output terminal OUT, the firing signal FIRE generates the control signal CS2 through the delay circuit TD1. The pulse time of the control signal CS2 is from the time point t5 to the time point t6. In some embodiments, the above-mentioned control signal CS2 is also called "Post-Synaptic Neuron STDP Trigger", and its pulse time is 0.1 milliseconds (ms). The control signal CS2 controls the gate of the switch SW2 in the synapse circuit 1200 to turn on the switch SW2.

During the pulse time of the control signal CS2, the current flowing through the phase change element PCM in the synaptic circuit 1200 will be determined by the synergistic effect of the pulse signal PS2 (axonal pulse STDP) and the control signal CS2 (post-neuron STDP trigger). In other words, the pulse signal PS2 (axonal pulse STDP) and the control signal CS2 (post-neuron STDP trigger) can determine the magnitude of the current flowing through the phase change element PCM. Specifically, at the pulse time of the pulse signal PS2 (axon pulse STDP), the control circuit CTR3 has a circuit path connected to the power supply voltage VDD, and the second terminal of the phase change element PCM is coupled to the power supply voltage VDD. At this time, the switch D1 is not conducting, so the current can only flow through the switch SW2. When the switch SW2 is turned on, the first end of the switch SW2 receives the pulse signal PS2 (axon pulse STDP).

Please refer to Figure 3A. The pulse time (time point t5 to time point t6) of the control signal CS2 (post-neuron STDP trigger) falls in the latter time interval of the pulse signal PS2 (axonal pulse STDP), so the first end of the switch SW2 is connected to the first end of the switch SW2. The voltage difference between the two terminals is small. Accordingly, the current flowing through the switch SW2 momentarily is small. That is, the current flowing through the phase change element PCM instantaneously is small. In this way, the phase change element PCM has a small resistance value. In other words, the synapse circuit 1200 has better conductivity, so it is called Synapse Long Term Potentiation. This also means that the firing of the posterior neuron 1400 (fire signal FIRE) is related to the impulse signal PS1 (axonal impulse LIF) of the pre-neuron 1300 . That is, the firing of the posterior neuron 1400 (fire signal FIRE) is causally related to the firing of the anterior neuron 1300 . Therefore, the weight W of the synaptic circuit 1200 connecting the two neurons is increased.

Otherwise, please refer to FIG. 2A , FIG. 2B and FIG. 3B simultaneously. 3B is a timing diagram of long-term inhibition of the synaptic circuit 1200 of the neural-like circuit 1000 according to some embodiments of the present disclosure. The operation principle described below is similar to the above, and only the differences are described below. Please refer to Figure 3B first. The pulse time (time point t5 to time point t6) of the control signal CS2 (post-neuron STDP trigger) falls within the previous time interval of the pulse signal PS2 (axonal pulse STDP), so the first end of the switch SW2 and the second The voltage difference between the terminals is large. Accordingly, the current flowing through the switch SW2 instantaneously is larger. That is, the current flowing through the phase change element PCM instantaneously is large. In this way, the phase change element PCM has a higher resistance value. In other words, the synapse circuit 1200 has poor conductivity, so it is called synapse long term depression (Synapse Long Term Depression). It can be seen from FIG. 3B that the excitation of the posterior neuron 1400 (the excitation signal FIRE) is not caused by the impulse signal PS1 (the axonal impulse LIF) of the anterior neuron 1300 . That is, the firing of the posterior neuron 1400 (fire signal FIRE) is not causally related to the firing of the anterior neuron 1300 . Therefore, the weight W of the synaptic circuit 1200 connecting the two neurons is lowered. The neural-like circuit 1000 can use the above operations to perform learning behaviors, so as to implement a neural network system similar to that in a living body.

Refer to Figure 4. FIG. 4 is a schematic diagram of a neural-like circuit 4000 according to some embodiments of the present disclosure. The neuron-like circuit 4000 includes a pre-neuron 4300 , a synaptic circuit 4200 and a post-neuron 4400 . Only the main differences between the neural-like circuit 4000 of FIG. 4 and the neural-like circuit 1000 of FIG. 1 are described below.

Taking the example of FIG. 4 as an example, as mentioned above, the control circuit CTR1 can be realized by the comparator COM and the wave rectifying circuit SP. The comparator COM compares the voltage level of the integration terminal CP with the voltage threshold V _th to generate a comparison signal. When the membrane potential Vp is less than the voltage threshold value _Vth , the comparison signal has a low voltage level. When the membrane potential Vp is greater than the voltage threshold value _Vth , the comparison signal has a high voltage level. The wave rectifying circuit SP generates the excitation signal FIRE according to the comparison signal.

In addition, as described above, the control circuit CTR2 can be realized by the inverter INV1. Taking the example of FIG. 4 as an example, the control circuit CTR2 further includes a filter circuit FT2. The filter circuit FT2 includes a capacitor C2 and a resistor R2. The inverter INV1 receives the firing signal FIRE to generate an inverted signal. The filter circuit FT2 filters the inverted signal from the inverter INV1 to generate the control signal CS1. In this embodiment, the switch S1 is a P-type metal oxide semiconductor field effect transistor (PMOS). In the initial state, the gate terminal of the switch S1 is coupled to the power supply voltage VDD, the switch S1 is turned off, the accumulation terminal CP is in a floating state, and when the control circuit CTR1 sends a positive-phase excitation signal FIRE, the inverter INV1 will activate the signal FIRE inverted. The filter circuit FT2 is a high pass filter, so the control terminal of the switch S1 is instantly pulled to a low voltage, and the switch S1 is turned on to raise the voltage of the power supply terminal CP to the power supply voltage VDD. The time constant (τ) of the filter circuit FT2 is appropriately designed so that the voltage at the control terminal of the switch S1 rises slowly. Switch S1 can be closed for approximately twice td time. The connection relationship and operation of other elements of the neural-like circuit 4000 are similar to those of the neural-like circuit 1000 in FIG. 1 , and thus will not be repeated here.

Please refer to Figure 5. FIG. 5 is a schematic diagram of a neural-like circuit 5000 according to some embodiments of the present disclosure. The neuron-like circuit 5000 includes a pre-neuron 5300 , a synaptic circuit 5200 and a post-neuron 5400 . Only the main differences between the neural-like circuit 5000 of FIG. 5 and the neural-like circuit 1000 of FIG. 1 will be described below.

For example in FIG. 5 , the control circuit CTR2 includes an inverter INV2 and an inverter INV3 . The inverter INV2 receives the firing signal FIRE to generate an inverted signal. The inverter INV3 receives the inverted signal to generate the control signal CS1. In this embodiment, when the firing signal FIRE has a high voltage level, the control signal CS1 has a high voltage level. The switch S1 is an N-type transistor, and the switch S1 is turned on according to the control signal CS1 with a high voltage level, thereby controlling (maintaining) the voltage level of the accumulation terminal CP. In this embodiment, the switch S1 is an N-type metal oxide semiconductor field effect transistor (NMOS). In the initial state, the gate terminal of the switch S1 is connected to the ground terminal GND, the switch S1 is turned off, and the accumulation terminal CP is floating. state, when the control circuit CTR1 sends a positive-phase excitation signal FIRE, the inverter INV2 and the inverter INV3 cooperate to instantly pull the control terminal of the switch S1 to a high voltage, and the switch S1 is turned on to pull the voltage of the accumulation terminal CP to the power supply voltage VDD. After the pulse signal FIRE ends, the switch S1 is turned off, and the accumulation terminal CP is in a floating state.

The connection relationship and operation of the other components of the neural-like circuit 5000 are similar to those of the neural-like circuit 1000 in FIG. 1 , and thus will not be repeated here.

Please refer to Figure 6. FIG. 6 is a schematic diagram of a neural-like circuit 6000 according to some embodiments of the present disclosure. The neuron-like circuit 6000 includes a pre-neuron 6300 , a synaptic circuit 6200 and a post-neuron 6400 . Only the main differences between the neural-like circuit 6000 of FIG. 6 and the neural-like circuit 5000 of FIG. 5 will be described below.

Taking the example of FIG. 6 as an example, the control circuit CTR2 further includes a filter circuit FT4. Filter circuit FT4 filters the output of inverter INV3 to generate control signal CS1. When the control circuit CTR1 sends the positive-phase excitation signal FIRE, because the FT4 is a high pass filter (High Pass Filter), the control terminal of the switch S1 is instantly pulled to a high voltage. The switch S1 is turned on to pull up the voltage of the power supply terminal CP to the power supply voltage VDD. The time constant (τ) of the filter circuit FT4 is appropriately designed, so that the voltage at the control terminal of the switch S1 decreases slowly, and the switch S1 can be turned off at about twice the time td.

The connection relationship and operation of the remaining components of the neural-like circuit 6000 are similar to those of the neural-like circuit 5000 in FIG. 5 , and thus will not be repeated here.

Please refer to Figure 7. FIG. 7 is a schematic diagram of a neural-like circuit 7000 according to some embodiments of the present disclosure. The neuron-like circuit 7000 includes a synaptic circuit 7200 and a post-neuron 7400 . Only the main differences between the neural-like circuit 7000 of FIG. 7 and the neural-like circuit 1000 of FIG. 1 are described below.

For example in FIG. 7 , the control circuit CTR2 can be implemented by a level latch LA1 (Level Latch) and a delay circuit TD3, but the present disclosure is not limited to this.

The connection relationship and operation of other components of the neural-like circuit 7000 are similar to those of the neural-like circuit 6000 in FIG. 6 , and thus will not be repeated here.

Please refer to Figure 8. FIG. 8 is a flowchart of a method 8000 for operating a type of neural circuit according to some embodiments of the present disclosure. Taking the example of FIG. 8 , the operation method 8000 includes operation S810 , operation S820 , operation S830 , operation S840 , and operation S850 . In some embodiments, the operation method 8000 is applied to the neural-like circuit 1000 of FIG. 1 , but the present disclosure is not limited thereto. For ease of understanding, the following discussion will be made in conjunction with FIG. 1 .

In operation S810 , the axonal pulse LIF (pulse signal PS1 ) and the axonal pulse STDP (pulse signal PS2 ) are sent by the preneuron 1300 to the synapse circuit 1200 . In some embodiments, synaptic circuit 1200 acts like an axon of anterior neuron, emitting axonal pulse STDP (pulse signal PS2 ) to posterior neuron 1400 .

In operation S820, an excitation signal FIRE is generated by the posterior neuron 1400 according to the axonal pulse LIF (pulse signal PS1). In some embodiments, post-neuron 1400 acts like a dendrite of a post-neuron to receive signals from synaptic circuit 1200 . The axonal pulse LIF (pulse signal PS1) charges the capacitor of the accumulation terminal CP of the posterior neuron 1400, and the membrane potential on the accumulation terminal CP is compared with the voltage threshold V _th to generate the excitation signal FIRE.

In operation S830, a delay time td is introduced to the firing signal FIRE by the post-neuron 1400 to generate a post-neuron STDP trigger (control signal CS2). In some embodiments, the delay circuit TD1 introduces a delay time td to the firing signal FIRE to output the post-neuron STDP firing (control signal CS2).

In operation S840, the post-neuron STDP triggering (control signal CS2) is delayed by the post-neuron 1400 to generate the control signal CS3. In some embodiments, the delay circuit TD2 introduces a delay time td to the post-neuron STDP triggering (control signal CS2) to output the control signal CS3. The control signal CS3 is used to control the switch S2 and the switch S3, so that the power accumulation terminal CP is maintained at a delay time td that is twice the high voltage level.

In operation S850, the post-neuron STDP triggers (control signal CS2) in conjunction with axonal pulse STDP (pulse signal PS2) to control the switch SW2, thereby controlling the state of the phase change element PCM to determine the weight of the synaptic circuit 1200. In some embodiments, if the pulse interval of the post-neuron STDP trigger (control signal CS2) falls within the latter time interval of the axonal pulse STDP (pulse signal PS2), the resistance of the phase change element PCM of the synaptic circuit 1200 changes. is small, so the weight of the synaptic circuit 1200 is enhanced. In some embodiments, if the pulse interval of the post-neuron STDP triggering (control signal CS2) falls within the preceding time interval of the axonal pulse STDP (pulse signal PS2), the resistance of the phase change element PCM of the synaptic circuit 1200 increases. , so the weight of the synaptic circuit 1200 is suppressed.

The above description of method of operation 8000 contains exemplary operations, but the operations of method of operation 8000 do not have to be performed in the order shown. It is within the spirit and scope of the embodiments of the present disclosure that the order of the operations of the operation method 8000 may be changed, or that the operations may be performed concurrently, partially concurrently, or partially omitted as appropriate.

To sum up, the neural-like circuit and operation method disclosed in the present disclosure can construct a neural network-like system by using the circuit.

Although the present disclosure has been disclosed as above in embodiments, it is not intended to limit the present disclosure. Anyone with ordinary knowledge in the art can make various changes and modifications without departing from the spirit and scope of the present disclosure. Therefore, The scope of protection of the present disclosure should be determined by the scope defined by the appended claims.

Claims (16)

1. A neural circuit, comprising:

a synapse circuit comprising a phase change element for receiving a first pulse signal and a second pulse signal; and

a post-neuron circuit coupled to the synapse circuit, wherein the post-neuron circuit comprises an input terminal, an output terminal, and an integrating terminal, wherein the integrating terminal charges to a membrane potential according to the first pulse signal, the post-neuron circuit further comprising:

the first control circuit is coupled between the accumulated power end and the output end and used for generating an excitation signal at the output end according to the membrane electricity;

a second control circuit coupled to the output terminal, the second control circuit generating a first control signal according to the excitation signal;

a first delay circuit for delaying the trigger signal to generate a second control signal; and

a second delay circuit for delaying the second control signal to generate a third control signal;

the first control signal and the third control signal are used for controlling the voltage level of the accumulating end and maintaining the accumulating end at a fixed voltage period, and the second control signal is used for cooperating with the second pulse signal to control the state of the phase change element so as to determine the weight of the neural circuit.

2. The neural circuit of claim 1, further comprising:

a pre-neuron circuit coupled to the synapse circuit, the pre-neuron circuit configured to generate the first pulse signal and the second pulse signal and transmit the first pulse signal and the second pulse signal to the synapse circuit.

3. The neural circuit of claim 1, wherein the first control circuit comprises:

a comparator for comparing the membrane potential with a voltage threshold to generate a comparison signal; and

a wave shaping circuit for generating the excitation signal according to the comparison signal.

4. The neural circuit of claim 1, wherein the post-neuron circuit further comprises:

and the first switch is coupled among the second control circuit, a power supply voltage and the accumulated power end and is controlled by the first control signal.

5. The neural circuit of claim 4, wherein the post-neuron circuit further comprises:

the second switch is coupled between the accumulated electricity end and a grounding end; and

a third switch coupled between the output terminal and the ground terminal;

wherein the second switch and the third switch are controlled by the third control signal.

6. The neural circuit of claim 1, wherein the second control circuit comprises:

an inverter for receiving the excitation signal to generate the first control signal.

7. The neural circuit of claim 1, wherein the second control circuit comprises:

a filter circuit for receiving the excitation signal to generate the first control signal.

8. The neural circuit of claim 1, wherein the second control circuit comprises:

an inverter for receiving the excitation signal to generate an inverted signal; and

a filter circuit for generating the first control signal according to the inverted signal.

9. The neural circuit of claim 1, wherein the synaptic electrical circuit further comprises:

an axon pulse switch, wherein a first end of the axon pulse switch is configured to receive the first pulse signal; and

and the axon plastic switch is used for receiving a second pulse signal, wherein a second end of the axon pulse switch and a second end of the axon plastic switch are coupled to the phase change element, and the phase change element is coupled to the post-neuron circuit.

10. A method of operating a neural circuit, comprising:

receiving a first pulse signal and a second pulse signal through a synapse circuit;

generating a trigger signal according to the first pulse signal by a back neuron circuit, and generating a first control signal according to the trigger signal, wherein the first control signal is used for controlling the voltage level of an integrating end of the back neuron circuit;

delaying the excitation signal by the post neuron circuit to generate a second control signal; and

delaying the second control signal by the post neuron circuit to generate a third control signal;

the third control signal is used for controlling the voltage level of the integrating end of the back neuron circuit, and the second control signal is used for cooperating with the second pulse signal to control the state of the phase change element so as to determine the weight of the neuron circuit.

11. The method of claim 10, wherein the post-neuron circuit comprises a first control circuit, and generating the excitation signal comprises:

comparing the voltage level of the accumulating end with a voltage threshold value through a comparator of the first control circuit to generate a comparison signal; and

the excitation signal is generated by a wave shaping circuit of the first control circuit according to the comparison signal.

12. The method of claim 10, wherein the post-neuron circuit comprises a second control circuit, the method further comprising:

generating the first control signal by the second control circuit according to the excitation signal; and

controlling a switch of the back neuron circuit according to the first control signal.

13. The method of claim 12, wherein generating the first control signal comprises:

the excitation signal is received by a filter circuit of the second control circuit to generate the first control signal.

14. The method of claim 12, wherein generating the first control signal comprises:

the excitation signal is received by an inverter of the second control circuit to generate the first control signal.

15. The method of claim 12, wherein generating the first control signal comprises:

receiving the excitation signal through an inverter of the second control circuit; and

the first control signal is generated by a filter circuit of the second control circuit according to the inverted excitation signal.

16. The method of claim 10, wherein generating the second control signal and the third control signal comprises:

delaying the fire signal by a first delay circuit of the post neuron circuit to generate the second control signal; and

the second control signal is delayed by a second delay circuit of the post neuron circuit to generate the third control signal.

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