CN111601916A - Quality determination method of silicon ingot, quality determination program of silicon ingot, and manufacturing method of single crystal silicon - Google Patents

Abstract

A method for determining the quality of a plurality of silicon ingots cut out of a silicon single crystal pulled by a Czochralski method, the method comprising: a step (S2) for obtaining the quality evaluation results of the sample wafers cut from the respective ends of the plurality of silicon blocks; a step (S3) for acquiring actual data on pulling of the silicon single crystal; a step (S6, S7) of setting a pulling control range of each silicon block according to the quality evaluation result of each sample wafer; and a step (S8, S9) of comparing the acquired pulling actual data with the set pulling control range and judging the quality of each silicon block.

Description

Quality determination method of silicon ingot, quality determination procedure of silicon ingot, and production of single crystal silicon method

technical field

The invention relates to a method for judging the quality of a silicon block, a program for judging the quality of a silicon block and a method for producing single crystal silicon.

Background technique

Conventionally, when manufacturing semiconductor wafers, such as a silicon wafer, after grinding the outer periphery of the single crystal silicon ingot pulled by the pulling method, for example, the top part and the tail part which cannot be used as a product are cut off. After that, the single crystal silicon ingot is cut into a plurality of silicon ingots using a cutting device such as a wire saw.

At this time, a sample wafer was cut out from the end of the silicon block, and the resistivity, oxygen concentration, OSF (Oxidation Induced Stacking Fault ring, oxidation induced stacking fault ring), Void defect, L/DL defect (Large Dislocation Loop, large dislocation ring) were evaluated by evaluating Ring) and other Grown-in (original) defects, etc., to evaluate the quality of the silicon block.

In addition, in recent years, there has been a strong demand for wafers having no primary defects or only an extremely low density of primary defects in the entire surface of the wafer, and along with this, there is also a strong demand for single crystals with no primary defects or only an extremely low density of primary defects. silicon.

As a method of pulling such single crystal silicon, for example, there is a method of pulling the single crystal silicon while improving the temperature distribution in the furnace of the pulling device and adjusting the pulling speed.

However, the management range of the pulling speed is very narrow, so even if the crystal quality at the end of the silicon block is acceptable, if the pulling speed varies in the middle part of the block, there may be cases where primary defects are generated in the silicon block, so there is a next A defect occurred in the process.

Here, among the defects, the defect based on the detection result of the L/DL defect is referred to as the L/DL defect, and the defect based on the detection result of the Void defect is referred to as the Void defect.

Patent Document 1 discloses a technique in which pulling data is read into a computer along the growth axis of a single crystal silicon ingot, and when the difference between the pulling data and a target value becomes a predetermined value or more, the position becomes a predetermined position or more. A single crystal silicon ingot is cut to obtain a silicon ingot without primary defects.

prior art literature

Patent Literature

Patent Document 1: Japanese Patent Laid-Open No. 2007-99556

SUMMARY OF THE INVENTION

The technical problem to be solved by the invention

However, in the technique disclosed in Patent Document 1, since the difference between the pulling data and the target value is managed so that the difference between the target value becomes a predetermined value, it does not necessarily agree with the quality evaluation result of the actual sample wafer. Therefore, in the next step, when the silicon block determined to be defective is excluded, the silicon block is cut, and the quality evaluation is performed again, it is not known in which part the defect has occurred, so there is a problem that the frequency of quality confirmation increases. .

An object of the present invention is to provide a method for judging the quality of a silicon ingot, a program for judging the quality of a silicon ingot, and a method for producing single crystal silicon, which can reduce the frequency of quality confirmation in the next step.

Solutions for Technical Problems

The quality judging method of a silicon ingot of the present invention is a quality judging method of a silicon ingot for judging the quality of a plurality of silicon ingots cut out from single crystal silicon pulled by the pulling method, and the characteristics of the quality judging method of the silicon ingot It is to perform: the step of obtaining the quality evaluation results of the sample wafers cut out from the respective ends of the plurality of silicon blocks; the step of obtaining the actual data of the pulling of the single crystal silicon; according to the quality evaluation results of each sample wafer, setting The step of pulling management range of each silicon block; and the step of judging the quality of each silicon block by comparing the obtained actual data of pulling and the set pulling management range.

Here, the quality evaluation of the sample wafer refers to the quality evaluation in the Pv region, the region where the Pv region and the Pi region coexist, and the Pi region of the single crystal silicon without primary defects.

In addition, the pull-up management range refers to a range of allowable actual values with respect to the pull-up target value, and is set based on the quality evaluation result of the sample wafer.

According to the present invention, according to the quality evaluation result of the sample wafer, the pulling management range of each silicon block is set, and the pulling management range and actual pulling data of each silicon block are compared. Therefore, the actual pulling data beyond the pulling management range can be determined with high accuracy, and the frequency of quality confirmation in the next process can be reduced.

In the present invention, before the step of setting the pull-up management range, if a result showing L/DL (Large Dislocation Loop) failure is obtained in the quality evaluation result of the sample wafer, it is preferable to execute the exclusion and display the result. steps of the silicon block.

According to the present invention, if a sample wafer exhibits L/DL failure, it is highly likely that all silicon blocks from which the sample wafer is cut out have L/DL failure. Therefore, it is possible to preliminarily exclude defective products and further reduce the quality in the next process. Confirm the frequency.

In the present invention, before the step of setting the pull-up management range, if a result showing void failure is obtained in the quality evaluation result of the sample wafer, the step of excluding the silicon block showing the result is preferably performed.

According to the present invention, similarly to the case of L/DL failure, it is possible to exclude a silicon block with a Void failure, and to further reduce the frequency of quality confirmation in the next process.

The quality judging program of a silicon block of the present invention is characterized by causing a computer to execute the above-mentioned method for judging the quality of a silicon block.

According to the present invention, since automation can be promoted by executing the computer, the burden of the quality control process itself can be reduced.

The method for producing single crystal silicon of the present invention is characterized in that a computer executes the quality determination program of the silicon block, calculates a pulling control range when pulling the single crystal silicon, and controls the pulling control range based on the calculated pulling control range. The pulling of the single crystal silicon.

According to the present invention, by controlling the pulling of single crystal silicon according to the pulling management range set for each silicon block, it is possible to prevent the generation of defective silicon blocks and reduce the generation of defective products.

Description of drawings

FIG. 1 is a schematic view showing a pulling apparatus for single crystal silicon according to an embodiment of the present invention.

FIG. 2 is a flowchart showing the quality determination method of single crystal silicon according to the embodiment.

FIG. 3 is a schematic diagram for explaining the management range of the embodiment.

FIG. 4 is a schematic diagram for explaining the management range of the embodiment.

FIG. 5 is a graph showing the quality judgment results of the example.

FIG. 6 is a graph showing the quality judgment result of the example.

Detailed ways

[1] Structure of the pulling device 1 for single crystal silicon

FIG. 1 is a schematic diagram showing an example of the configuration of a single crystal silicon pulling device 1 to which the method for producing single crystal silicon 10 according to the embodiment of the present invention can be applied. The pulling apparatus 1 is an apparatus for pulling up the single crystal silicon 10 by the pulling method, and includes a chamber 2 constituting an outer casing, and a crucible 3 arranged in the center of the chamber 2 .

The crucible 3 has a double-layer structure composed of an inner quartz crucible 3A and an outer graphite crucible 3B, and is fixed to an upper end portion of a rotatable and ascendable support shaft 4 .

Resistance heating heaters 5A and 5B surrounding the crucible 3 are provided on the outside of the crucible 3 , and a heat insulating material 6 is provided on the outside of the crucible 3 along the inner surface of the chamber 2 .

Above the crucible 3, on the same shaft as the support shaft 4, a pulling shaft 7 such as a wire that rotates at a predetermined speed in the opposite direction or the same direction is provided. A seed crystal 8 is attached to the lower end of the pulling shaft 7 .

A cylindrical heat shield 12 is arranged in the chamber 2 .

The heat shield 12 functions to cut off the high-temperature radiant heat from the silicon melt 9 in the crucible 3, the heaters 5A, 5B, or the side walls of the crucible 3 for the single crystal silicon 10 being grown, and to prevent the crystal growth interface. That is, in the vicinity of the solid-liquid interface, the diffusion of heat to the outside is suppressed, and the function of controlling the temperature gradient in the pulling axis direction of the single crystal center portion and the single crystal outer peripheral portion is performed.

The heat shield 12 also functions as a rectifying cylinder for discharging the evaporated part from the silicon melt 9 to the outside of the furnace by the inert gas introduced from above the furnace.

The upper part of the chamber 2 is provided with a gas introduction port 13 for introducing an inert gas such as argon gas (hereinafter referred to as Ar gas) into the chamber 2 . An exhaust port 14 is provided at the lower part of the chamber 2, and the exhaust port 14 sucks and discharges the gas in the chamber 2 by driving a vacuum pump (not shown).

The inert gas introduced into the chamber 2 from the gas inlet 13 descends between the growing single crystal silicon 10 and the heat shield 12 , and passes between the lower end of the heat shield 12 and the liquid level of the silicon melt 9 After the clearance, it flows out toward the outside of the heat shield 12 , even the outside of the crucible 3 , and then descends outside the crucible 3 , and is discharged from the exhaust port 14 .

When the single crystal silicon 10 is produced using the pulling apparatus 1, the polycrystalline silicon or the like filled in the crucible 3 is heated by the heaters 5A and 5B while maintaining the inside of the chamber 2 in a state of an inert gas under reduced pressure. The solid raw material is melted to form a silicon melt 9 . When the silicon melt 9 is formed in the crucible 3, the pulling shaft 7 is lowered, the seed crystal 8 is immersed in the silicon melt 9, and the crucible 3 and the pulling shaft 7 are slowly pulled up while rotating in a predetermined direction. The shaft 7 is pulled up, thereby growing the single crystal silicon 10 connected to the seed crystal 8 .

[2] Crystal defects generated in the single crystal silicon 10

It is known that in the single crystal silicon 10 pulled by the pulling method, there are crystal defects (primary defects) formed during crystal growth.

Generally, there are real point defects in the single crystal silicon 10 , namely, Vacancy (vacancy) and Interstitial (invading) silicon.

The saturation concentration of these genuine point defects is a function of temperature, and a supersaturated state of point defects occurs with the rapid temperature drop during crystal growth.

The supersaturated point defects progress in the direction of alleviating the supersaturated state due to pair extinction, out-diffusion, slope diffusion, and the like. Usually, the supersaturation state cannot be completely eliminated, and eventually it remains as a supersaturated point defect in which either vacancies or intrusive silicon predominate.

It is known that when the crystal growth rate is high, vacancies tend to be in a supersaturated state, and conversely, when the crystal growth rate is slow, intrusive silicon tends to be in a supersaturated state.

When the concentration of this supersaturated state reaches a certain value or more, these aggregate and form crystal defects (primary defects) during crystal growth.

As a native defect in the case of a vacancy-dominated region (V region), an OSF core or a void defect is known. The OSF core is that when a sample cut from a crystal is heat-treated at a high temperature of about 1100°C in a humid oxygen atmosphere, intrusive silicon is implanted from the surface, and stacking faults (SF) are grown around the OSF core. Defects observed as stacking faults when the sample was selectively etched while being shaken in the liquid.

Since stacking faults are grown by oxidation treatment, they are called OSFs (Oxygen induced Stacking Faults).

Void defects are void-like defects in which vacancies are aggregated, and it is known that an oxide film called an inner wall oxide film is formed on the inner wall. This defect has several names depending on the detection method.

When the surface of the wafer is irradiated with laser light and observed by a particle counter that detects reflected light, scattered light, etc., it is called COP (Crystal Originated Pattern Defect).

When the sample is left to stand for a relatively long period of time without shaking the sample in the selected etching solution, when a flow pattern is observed, it is called FPD (Flow Pattern Defect).

When an infrared light laser is incident from the surface of the wafer and observed by an infrared scattering tomography scanner that detects the scattered light, it is called LSTD (Laser Scattering Tomography Defect). Although these detection methods are different, they are all considered Void defects.

DSOD (Direct Surface Oxide Defect, Direct Surface Oxide Defect) is also one of the Void defects. DSODs are tiny void defects that exist in the OSF region. Since it is a minute void defect, it cannot be observed by selective etching or the like.

DSOD evaluation detects defects by growing an oxide film on a wafer and performing Cu decoration on it.

On the other hand, when the intrusive silicon is dominant, a crystal defect in which the intrusive silicon is aggregated is formed. Although its true identity is not clear, it is considered to be a dislocation loop or the like, and the huge defect is observed by TEM (Transmission Electron Microscopy, transmission electron microscopy) as a cluster of dislocation loops.

The primary defects of the intrusive silicon were observed as large conchoidal pits by the same etching method as that of FPD, that is, by leaving the sample in a selective etching solution for a relatively long period of time without shaking it. This is called LEP (Large EtchPit).

These dislocation loops, dislocation loop clusters and LEPs are collectively referred to as L/DL (Large Dislocation Loop, large dislocation loop).

[3] Quality judgment method of silicon block

The quality determination method of the silicon block of the present embodiment will be described with reference to the flowchart shown in FIG. 2 . The quality determination program of the silicon block of the present embodiment can be executed by installing the quality determination program of the silicon block in a computer.

After the single crystal silicon 10 is produced by the pulling device 1 (step S1 ), the outer periphery of the single crystal silicon 10 is ground, and then cut into a plurality of silicon blocks 10A, 10B, and 10C with a wire saw or the like (see FIG. 4 , which illustrates In the case of dividing into 3 pieces, it may be 4 pieces or more, or 2 pieces or less). At this time, sample wafers SW1 , SW2 , SW3 , and SW4 were simultaneously cut out from both ends of the silicon blocks 10A, 10B, and 10C, and the sample wafers SW1 , SW2 , SW3 , and SW4 were each subjected to quality evaluation. In addition, the sample wafer SW2 is a common sample of the silicon block 10A and the silicon block 10B, and the sample wafer SW3 is a common sample of the silicon block 10B and the silicon block 10C.

After the quality evaluation is completed, the quality evaluation results of each of the sample wafers SW1, SW2, SW3, and SW4 are read into the computer (step S2).

In addition, the actual manufacturing data when the single crystal silicon 10 is pulled are also read into the computer (step S3).

The computer determines whether or not there are sample wafers SW1 , SW2 , SW3 , and SW4 showing L/DL failure or Void failure in the quality evaluation results (step S4 ). Regarding the determination of L/DL failure, if L/DL occurred at one of the sample wafers SW1 , SW2 , SW3 , and SW4 , the L/DL failure was determined. In addition, regarding the determination of whether or not it is a Viod defect, when the number of Void defects detected in the sample wafers SW1 , SW2 , SW3 , and SW4 is a predetermined number or more, for example, 100 or more per wafer, it is determined to be a defect. When neither L/DL failure nor Void failure occurs, the process proceeds to step S6.

If there are sample wafers SW1, SW2, SW3, and SW4 showing L/DL failure or Void failure, the silicon ingot from which the sample wafers SW1, SW2, SW3, and SW4 are cut out is excluded from the silicon ingot to be sent to the next process. 10A, 10B, 10C (step S5).

From the quality evaluation result, the computer calculates the pulling control range in which the target quality can be obtained (step S6 ). Here, as shown in FIG. 3 , the qualities of the sample wafers SW1 , SW2 , SW3 , and SW4 vary depending on the pulling speed. Specifically, when the pulling speed is high, a void, which is an aggregate of voids, is generated. On the other hand, when the pulling rate is slow, the amount of inter-lattice silicon atoms becomes excessive, and L/DL, which is an aggregate of inter-lattice silicon, is generated.

The pulling speed of the present embodiment is a value obtained by performing a moving average of the pulling speed, and refers to a moving average speed having the highest correlation with the defect distribution in the right graph of FIG. 3 . For example, a time moving average speed in the range of 50 minutes to 200 minutes can be employed. Conversely, in the range of 50 minutes to 200 minutes, there is usually a time moving average speed with the highest correlation.

In this embodiment, the pulling speed is used as an index of the management range, but it is not limited to this, and the present invention can also be applied when the diameter of the straight body of the single crystal silicon 10 is detected and controlled to be constant.

There are two defect-free regions, the Pv region and the Pi region, between the Void region and the L/DL region.

The Pv region refers to a region that contains oxygen precipitation nuclei in an as-grown (grown) state and is prone to generate oxygen precipitates when a two-stage heat treatment of low temperature and high temperature (eg, 800° C. and 1000° C.) is performed. The Pi region refers to a region in which almost no oxygen precipitation nuclei are contained in the as-grown state, and it is difficult to generate oxygen precipitates even if heat treatment is performed.

Regarding the determination of the Pv region or the Pi region, since the precipitation state of the oxygen precipitates after the heat treatment is evaluated, the determination result of the Pv region or the Pi region is affected by the oxygen concentration. As a result, the defect-free range and the new management line described later are affected by the oxygen concentration.

The defect-free region is formed at a crystal growth rate between the crystal growth rate dominated by the OSF region and the crystal growth rate dominated by the L/DL region, and is composed of a cavity dominant region (Pv region) and an interlattice silicon dominant region (Pi region) .

The defect-free crystal pulled at the crystal growth rate of the defect-free region can be said to be a good-quality single crystal silicon with no or very few primary defects such as COP and dislocation clusters. Therefore, it is important to control the pull-up of the single-crystal silicon using the crystal growth rate in the defect-free region in order to ensure the quality of the single-crystal silicon.

In this embodiment, as shown in FIG. 3 , between the region where Void occurs and the region where L/DL occurs, there are Pv regions and Pi regions of sampled wafers SW1 , SW2 , SW3 , and SW4 , that is, defect-free regions. exists, and set the pull-up speed range that becomes the pull-up management range.

In the case of FIG. 3 , the range of the pulling speed of the defect-free region is 5% of the pulling speed in the center of the defect-free region (target value of the ideal pulling speed).

Specifically, the defect distribution evaluation of the sample wafers SW1, SW2, SW3, and SW4 was performed, and the pattern of the Pv region and Pi region in the wafer plane was compared with the defect distribution and the pulling speed shown on the left side of FIG. 3 . The relationship between the actual pulling speed and the upper limit of the defect-free region (the boundary between the OSF region and the Pv region) can be grasped (hereinafter, referred to as the upper defect-free range) and the actual pulling speed relative to the range of the pulling speed. The range of the pulling speed at the lower limit of the defect-free area (the boundary between the Pi area and the L/DL area) (hereinafter, referred to as the lower defect-free area).

That is, when the actual pulling speed is close to the upper limit of the defect-free region (the boundary between the OSF region and the Pv region), the upper defect-free range is set to be small, and the lower defect-free range is set to be larger. On the other hand, when approaching the lower limit of the defect-free region (the boundary between the Pi region and the L/DL region), the upper defect-free range is set larger, and the lower defect-free range is set smaller.

For example, in the present embodiment, in the case of the sample wafer SW1 having only the Pv region, the upper defect-free range is set to 0.5% of the target value of the pulling speed, and the lower defect-free range is set to the pulling speed 4.5% of the target value.

Similarly, in the case of the sample wafer SW2, the upper defect-free range is set to 2.5%, the lower defect-free range is set to 2.5%, and in the case of the sample wafer SW3, the upper defect-free range is set to 3%, the lower defect-free range was set to 2%, and in the case of the sample wafer SW4, the upper defect-free range was set to 4.8%, and the lower defect-free range was set to 0.2%.

When the sample wafers SW1, SW2, SW3, and SW4 generate a predetermined number or more of voids, or when L/DL occurs, it is not necessary to set a pull-up management range, and the generated silicon blocks 10A, 10B, and 10C are regarded as defective products. exclude.

Next, returning to FIG. 2, a new management line is set according to the pull-up management range (step S7). Specifically, from the evaluation result of the defect distribution of the silicon wafers at both ends of the silicon block, the upper defect-free range and the lower defect-free range at the actual pulling speed are grasped. Next, the pulling speed (target value of the ideal speed) corresponding to the center of the defect-free region is grasped.

With regard to the inside of the silicon block, the line connecting the upper limits of the defect-free areas at both ends of the silicon block is set as the new management line on the upper side, and the line connecting the lower limits of the defect-free areas at both ends of the silicon block is set as the new management line on the lower side. Wire. In FIG. 4(B) , the new management line of the upper limit and the new management line of the lower limit are set as straight lines, but it is not limited to this.

Next, returning to FIG. 2, the computer compares the actual pulling data and the pulling management range (step S8).

As shown in FIG. 4(A) , the management line of the conventional pulling speed is set equally in the Void side area and the L/DL side area with respect to the target value of the pulling speed, and the actual value of the pulling speed exceeds the conventional value. In the case of a management line, the silicon blocks 10A, 10B, and 10C are determined to be defective products.

On the other hand, as shown in FIG. 4(B) , regarding the new management line of the pulling speed of the present embodiment, the management line of the pulling speed is changed according to the evaluation results of the obtained sample wafers SW1 , SW2 , SW3 , and SW4 .

As a result, as shown in FIG. 4(B) , the silicon block 10B judged to be a good product under the conventional management line is judged to be at risk of failure under the new management line of the pulling speed of the present embodiment (step S9 ). ).

When it is judged that there is a risk of failure, the silicon block 10B is excluded, and in the next step, the excluded silicon block 10B is divided into a plurality of wafers and then evaluated (step S10 ). In addition, the silicon block 10B determined to be at risk of failure may be discarded as it is.

When it is judged that there is no risk of failure, the silicon block 10B is discharged to the next process.

When the method for judging the quality of the silicon blocks 10A, 10B, and 10C using the computer is completed, when the next pulling of the single crystal silicon 10 is performed, the single crystal silicon is subjected to a new management line based on the calculated pulling speed. 10 lift controls.

[4] Action and effect of the embodiment

In this way, according to the present embodiment, a new line for managing the pull-up speed is calculated from the sample wafers SW1 , SW2 , SW3 , and SW4 that have been subjected to quality evaluation. Therefore, even if the silicon block 10B that has been determined to be not defective in the past is at risk of being determined to be defective, the possibility of sending the defective silicon block 10B to the next process can be reduced, and the next process can be reduced. The frequency of quality confirmation in .

By performing L/DL judgment and Void judgment before calculating the new line of management of the pulling speed, obviously defective silicon blocks 10A, 10B and 10C can be discharged in advance. Therefore, defective products can be eliminated in advance and the quality in the next process can be further reduced. Confirm the frequency.

By executing the quality determination method of the silicon block according to the continuous flow chart shown in FIG. 2 as a program on a computer, automation can be promoted, and the burden of the quality control process itself can be reduced.

By controlling the pulling of the single crystal silicon 10 according to the new management line of the pulling speed set for each silicon block 10A, 10B and 10C, it is possible to prevent the generation of defective silicon blocks 10A, 10B and 10C, thereby reducing the inconvenience. Production of qualified products.

Example

Next, the Example of this invention is demonstrated. In addition, this invention is not limited to an Example.

The results shown in FIG. 5 were obtained as a result of dividing the discharged silicon block 10B into a plurality of wafers and evaluating each wafer.

In the case of managing with the conventional management line, when the lift actually obtained a peak value on the Void side and when the peak value was obtained on the L/DL side, quality evaluation was performed, and a good product and a bad product were judged.

On the other hand, when the new management line is used for management, the determination of the good and bad products of the wafer W1 actually pulled beyond the A1 area and the A2 area actually exceeds the new management line.

In the Void distribution diagram of the wafer W1 in the A1 area, it was confirmed that a ring-shaped Void was generated around the wafer W1.

In the Void distribution diagram of the wafer W1 in the A2 area, it was confirmed that a ring-shaped void was generated in the center and the periphery of the wafer W2.

As a result of the determination of other parts, as shown in FIG. 6 , L/DL was generated in the A3 area, and Void was generated in the A4 area and the A5 area.

Table 1 shows the results of the quality evaluation of the silicon block 10B. In the case of the conventional method, the defective part cannot be extracted unless the quality of all the wafers which obtain the actual peak of the pulling is not evaluated.

On the other hand, in the case of the example, only the wafers that were actually pulled beyond the new management line from the A1 area to the A5 area were evaluated. The results are shown in Table 1.

[Table 1]

In the conventional method, 809 pieces of samples were evaluated for quality, and 22 pieces of defective products were found.

On the other hand, in the examples, 376 samples were evaluated for quality, and 22 defective samples were found to be the same as the conventional method.

From this result, it was confirmed that by executing the quality determination method based on the new management line of the present example, the number of wafers to be re-evaluated for quality among the discharged silicon blocks 10B can be greatly reduced, and the next step can be reduced. The quality evaluation frequency of the process.

Description of reference numerals

1-pulling device, 2-chamber, 3-crucible, 3A-quartz crucible, 3B-graphite crucible, 4-support shaft, 5A-heater, 5B-heater, 6-insulation material, 7-pulling shaft , 8-seed crystal, 9-silicon melt, 10-single crystal silicon, 10A-silicon block, 10B-silicon block, 10C-silicon block, 12-heat shield, 13-gas inlet, 14-exhaust port , SW1-sample wafer, SW2-sample wafer, SW3-sample wafer, SW4-sample wafer, W1-wafer.

Claims (5)

1. A method for judging the quality of a silicon block, which judges the quality of a plurality of silicon blocks cut out from single crystal silicon pulled by a pulling method, wherein the method for judging the quality of the silicon block is characterized by performing: the step of obtaining quality evaluation results of sample wafers cut out from respective ends of the plurality of silicon blocks; The step of obtaining the actual data of the pulling of the single crystal silicon; The step of setting the pull-up management range of each silicon block according to the quality evaluation result of each sample wafer; and A step of judging the quality of each silicon block by comparing the acquired actual pulling data and the set pulling management range. 2. The method for judging the quality of a silicon block according to claim 1, characterized in that: Before the step of setting the management range, if a result showing poor L/DL is obtained in the quality evaluation result of the sample wafer, the step of excluding the silicon block showing the result is performed. 3. The method for judging the quality of a silicon block according to claim 1 or 2, characterized in that: Before the step of setting the management range, if a result showing Void failure is obtained in the quality evaluation result of the sample wafer, the step of excluding the silicon block showing the result is performed. 4. A quality determination program for silicon block, characterized in that, The computer is caused to execute the method for determining the quality of the silicon block according to any one of claims 1 to 3 . 5. a manufacture method of monocrystalline silicon, it is characterized in that performing: The step of causing the computer to execute the quality determination program of the silicon block according to claim 4, and to set the pulling management range when pulling the single crystal silicon; and The step of pulling the single crystal silicon is controlled according to the set pulling management range.

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