CN111505371A - Electronic detonator charging voltage detection circuit system - Google Patents
Electronic detonator charging voltage detection circuit system Download PDFInfo
- Publication number
- CN111505371A CN111505371A CN202010188116.8A CN202010188116A CN111505371A CN 111505371 A CN111505371 A CN 111505371A CN 202010188116 A CN202010188116 A CN 202010188116A CN 111505371 A CN111505371 A CN 111505371A
- Authority
- CN
- China
- Prior art keywords
- transistor
- pin
- electronic detonator
- coupled
- voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000001514 detection method Methods 0.000 title claims abstract description 42
- 239000003990 capacitor Substances 0.000 claims abstract description 45
- 238000004146 energy storage Methods 0.000 claims abstract description 24
- BWSIKGOGLDNQBZ-LURJTMIESA-N (2s)-2-(methoxymethyl)pyrrolidin-1-amine Chemical compound COC[C@@H]1CCCN1N BWSIKGOGLDNQBZ-LURJTMIESA-N 0.000 claims description 9
- 238000006243 chemical reaction Methods 0.000 abstract 1
- 230000008878 coupling Effects 0.000 description 12
- 238000010168 coupling process Methods 0.000 description 12
- 238000005859 coupling reaction Methods 0.000 description 12
- 238000000034 method Methods 0.000 description 5
- 230000005540 biological transmission Effects 0.000 description 4
- 238000005474 detonation Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 239000000843 powder Substances 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 238000013461 design Methods 0.000 description 2
- 239000002360 explosive Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 238000011161 development Methods 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 230000037452 priming Effects 0.000 description 1
- 238000005070 sampling Methods 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
- G01R19/25—Arrangements for measuring currents or voltages or for indicating presence or sign thereof using digital measurement techniques
- G01R19/2503—Arrangements for measuring currents or voltages or for indicating presence or sign thereof using digital measurement techniques for measuring voltage only, e.g. digital volt meters (DVM's)
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Air Bags (AREA)
Abstract
The embodiment of the application discloses electronic detonator charging voltage detection circuitry includes: the circuit comprises an analog-to-digital converter module, a first resistor, a second resistor, a first transistor, a second transistor, a third transistor, a fourth transistor, an inverter and an energy storage capacitor end. By adopting the electronic detonator charging voltage detection circuit system, high-voltage to low-voltage conversion can be carried out, so that a high-voltage signal can be measured by a low-voltage device analog-to-digital converter. The system can accurately measure the high-voltage signal in the circuit, and simultaneously, the self-bias is realized by utilizing the unique structure of the circuit, so that the use of a complex bias circuit is avoided, and the condition that the withstand voltage of a low-voltage device is exceeded is avoided.
Description
Technical Field
The invention relates to the field of electronic detonator design and manufacture, in particular to a charging voltage detection circuit system of an electronic detonator.
Background
In recent years, with the rapid development of scientific technology, electronic detonators have been widely used in engineering work and replace traditional priming systems in many applications. The electronic detonator is a product of combining a detonator and an integrated circuit and mainly comprises an electronic control module, a bridge wire with a powder head, a powder tube or a non-detonating powder tube. Compared with a front detonating tube, the electronic detonator has the characteristics of high-precision delay, safe control, reliable detonation and the like. Before detonation, the external controller supplies power and communicates with the electronic detonator through the bus, so that the operations of encoding, detecting, charging, detonation and the like of the electronic detonator are realized. The ignition head of the electronic detonator generally adopts an external special ignition head device, after the electronic detonator chip is charged, once a detonation instruction is received, an ignition discharge switch is switched on, and the accumulated charges of the electronic detonator can pass through the switch and the ignition head, so that necessary heat is generated on the ignition head to detonate the explosive. If the charge is not accumulated enough, in other words, the voltage on the energy storage capacitor of the electronic detonator is not enough, the current flowing through the ignition head after the discharge switch is opened is not enough to ignite the explosive. Therefore, before discharging, the voltage on the energy storage capacitor needs to be detected to judge whether the detonator can normally detonate. In the production test stage, whether the energy storage capacitor is normally welded or not and whether the chip can be normally charged or not can be judged by detecting the voltage on the energy storage capacitor.
In the prior art, the voltage on the energy storage capacitor can be detected by integrating a comparator or an analog-to-digital converter (ADC) in a chip, and the voltage is sampled or compared with a reference to judge. However, in order to save area and improve performance, the comparator and the analog-to-digital converter in the existing electronic detonator chip are often formed by low-voltage devices. The charging voltage is often high in order to be able to initiate the ignition head. If the high-voltage signal is directly measured, a comparator and an analog-to-digital converter which are composed of low-voltage devices can be damaged, so that how to design a low-cost detection circuit to measure the high-voltage signal and simultaneously avoid the circuit structure of the low-voltage device from being damaged becomes a technical problem which needs to be solved by the technical personnel in the field.
Disclosure of Invention
Therefore, the embodiment of the invention provides a charging voltage detection circuit system for an electronic detonator, which aims to solve the problems that in the prior art, the circuit structure is complex, and overvoltage risks exist in the voltage sampling or comparing process of a low-voltage device, so that the device is damaged.
In order to achieve the above object, the embodiments of the present invention provide the following technical solutions:
the invention provides an electronic detonator charging voltage detection circuit system which comprises an analog-to-digital converter module, a first resistor R1, a second resistor R2, a first transistor MN1, a second transistor MN2, a third transistor MN3, a fourth transistor MP1, an inverter and an energy storage capacitor end, wherein the energy storage capacitor end is a voltage input end of a detection circuit, a first end 1 of the first resistor is coupled with the anode of the energy storage capacitor end, a second end 2 of the first resistor is respectively coupled with a first end 1 of the second resistor and a connection point of a second pin of the first transistor and a second pin of the fourth transistor, a second end 2 of the second resistor is respectively coupled with a second pin of the second transistor and a first pin of the fourth transistor, a third pin of the second transistor is coupled with the cathode of the energy storage capacitor end, a first pin of the second transistor is coupled with an input end of the inverter, a first pin of the first transistor and a connection point of an electronic detonator control signal output terminal L of the electronic detonator, and a third pin of the energy storage capacitor end is coupled with an input end of the third transistor, and a third pin of the third transistor is coupled with the third pin of the energy storage capacitor end of the third transistor, and a third pin of the third transistor are respectively coupled with an input end of the third transistor, and a third pin of the third transistor, and a third pin of the third transistor are coupled with the third transistor, and a third pin of the third transistor, and a.
Further, the first transistor and the second transistor are high voltage NMOS transistors, and the third transistor is a low voltage NMOS transistor.
Further, the fourth transistor is a P-channel high-voltage MOS transistor.
Furthermore, a first pin of the first transistor is a grid electrode, a second pin is a drain electrode, and a third pin is a source electrode; the first pin of the second transistor is a grid electrode, the second pin is a drain electrode, and the third pin is a source electrode; the first pin of the third transistor is a grid electrode, the second pin is a drain electrode, and the third pin is a source electrode.
Furthermore, the first pin of the fourth transistor is a gate, the second pin is a source, and the third pin is a drain.
Further, the output end of the analog-to-digital converter module is coupled with an electronic detonator control module of the electronic detonator.
Further, the negative electrode of the energy storage capacitor end is grounded.
Further, a third pin of the second transistor and a third pin of the third transistor are grounded.
Correspondingly, the application also provides an electronic detonator charging voltage detection circuit system which comprises a comparator, a first resistor R1, a second resistor R2, a first transistor MN1, a second transistor MN2, a third transistor MN3, a fourth transistor MP1, an inverter and a storage capacitor end, wherein the storage capacitor end is a voltage input end of a detection circuit, a first end 1 of the first resistor is coupled with the anode of the storage capacitor end, a second end 2 of the first resistor is coupled with a first end 1 of the second resistor and a connection point of a second pin of the first transistor and a second pin of the fourth transistor respectively, a second end 2 of the second resistor is coupled with a second pin of the second transistor and a first pin of the fourth transistor respectively, a third pin of the second transistor is coupled with the cathode of the storage capacitor end, a first pin of the second transistor is coupled with an input end of the inverter, a first pin of the first transistor and a first pin of the fourth transistor respectively, a third pin of the second transistor is coupled with the cathode of the storage capacitor end, a first pin of the second transistor is coupled with an input end of the inverter, a first pin of the first transistor and a negative pin of the third transistor are coupled with a positive pin of the third transistor, a negative pin of the SAME transistor is coupled with a third pin of the third transistor and a reference transistor, and a negative pin of the third transistor are coupled with a third transistor and a third transistor of the third transistor L of the third transistor, and.
Further, the output end of the comparator is coupled with an electronic detonator control module of the electronic detonator.
The electronic detonator charging voltage detection circuit system can convert high voltage into low voltage so as to realize the measurement of high voltage signals by using a low-voltage device analog-to-digital converter. The system can accurately measure the high-voltage signal in the circuit, and simultaneously, the self-bias is realized by utilizing the unique structure of the circuit, so that the use of a complex bias circuit is avoided, and the condition that the withstand voltage of a low-voltage device is exceeded is avoided.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below. It should be apparent that the drawings in the following description are merely exemplary, and that other embodiments can be derived from the drawings provided by those of ordinary skill in the art without inventive effort.
Fig. 1 is a schematic structural diagram of a first electronic detonator charging voltage detection circuit system provided in an embodiment of the present application;
fig. 2 is a schematic structural diagram of a second electronic detonator charging voltage detection circuit system provided in the embodiment of the present application.
Detailed Description
The present invention is described in terms of particular embodiments, other advantages and features of the invention will become apparent to those skilled in the art from the following disclosure, and it is to be understood that the described embodiments are merely exemplary of the invention and that it is not intended to limit the invention to the particular embodiments disclosed. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
According to the embodiment of the electronic detonator charging voltage detection circuit system, the charging voltage is reduced in a resistance voltage division mode and then is sent to the input of the analog-to-digital converter module or the comparator through the high-voltage transmission gate. The control of the high-voltage transmission gate adopts a self-bias mode to drive the P-channel high-voltage MOS transistor, so that the P-channel high-voltage MOS transistor is prevented from being driven by a complex circuit. The output of the analog-to-digital converter module or the comparator represents the numerical value of the charging voltage, the numerical value is output to the electronic detonator control module, and then the numerical value is fed back to the host equipment through the electronic detonator control module, so that the host equipment is used for judging whether the charging voltage of the energy storage capacitor is normal or not, the damage of a device caused by the overvoltage risk of a low-voltage device is avoided, and the safety and the stability of the low-voltage device are improved.
The detailed description of the embodiment of the present invention will be given based on the first electronic detonator charging voltage detection circuit system described in the present invention, as shown in fig. 1, which is a schematic diagram of the structure of the first electronic detonator charging voltage detection circuit system provided in the present embodiment, the detailed structure of the electronic detonator charging voltage detection circuit system described in the present application at least comprises an analog-to-digital converter module, a first resistor R1, a second resistor R2, a first transistor MN1, a second transistor MN2, a third transistor MN3, a fourth transistor MP1, an inverter I1, and a storage capacitor terminal (i.e. the detection circuit is coupled to one end of a storage capacitor C1), wherein the storage capacitor terminal is a voltage input terminal of the detection circuit, a first terminal 1 of the first resistor R1 is coupled to a positive electrode of the storage capacitor terminal, a second terminal 2 of the first resistor R1 is coupled to a first terminal 2 of the second transistor R2, a connection point 1 of the first transistor MN2 and a second terminal 1 of the first transistor MN2 is coupled to a first terminal of the second transistor MN R369, a connection point of the first transistor MN, a second terminal of the first transistor MN1 is coupled to a negative electrode of the third transistor MN1, a third transistor MN1 is coupled to a third terminal of the third transistor MN1, a third transistor MN 368672, a third transistor MN1 is coupled to a third transistor MN1, a third transistor p 3614, a third transistor p1 is coupled to a third transistor MN1, a third transistor p1 is coupled to a third transistor p 3614, a third transistor p1, a third transistor p 3614 is coupled to a third transistor 3614, a third transistor p1, a third transistor p 3614, a third transistor p 367, a third transistor p1 is coupled to a third transistor 1, a third transistor p 1.
The first transistor and the second transistor are high-voltage NMOS transistors, and the third transistor is a low-voltage NMOS transistor. The fourth transistor MP1 is a P-channel high voltage MOS transistor. Specifically, a first pin of the first transistor MN1 is a gate, a second pin is a drain, and a third pin is a source; a first pin of the second transistor MN2 is a grid electrode, a second pin is a drain electrode, and a third pin is a source electrode; the third transistor MN3 has a first pin serving as a gate, a second pin serving as a drain, and a third pin serving as a source. The first pin of the fourth transistor MP1 is a gate, the second pin is a source, and the third pin is a drain.
Further, the output end of the analog-to-digital converter module is coupled with an electronic detonator control module of the electronic detonator.
The negative electrode of the energy storage capacitor end is grounded, and the third pin of the second transistor MN2 and the third pin of the third transistor MN3 are grounded.
In the specific implementation process, the voltage difference between the poles of the low-voltage MOS transistor cannot exceed the voltage value of the low-voltage power supply, and the absolute values of the gate-source voltage VGS and the substrate (well) -source voltage VBS of most of the high-voltage MOS transistors cannot exceed the voltage value of the low-voltage power supply, but the drain-source voltage VDS, the gate-drain voltage VGD, and the drain-substrate (well) -source voltage VDB of the high-voltage MOS transistor are all tolerant to a predetermined high-voltage. The electronic detonator chip is generally generated by a low-voltage power supply, for a high-voltage NMOS (N-channel high-voltage MOS transistor), a control signal output by a low-voltage control circuit can meet the requirement of a voltage difference of a high-voltage NMOS device, and a PMOS (P-channel MOS transistor) needs to generate a voltage difference relative to a high source voltage to control a grid electrode, so that the high-voltage PMOS (P-channel high-voltage MOS transistor) needs a relatively complex driving circuit.
As shown in fig. 1, in the embodiment of the present invention, the initial SAMP L E signal is logic low, the first transistor MN1 and the second transistor MN2 in the high voltage NMOS are both turned off, the drain of the second transistor MN2 is coupled to the gate of the first transistor MN1, since the second transistor MN2 is turned off, the voltage at this point is equal to the voltage on the energy storage capacitor C1 and is also equal to point a, the fourth transistor MP1 in the high voltage PMOS is also turned off, the SAMP L E signal controls the third transistor MN3 after passing through the inverter I1, so the initial third transistor MN3 is turned on to pull the point B to the same potential as the electronic detonator chip, it can be seen that when the energy storage capacitor C1 is initially uncharged, the voltages at points a and B are also 0, the signal received by the analog-to-digital converter module (ADC) is also 0, there is no risk of damage, and there is no power consumption, the SAMP L E is at the same potential as the electronic detonator chip, the signal of the internal logic potential of the inverter I1 exceeds the internal logic potential, the first transistor MN1 does not damage the high voltage of the high voltage transistor MN2, and the third transistor MN1 is not damaged by the existing transistors.
If the electronic detonator chip has not started to measure the voltage, the SAMP L E signal is still logic low, the first transistor MN1 and the second transistor MN2 are both turned off, the point a is the voltage on the energy storage capacitor C1, the VGS of the third transistor MN3 is a low voltage logic power value, the VGS and the VSB of the second transistor are 0, the VSB and the VGS of the first transistor MN1 are the difference between the voltage at the point B and the chip ground, and the third transistor MN3 is turned on, so the potential at the point B is 0, so the VSB and the VGS of the first transistor MN1 are 0, the VDS of the first transistor MN1 and the VDS of the second transistor MN2 are the tolerable high voltages, the second transistor MN2 is turned off so that the gate of the fourth transistor MP1 is automatically raised to the voltage at the point a, the fourth transistor MN1 is also turned off, the voltages of the fourth transistor MN 39mn 632 and the fourth transistor MP 638 are capable of withstanding high voltage, wherein the first transistor MN 638 is in the first transistor MP 638, the first transistor state.
When the electronic detonator chip needs to sample the voltage of the energy storage capacitor C1, the SAMP L E signal is logic high, the second transistor MN2 is turned on, the third transistor MN3 is turned off, then the grid potential of the fourth transistor MP1 is the electronic detonator chip ground, the potential of the point A is the partial voltage of the voltage on the energy storage capacitor C1 on R1 and R2,
in a practical implementation, by adjusting the values of R1 and R2, when the voltage of the SAMP L E is high, VA may not exceed the low voltage power supply at all times, for example, if the high voltage power supply 24V of the electronic detonator chip, the logic low voltage source is 5V, the energy storage capacitor C1 is charged up to 24V, at this time, R1 may be set to 19K, and R2 may be set to 5K, then the voltage of the B point is equal to that of the a point and may not exceed the low voltage power supply no matter how much the voltage of the energy storage capacitor C1 is charged, because one of the first transistor MN1 and the fourth transistor MP1 of the transmission gate is always turned on, because the voltage of the energy storage capacitor C1 is charged, the absolute value of VGS of the fourth transistor MP1 may not exceed the voltage resistance value of the voltage, which is VSB 0, VDS is 0, and the voltage of the B point may not exceed the low voltage power supply, and the voltage of the first transistor is not exceed the voltage of the third transistor MN 598654, when the voltage of the third transistor MN is sampled by the MOS 54 a, the MOS 27, the MOS resistor p 597, the resistor R8654B point may not be considered as a, and the resistor R597, and the resistor R8654B may not be considered as well as the resistor p 27, and the resistor p 27 may be considered as well as the resistor p 27, and the resistor p 27 may be considered as the resistor p 27.
By adopting the first electronic detonator charging voltage detection circuit system, high voltage can be converted into low voltage, so that a high voltage signal can be measured by a low voltage device analog-to-digital converter. The system can accurately measure the high-voltage signal in the circuit, and simultaneously, the self-bias is realized by utilizing the unique structure of the circuit, so that the use of a complex bias circuit is avoided, and the condition that the withstand voltage of a low-voltage device is exceeded is avoided.
Corresponding to the first electronic detonator charging voltage detection circuit system, the invention also provides a second electronic detonator charging voltage detection circuit system. Similar to the above method embodiment, the description is simple, and for the relevant points, reference may be made to the description of the above method embodiment, and the following description of the electronic detonator charging voltage detection circuit system is only schematic. As shown in fig. 2, the two are respectively a schematic structural diagram of a second electronic detonator charging voltage detection circuit system according to an embodiment of the present invention.
Compared with the first electronic detonator charging voltage detection circuit system, the second electronic detonator charging voltage detection circuit system provided by the invention has the advantages that the analog-to-digital converter module can be replaced by a comparator and then is compared with a reference voltage, specifically, the comparison is carried out on the voltage of a point B and the reference voltage (reference voltage), for example, the point B is connected with the positive input end of the comparator, the reference voltage is connected with the negative input end of the comparator, if the voltage of the point B exceeds the reference voltage, the output logic of the comparator is high, the electronic detonator control module considers that the charging voltage reaches a preset target voltage value, and otherwise, the charging voltage does not reach the preset target voltage value.
The implementation process comprises the steps of coupling a comparator, a first resistor R1, a second resistor R2, a first transistor MN1, a second transistor MN2, a third transistor MN3, a fourth transistor MP1, an inverter I1 and a storage capacitor terminal (i.e. the detection circuit is coupled to one end of a storage capacitor C1), wherein the storage capacitor terminal is a voltage input terminal of a detection circuit, coupling a first terminal 1 of the first resistor R1 to a positive terminal of the storage capacitor terminal, coupling a second terminal 2 of the first resistor R1 to a first terminal 1 of the second resistor R2 and to a connection point of a second pin of the first transistor MN1 and a second pin of the fourth transistor MP1, respectively, coupling a second terminal 2 of the second resistor R2 to a second pin of the second transistor MN2 and a first pin of the fourth transistor MP1, coupling a third terminal of the third transistor R847 to a positive terminal of the third transistor MN2 and a negative terminal of the fourth transistor MP1, coupling a negative terminal of the third transistor MN1 to a negative terminal of the third transistor MN1, coupling a negative terminal of the third transistor MN1 and a negative terminal of the third transistor P1 to a control circuit, coupling a third transistor of the third transistor MN 363636363672, coupling a third transistor, coupling a positive terminal of the third transistor MN1 and a third transistor MN 3636363672 to a third transistor, and a third transistor, coupling a third transistor, and a negative terminal of the third transistor MN 3636363636363636363636363636363672, and a third transistor of the third.
It should be noted that, when the SAMP L E is logic low, the transmission gate is turned off, the point B is high-impedance, and it is easy to receive an external interference coupling high-voltage signal, and the inverter I1 and the third transistor MN3 may connect the point B to the ground voltage of the electronic detonator chip to shield interference at this time.
The second electronic detonator charging voltage detection circuit system can be compared with the reference voltage to judge that the charging voltage reaches the preset target voltage value, avoids overvoltage risks of low-voltage devices, realizes self-bias by using a unique circuit framework, does not need a complex bias circuit, and improves the safety and stability of the low-voltage devices.
Although the invention has been described in detail above with reference to a general description and specific examples, it will be apparent to one skilled in the art that modifications or improvements may be made thereto based on the invention. Accordingly, such modifications and improvements are intended to be within the scope of the invention as claimed.
Claims (10)
1. The electronic detonator charging voltage detection circuit system is characterized by comprising an analog-to-digital converter module, a first resistor, a second resistor, a first transistor, a second transistor, a third transistor, a fourth transistor, an inverter and a storage capacitor end, wherein the storage capacitor end is a voltage input end of a detection circuit, a first end of the first resistor is coupled with a positive electrode of the storage capacitor end, a second end of the first resistor is coupled with a first end of the second resistor and a connection point of a second pin of the first transistor and a second pin of the fourth transistor respectively, a second end of the second resistor is coupled with a second pin of the second transistor and a first pin of the fourth transistor respectively, a third pin of the second transistor is coupled with a negative electrode of the storage capacitor end, a first pin of the second transistor is coupled with an input end of the inverter, a first pin of the first transistor and a signal line SAMP L E output by an electronic detonator control module of the electronic detonator, an output end of the inverter is coupled with a negative electrode of the first pin, a first pin of the inverter is coupled with a connection point of the third pin, and a connection point of the third pin is coupled with the third pin of the third transistor and a connection point of the third transistor is coupled with the third transistor.
2. The electronic detonator charging voltage detection circuitry of claim 1 wherein the first transistor and the second transistor are high voltage NMOS transistors and the third transistor is a low voltage NMOS transistor.
3. The electronic detonator charging voltage detection circuitry of claim 1 wherein the fourth transistor is a P-channel high voltage MOS transistor.
4. The electronic detonator charging voltage detection circuitry of claim 2 wherein the first transistor first pin is a gate, the second pin is a drain, and the third pin is a source; the first pin of the second transistor is a grid electrode, the second pin is a drain electrode, and the third pin is a source electrode; the first pin of the third transistor is a grid electrode, the second pin is a drain electrode, and the third pin is a source electrode.
5. The electronic detonator charging voltage detection circuitry of claim 3 wherein the fourth transistor first pin is a gate, the second pin is a source, and the third pin is a drain.
6. The electronic detonator charging voltage detection circuitry of claim 1 wherein the output of the analog-to-digital converter module is coupled to an electronic detonator control module of the electronic detonator.
7. The electronic detonator charging voltage detection circuitry of claim 1 wherein a negative electrode of the energy storage capacitor terminal is grounded.
8. The electronic detonator charging voltage detection circuitry of claim 1 wherein the third pin of the second transistor and the third pin of the third transistor are grounded.
9. The electronic detonator charging voltage detection circuit system is characterized by comprising a comparator, a first resistor, a second resistor, a first transistor, a second transistor, a third transistor, a fourth transistor, an inverter and a storage capacitor end, wherein the storage capacitor end is a voltage input end of a detection circuit, a first end of the first resistor is coupled with a positive electrode of the storage capacitor end, a second end of the first resistor is coupled with a first end of the second resistor and a connection point of a second pin of the first transistor and a second pin of the fourth transistor respectively, a second end of the second resistor is coupled with a second pin of the second transistor and a first pin of the fourth transistor respectively, a third pin of the second transistor is coupled with a negative electrode of the storage capacitor end, a first pin of the second transistor is coupled with an input end of the inverter, a first pin of the first transistor and a signal line SAMP L E output by an electronic detonator control module of the electronic detonator, an output end of the inverter is coupled with a negative electrode of the third transistor, a first pin of the inverter is coupled with a positive electrode of the third transistor, a negative electrode of the third transistor is coupled with a connection point of the third transistor, and a reference voltage of the third transistor is coupled with a negative electrode of the third transistor respectively.
10. The electronic detonator charging voltage detection circuitry of claim 9 wherein the output of the comparator is coupled to an electronic detonator control module of the electronic detonator.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010188116.8A CN111505371B (en) | 2020-03-17 | 2020-03-17 | Electronic detonator charging voltage detection circuit system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010188116.8A CN111505371B (en) | 2020-03-17 | 2020-03-17 | Electronic detonator charging voltage detection circuit system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN111505371A true CN111505371A (en) | 2020-08-07 |
| CN111505371B CN111505371B (en) | 2020-12-29 |
Family
ID=71871618
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010188116.8A Active CN111505371B (en) | 2020-03-17 | 2020-03-17 | Electronic detonator charging voltage detection circuit system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN111505371B (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4712477A (en) * | 1985-06-10 | 1987-12-15 | Asahi Kasei Kogyo Kabushiki Kaisha | Electronic delay detonator |
| US20060042494A1 (en) * | 2004-08-30 | 2006-03-02 | Lucas James D | Fuze with electronic sterilization |
| CN101338996A (en) * | 2008-06-04 | 2009-01-07 | 北京铱钵隆芯科技有限责任公司 | Electronic detonator control chip and its connection reliability checking method |
| CN106440978A (en) * | 2016-11-23 | 2017-02-22 | 中国电子科技集团公司第五十四研究所 | Electronic detonator bridge-wire detecting circuit and method |
| CN109029165A (en) * | 2018-09-04 | 2018-12-18 | 江苏众芯邦软件科技有限公司 | A kind of the detonator circuit and test method of electronic delay control |
-
2020
- 2020-03-17 CN CN202010188116.8A patent/CN111505371B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4712477A (en) * | 1985-06-10 | 1987-12-15 | Asahi Kasei Kogyo Kabushiki Kaisha | Electronic delay detonator |
| US20060042494A1 (en) * | 2004-08-30 | 2006-03-02 | Lucas James D | Fuze with electronic sterilization |
| CN101338996A (en) * | 2008-06-04 | 2009-01-07 | 北京铱钵隆芯科技有限责任公司 | Electronic detonator control chip and its connection reliability checking method |
| CN106440978A (en) * | 2016-11-23 | 2017-02-22 | 中国电子科技集团公司第五十四研究所 | Electronic detonator bridge-wire detecting circuit and method |
| CN109029165A (en) * | 2018-09-04 | 2018-12-18 | 江苏众芯邦软件科技有限公司 | A kind of the detonator circuit and test method of electronic delay control |
Also Published As
| Publication number | Publication date |
|---|---|
| CN111505371B (en) | 2020-12-29 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP5718478B2 (en) | Lithium battery protection circuit | |
| EP2698969B1 (en) | Electronic device having usb interface and usb communication start method thereof | |
| US9350180B2 (en) | Load switch having load detection | |
| US8242747B2 (en) | Charging control circuit capable of constant current charging | |
| CN102025263B (en) | Power supply starting detection circuit | |
| US10090689B2 (en) | Overcurrent protection circuit and method for limiting discharge current of battery within safety limiting value | |
| CN102832651A (en) | System and method for battery management used in battery pack | |
| US20110101918A1 (en) | Battery state monitoring circuit and battery device | |
| US10483753B2 (en) | Embedded battery protection system | |
| US20110215765A1 (en) | Protection circuit and battery pack | |
| US9203119B2 (en) | Battery device | |
| US8524385B2 (en) | Battery pack | |
| US6842063B2 (en) | Analog switch circuit | |
| CN110417087A (en) | A kind of charging chip | |
| CN104979804B (en) | A kind of output overvoltage protection circuit | |
| CN107181395A (en) | A kind of adjustable control circuit of ON time | |
| CN111735354A (en) | Electronic detonator ignition head reliability detection circuit, method and chip | |
| CN115622183B (en) | Control circuit for preventing hot plug during charging of high-voltage lithium battery | |
| CN111505371B (en) | Electronic detonator charging voltage detection circuit system | |
| CN104022490A (en) | Lithium battery protection system and over-current direction circuit thereof | |
| CN205594056U (en) | Anti -interference low voltage detect device | |
| KR19990083573A (en) | Delay circuit | |
| JP2009183050A (en) | Battery pack | |
| CN114362287B (en) | Battery 0V charge inhibition circuit and battery protection circuit | |
| US9042066B2 (en) | Output stage with short-circuit protection |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20231009 Address after: Building 6, Electronic Information Industry Incubation Park, Gui'an New District, Guiyang City, 550000, Guizhou Province Patentee after: GUIZHOU QAML OF SCIENCE AND TECHNOLOGY CO.,LTD. Address before: Room 410, South Building, building 1, 350 Chunxiao Road, China (Shanghai) pilot Free Trade Zone, Pudong New Area, Shanghai, 200120 Patentee before: Shanghai weifuer Semiconductor Co.,Ltd. |
|
| TR01 | Transfer of patent right |