CN111435645B - Semiconductor structures and methods of forming them - Google Patents

Abstract

A semiconductor structure and a method for forming the same, the method for forming the same includes: forming a substrate, wherein the substrate comprises a substrate, a fin part protruding out of the substrate and a grid structure crossing the fin part, and the grid structure covers part of the top and part of the side wall of the fin part; forming a side wall layer on the side surface of the fin part exposed by the grid structure; removing the fin part with partial thickness to form an opening surrounded by the side wall layer and the rest fin part; forming a bottom source-drain doped layer in the opening; removing part of the side wall layer; and forming a top source drain doping layer, covering the top and the side walls of the bottom source drain doping layer exposed by the residual side wall layer, wherein the top source drain doping layer and the bottom source drain doping layer form a source drain doping layer, the doping ion types of the top and the bottom source drain doping layers are the same, and the ion doping concentration in the top source drain doping layer is greater than that in the bottom source drain doping layer. The embodiment of the invention is beneficial to improving the short channel effect, reducing the contact resistance of the contact hole plug and the source-drain doped layer and improving the electrical property of the semiconductor structure.

Description

Semiconductor structures and methods of forming them

Technical field

Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a forming method thereof.

Background technique

With the gradual development of semiconductor process technology, the development trend of semiconductor process nodes following Moore's Law continues to decrease. In order to adapt to the reduction of process nodes, the channel length of MOSFET field effect transistors has also been shortened accordingly. However, as the channel length of the device shortens, the distance between the source and drain of the device also shortens. Therefore, the gate's ability to control the channel becomes worse, and it becomes more difficult for the gate voltage to pinch off the channel. is getting larger and larger, making it easier for the subthreshold leakage phenomenon, the so-called short-channel effects (SCE), to occur.

Therefore, in order to better adapt to the requirements of device size scaling down, semiconductor technology has gradually begun to transition from planar MOSFETs to three-dimensional devices with higher efficiency, such as fin field effect transistors (FinFETs). In FinFET, the gate can at least control the ultra-thin body (fin) from both sides. Compared with planar MOSFET, the gate has stronger control over the channel and can well suppress the short channel effect; and FinFET Compared with other devices, it has better compatibility with existing integrated circuit manufacturing.

Contents of the invention

The problem solved by embodiments of the present invention is to provide a semiconductor structure and a method for forming the same to improve the electrical performance of the semiconductor structure.

In order to solve the above problems, embodiments of the present invention provide a method for forming a semiconductor structure, including: forming a substrate, the substrate includes a substrate, a fin protruding from the substrate, and a gate across the fin. structure, the gate structure covers part of the top and part of the sidewall of the fin; a sidewall layer is formed on the side of the fin exposed by the gate structure; part of the thickness of the fin is removed to form a sidewall layer and an opening surrounded by the remaining fins; forming a bottom source-drain doped layer in the opening; removing part of the height of the sidewall layer in a direction perpendicular to the substrate surface; forming a top source-drain doped layer , covering the top and side walls of the bottom source-drain doped layer exposed by the remaining sidewall layer, the top source-drain doped layer and the bottom source-drain doped layer constitute a source-drain doped layer, the top source-drain doped layer The type of doping ions in the layer is the same as that in the bottom source-drain doping layer, and the doping concentration of ions in the top source-drain doping layer is greater than the doping concentration of ions in the bottom source-drain doping layer.

Correspondingly, embodiments of the present invention also provide a semiconductor structure, including: a substrate; a fin protruding from the substrate; a gate structure spanning the fin and covering part of the top of the fin; Part of the sidewall; a source-drain doped layer located in the fins on both sides of the gate structure. The source-drain doped layer includes a bottom source-drain doped layer and covers the top and part of the side of the bottom source-drain doped layer. The top source-drain doping layer of the wall, the doping ion type in the top source-drain doping layer and the bottom source-drain doping layer is the same, and the ion doping concentration in the top source-drain doping layer is greater than that of the bottom source-drain doping layer. The ion doping concentration of the drain doped layer.

Compared with the existing technology, the technical solutions of the embodiments of the present invention have the following advantages:

The source-drain doped layer in the embodiment of the present invention includes a bottom source-drain doped layer and a top source-drain doped layer covering its top and part of the sidewalls. The doping concentration of ions in the top source-drain doped layer is greater than that of the bottom source-drain doped layer. The doping concentration of ions in the doped layer, in order to make the overall doping concentration of the source-drain doped layer meet the electrical requirements, is different from only forming the bottom source-drain doped layer and making the ions in the bottom source-drain doped layer Compared with solutions with higher doping concentrations, embodiments of the present invention can appropriately reduce the ion doping concentration in the bottom source-drain doped layer, which is beneficial to reducing the flow of doped ions in the bottom source-drain doped layer into the channel region. The probability of diffusion is beneficial to improve the short channel effect.

Moreover, the inversion layer is usually formed in an area close to the top of the fin to form a conductive channel. The gate structure has weak control over the bottom of the fin, and the probability of forming an inversion layer in the bottom of the fin is low. The probability of problems such as leakage current and short channel effect is relatively high. Compared with the solution in which all sidewalls of the bottom source-drain doped layer are covered by the top source-drain doped layer, in this embodiment, the bottom The bottom of the source-drain doped layer is not covered by the top source-drain doped layer, which is beneficial to the formation method improving the short channel effect more significantly; in addition, compared with the solution of only forming the bottom source-drain doped layer In comparison, the embodiment of the present invention increases the surface area of the source-drain doped layer through the top source-drain doped layer, thereby increasing the size of the contact hole plug and the source-drain doped layer that are subsequently electrically connected to the source-drain doped layer. The contact area is large, and the concentration of the top source-drain doped layer is relatively large, which is beneficial to reducing the contact resistance of the contact hole plug and the source-drain doped layer, and improving the electrical performance of the semiconductor structure.

Description of drawings

Figures 1 to 7 are structural schematic diagrams corresponding to each step in a method for forming a semiconductor structure;

8 to 20 are structural schematic diagrams corresponding to each step in a method for forming a semiconductor structure according to an embodiment of the present invention.

Detailed ways

Devices currently formed still suffer from poor performance. Now, the reasons for poor device performance are analyzed based on a method of forming a semiconductor structure.

Referring to FIGS. 1 to 7 , a schematic structural diagram corresponding to each step in a method for forming a semiconductor structure is shown.

With reference to FIGS. 1 to 3 , a perspective view of the semiconductor structure, a cross-sectional view in the aa1 direction in FIG. 1 and a cross-sectional view in the bb1 direction in FIG. 1 are respectively shown. Forming a substrate, the substrate includes a substrate 1, a discrete fin 2 protruding from the substrate 1, and a gate structure 3 across the fin 2, the gate structure 3 covering the fin 2 part of the top and part of the side wall.

Referring to FIG. 4 , a sidewall layer 4 is formed on the side of the fin 2 exposed by the gate structure 3 .

Referring to FIG. 5 , the thickness of the fin portion 2 on both sides of the gate structure 3 is removed, forming an opening 5 surrounded by the sidewall layer 4 and the remaining fin portion 2 .

Referring to FIG. 6 , a source-drain doping layer 6 is formed in the opening 5 .

Referring to Figure 7, the sidewall layer 4 is removed; after the sidewall layer 4 is removed, a contact hole plug 7 electrically connected to the source and drain doped layer 6 is formed, and the contact hole plug 7 covers the The top and sidewalls of the source and drain doped layer 6.

In the semiconductor field, in order to reduce the contact resistance between the source-drain doped layer 6 and the contact hole plug 7 and improve the carrier mobility and other electrical properties of the semiconductor structure, the ion doping concentration of the source-drain doped layer 6 is usually If the value is higher, the doping ions in the source-drain doping layer 6 have a greater probability of lateral diffusion to the channel region, so the short channel effect is easily worsened, resulting in poor electrical performance of the formed semiconductor structure.

In order to solve the technical problem described above, the source-drain doped layer in the embodiment of the present invention includes a bottom source-drain doped layer and a top source-drain doped layer covering its top and part of the sidewalls. The ions in the top source-drain doped layer The doping concentration is greater than the doping concentration of ions in the bottom source-drain doped layer. In order to make the overall doping concentration of the source-drain doped layer meet the electrical requirements, it is better to only form the bottom source-drain doped layer and make the bottom source Compared with the solution in which the ion doping concentration in the drain doping layer is relatively high, the embodiments of the present invention can appropriately reduce the ion doping concentration in the bottom source and drain doping layer, which is beneficial to reducing the ion doping concentration in the bottom source and drain doping layer. The probability of doping ions diffusing into the channel region is beneficial to improving the short channel effect.

Moreover, the inversion layer is usually formed in an area close to the top of the fin to form a conductive channel. The gate structure has weak control over the bottom of the fin, and the probability of forming an inversion layer in the bottom of the fin is low. The probability of problems such as leakage current and short channel effect is relatively high. Compared with the solution in which all sidewalls of the bottom source-drain doped layer are covered by the top source-drain doped layer, in this embodiment, the bottom The bottom of the source-drain doped layer is not covered by the top source-drain doped layer, which is beneficial to making the formation method more effective in improving the short channel effect.

In addition, compared with the solution of only forming the bottom source-drain doped layer, the embodiment of the present invention increases the surface area of the source-drain doped layer through the top source-drain doped layer, thereby increasing the subsequent connection with the source-drain doped layer. The contact area of the contact hole plug and the source-drain doping layer that is electrically connected to the impurity layer, and the concentration of the top source-drain doping layer is relatively large, which is beneficial to reducing the contact hole plug and the source-drain doping layer. The contact resistance of the layers improves the electrical performance of the semiconductor structure.

In order to make the above objects, features and advantages of the embodiments of the present invention more obvious and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

8 to 20 are structural schematic diagrams corresponding to each step in a method for forming a semiconductor structure according to an embodiment of the present invention.

With reference to FIGS. 8 to 10 , a perspective view of the semiconductor structure, a cross-sectional view along the AA1 direction in FIG. 8 , and a cross-sectional view along the BB1 direction in FIG. 8 are respectively shown. Forming a substrate, the substrate includes a substrate 100, separate fins 110 protruding from the substrate 100, and a gate structure 114 spanning the fins 110, the gate structure 114 covering the fins Part of the top and part of the side wall of 110.

The substrate 100 is used to provide a process platform for subsequent formation of semiconductor structures.

In this embodiment, the substrate 100 is a silicon substrate. In other embodiments, the material of the substrate can also be other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium. The substrate can also be a silicon substrate on an insulator or an insulator. on germanium substrates and other types of substrates.

The fin portion 110 is used to subsequently provide a conductive channel for the fin field effect transistor.

In this embodiment, the fin portion 110 and the substrate 100 are obtained by etching the same semiconductor layer. In other embodiments, the fin portion may also be a semiconductor layer grown epitaxially on the substrate, thereby achieving the purpose of accurately controlling the height of the fin portion.

Therefore, in this embodiment, the material of the fin portion 110 is the same as the material of the substrate 100 , and the material of the fin portion 110 is silicon. In other embodiments, the material of the fins may also be germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium.

It should be noted that the substrate also includes an isolation layer 111 , which is located on the substrate 100 where the fins 110 are exposed and covers part of the sidewalls of the fins 110 . The isolation layer 111 is used to electrically isolate adjacent devices.

In this embodiment, the material of the isolation layer 111 is silicon oxide. In other embodiments, the material of the isolation layer may also be an insulating material such as silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, or silicon oxycarboxynitride.

In this embodiment, the gate structure 114 includes a gate oxide layer 112 (shown in FIG. 10 ) and a gate layer 113 (shown in FIG. 10 ) located on the gate oxide layer 112 .

The gate oxide layer 112 is made of silicon oxide or silicon oxynitride, and the gate layer 113 is made of polysilicon, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, or silicon nitride oxycarbon. or amorphous carbon. In this embodiment, the material of the gate oxide layer 112 is silicon oxide, and the material of the gate layer 113 is polysilicon.

In other embodiments, the gate structure may also be a metal gate structure.

In this embodiment, the gate oxide layer 112 also covers the surface of the fin 110 exposed by the gate layer 113 . It should be noted that, for convenience of illustration and description, in this embodiment, FIG. 8 only illustrates the gate layer 113 in the gate structure 114 .

In this embodiment, a pad oxide layer (pad oxide) 115 (as shown in FIG. 10 ) and a gate mask layer 116 (as shown in FIG. 10 ) located on the pad oxide layer 115 are also formed on the top of the gate structure 114 . shown).

The gate mask layer 116 is used as an etching mask to form the gate layer 113 and can also protect the top of the gate layer 113 in subsequent processes. In this embodiment, the material of the gate mask layer 116 is silicon nitride.

The pad oxide layer 115 is used to play a stress buffering role when forming the gate mask layer 116 and using the gate mask layer 116 as a mask to form the gate layer 113, thereby improving the gate mask layer. The adhesion between the film layer 116 and the gate layer 113 avoids the problem of dislocation caused by direct contact between the gate mask layer 116 and the gate layer 113 . In this embodiment, the material of the pad oxide layer 115 is silicon oxide.

Continuing to refer to FIG. 10 , in this embodiment, the forming method further includes: after forming the substrate, forming a first layer on the sidewalls of the gate layer 113 , the pad oxide layer 115 and the gate mask layer 116 . Side walls 118.

The first spacers 118 are used to protect the sidewalls of the gate layer 113 in subsequent processes. The formation method may further include a low-doping drain ion implantation process, and the first spacer serves as an offset spacer and is also used to define an implantation region of the low-doping drain ion implantation process.

In this embodiment, the first spacer 118 is made of silicon nitride. In other embodiments, the material of the first side wall can also be silicon oxide, silicon oxynitride, silicon carbide, silicon oxycarbide or silicon oxynitride.

Referring to FIG. 11 , after forming the first spacers 118 , the forming method further includes: removing the first spacers 118 to expose the gate oxide layer 112 on the surface of the fin 110 . By removing the gate oxide layer 112 on the surface of the first sidewall 118 exposing the fin 110 , it is beneficial to simplify the subsequent process of forming the sidewall layer and etching the fin 110 and the sidewall layer.

In other embodiments, according to actual process requirements, the gate oxide layer located on the exposed fin surface of the first spacer may also be retained.

Referring to FIGS. 12 to 15 , a sidewall layer 125 is formed on the side of the fin 110 exposed by the gate structure 114 (as shown in FIG. 15 ).

The sidewall layer 125 is used to define a subsequent formation region of the bottom source and drain doped layer along a direction perpendicular to the extending direction of the fin 110 . In this embodiment, the material of the sidewall layer 125 is silicon nitride. In other embodiments, the material of the sidewall layer may also be silicon carbonitride, boron silicon nitride, or silicon oxynitride.

Specifically, the step of forming the sidewall layer 125 includes:

Referring to FIGS. 12 to 13 , FIG. 12 is a cross-sectional view based on FIG. 11 , and FIG. 13 is a cross-sectional view of FIG. 12 along the direction perpendicular to the extension of the fins. The surface of the fins 110 exposed on the first side wall 118 and the isolation A layer 120 of sidewall material is formed on layer 111 .

The sidewall material layer 120 is used to subsequently form a sidewall layer. In this embodiment, the sidewall material layer 120 is formed using an atomic layer deposition (ALD) process.

The atomic layer deposition process has good conformal coverage capability. Therefore, with reference to FIG. 12 , in this embodiment, the sidewall material layer 120 is also formed on top of the gate mask layer 116 and the first sidewall 118 , and on the sidewalls of the first sidewalls 118. Moreover, the deposition uniformity of the atomic layer deposition process is good, which is beneficial to improving the thickness uniformity of the sidewall material layer 120, and correspondingly improves the thickness uniformity of subsequent sidewall layers.

With reference to FIGS. 14 and 15 , the sidewall material layer 120 on the top of the fin 110 is removed to form the sidewall layer 125 .

It should be noted that in this embodiment, in the step of removing the sidewall material layer 120 on top of the fin 110, the gate mask layer 116 and the sidewall material layer 120 on top of the first sidewall 118 are also removed, leaving only The sidewall material layer 120 on the sidewall of the first sidewall 118 serves as the second sidewall 119.

The second spacers 119 are used to protect the sidewalls of the gate layer 113 in subsequent processes. The second spacers 119 are also used to define the formation of subsequent source and drain doped layers along the extension direction of the fins 110 area.

By forming the second sidewall 119 in the step of forming the sidewall layer 125, it is beneficial to simplify the process flow.

Therefore, in this embodiment, the second spacer 119 and the sidewall layer 125 are made of the same material, and the material of the second spacer 119 is silicon nitride. In other embodiments, the material of the second sidewall can also be different from the material of the sidewall layer. The material of the second sidewall can also be silicon oxide, silicon oxynitride, silicon carbide, or silicon oxycarbide. Or silicon oxynitride.

In this embodiment, a dry etching process is used to remove the sidewall material layer 120 on the top of the fin 110 .

It should also be noted that in this embodiment, during the step of removing the sidewall material layer 120 on top of the fin portion 110 and the gate mask layer 116 and the first sidewall 118 , the sidewall material layer 120 located on the top of the gate mask layer 116 and the first sidewall 118 is also removed. Sidewall material layer 120 on isolation layer 111 .

In other embodiments, the sidewall material layer located on the isolation layer can also be retained. The sidewall material layer located on the isolation layer can also support the sidewall layer on the side of the fin, thereby helping to reduce subsequent etching. During the steps of fins and sidewall layers, the probability that the sidewall layer will tilt or fall off. Specifically, a protective layer can be formed on the sidewall material layer located on the isolation layer. Using the protective layer as a mask, remove the sidewall material layer on top of the fin, the gate mask layer and the top of the first sidewall, and remove the sidewall material layer on the isolation layer. The layer of sidewall material on the layer is retained under the protection of the protective layer.

Referring to FIG. 16 , part of the thickness of the fin 110 is removed, forming an opening 200 surrounded by the sidewall layer 125 and the remaining fin 110 .

The opening 200 is used to provide a spatial location for the subsequent formation of the bottom source and drain doped layer.

Specifically, the step of forming the opening 200 includes: using a dry etching process to remove part of the thickness of the fin portion 110 to form the opening 200 surrounded by the sidewall layer 125 and the remaining fin portion 110 . The dry etching process has better etching profile controllability, which is conducive to making the shape of the opening 200 meet process requirements.

Referring to FIG. 17 , a bottom source-drain doping layer 131 is formed within the opening 200 (shown in FIG. 16 ).

The bottom source-drain doping layer 131 is used for subsequent formation of the source-drain doping layer, and the bottom source-drain doping layer 131 is also used to provide a process platform for the subsequent formation of the top source-drain doping layer.

The subsequent process also includes removing part of the height of the sidewall layer 125; forming a top source-drain doped layer on the top and side walls of the bottom source-drain doped layer 131 exposed by the remaining sidewall layer 125, and the top source-drain doped layer is The doped layer and the bottom source-drain doped layer 131 constitute a source-drain doped layer. In order to make the overall doping concentration of the source-drain doped layer meet the electrical requirements, compared with the solution of only forming the bottom source-drain doped layer and making the ion doping concentration in the bottom source-drain doped layer higher , in this embodiment, the ion doping concentration in the bottom source-drain doped layer 131 can be appropriately reduced, which is beneficial to reducing the probability of doped ions in the bottom source-drain doped layer 131 diffusing to the channel region, thereby helping to improve short-term operation. channeling effect.

Therefore, in this embodiment, the ion doping concentration in the bottom source-drain doping layer 131 should not be too low or too high. If the ion doping concentration in the bottom source-drain doping layer 131 is too low, the overall doping concentration of the subsequent source-drain doping layer may be difficult to meet the electrical requirements; if the ion doping concentration in the bottom source-drain doping layer 131 is too high High, the probability of doping ions in the bottom source-drain doping layer 131 to diffuse to the channel region is high, which is not conducive to improving the short channel effect of the semiconductor structure. To this end, in this embodiment, the semiconductor structure is used to form an NMOS transistor, and the bottom source and drain doping layer 131 is doped with N-type ions, and the doping concentration of the N-type ions is 3.0E20 atoms per cubic centimeter to 8.0E21 atoms per cubic centimeter. In other embodiments, when the semiconductor structure is used to form a PMOS transistor, the bottom source-drain doping layer is doped with P-type ions, and the doping concentration of P-type ions ranges from 1.0E20 atoms per cubic centimeter to 4.0E20 atoms per cubic centimeter. cubic centimeters.

Specifically, in this embodiment, an in-situ self-doping process is used to form the bottom source and drain doped layer 131, that is, an epitaxial process is used to form an epitaxial layer (not shown) in the opening 200, and after forming the During the process of the epitaxial layer, the bottom source and drain doped layer 131 is formed by in-situ self-doping ions. The in-situ self-doping process is a commonly used process in the semiconductor field to form source and drain doped layers, and has high process compatibility.

Therefore, in this embodiment, the semiconductor structure is used to form an NMOS transistor. The bottom source-drain doped layer 131 includes an epitaxial layer doped with N-type ions. The material of the epitaxial layer can be Si or SiC, thereby forming the NMOS transistor. The channel region provides tensile stress, which is beneficial to improving the carrier mobility of the NMOS transistor. Among them, the N-type ions are P ions, As ions or Sb ions. In other embodiments, when the semiconductor structure is used to form a PMOS transistor, the bottom source-drain doping layer includes an epitaxial layer doped with P-type ions. The material of the epitaxial layer can be Si or SiGe, thereby forming a channel for the PMOS transistor. The channel region provides compressive stress, which is beneficial to improving the carrier mobility of the PMOS transistor, in which the P-type ions are B ions, Ga ions or In ions.

Referring to FIG. 18 , part of the height of the sidewall layer 125 is removed in a direction perpendicular to the surface of the substrate 100 .

By removing part of the height of the sidewall layer 125 , part of the sidewall of the bottom source-drain doped layer 131 is exposed, and the top and sides of the bottom source-drain doped layer 131 are subsequently exposed on the remaining sidewall layer 125 . The walls form the top source and drain doped layers to provide the basis for the process.

Moreover, the inversion layer is usually formed in an area close to the top of the fin 110 to form a conductive channel. The gate structure 114 has weak control over the bottom of the fin 110 and the probability of forming an inversion layer in the bottom of the fin 110 is low. , the probability of problems such as leakage current and short channel effect at the bottom of the fin 110 is relatively high. Compared with the solution of completely removing the sidewall layer, in this embodiment, only a part of the height of the sidewall layer 125 is removed, leaving The partial sidewall layer 125 located on the bottom sidewall of the bottom source-drain doped layer 131 prevents the bottom of the bottom source-drain doped layer 131 from being covered by the top source-drain doped layer, which is beneficial to the formation method. The effect of improving the short channel effect is more significant.

Therefore, in this embodiment, after removing part of the height of the sidewall layer 125 , the height of the remaining sidewall layer 125 should not be too small, nor should it be too large. If the height of the remaining sidewall layer 125 is too small, the subsequent top source-drain doped layer will be too close to the bottom of the fin 110, and the doped ions in the top source-drain doped layer will have a higher probability of diffusing into the bottom of the fin 110, and will not It is beneficial to improve the short channel effect; if the height of the remaining sidewall layer 125 is too large, the volume and surface area of the top source-drain doped layer will be too small, which will easily make it difficult to meet the overall doping concentration of the subsequent source-drain doped layer. Electrical requirements, for example, the contact area between the top source-drain doped layer and subsequent contact hole plugs is too small, which can easily cause the contact resistance between the source-drain doped layer and the contact hole plug to be too large, and the top source-drain doped layer Too small a volume can easily lead to too little stress in the source and drain doped layers, which is not conducive to improving the carrier mobility of the semiconductor structure. For this reason, in this embodiment, after part of the height of the sidewall layer 125 is removed, the height of the remaining sidewall layer 125 is 15 nm to 25 nm.

In this embodiment, a dry etching process is used to remove part of the thickness of the sidewall layer 125 . The use of dry etching process is conducive to controlling the ratio of lateral etching and longitudinal etching, thereby improving the anisotropy of the etching process, which is conducive to making the etching amount of the sidewall layer 125 meet process requirements, and is also conducive to reducing the In the process of removing part of the thickness of the sidewall layer 125, other film layer structures such as the bottom source and drain doped layer 131 are affected.

It should be noted that the bias voltage of the dry etching process should not be too small or too large. If the bottom bias voltage is too small, it is easy to reduce the anisotropy of the dry etching process, causing the dry etching process to also laterally etch the sidewall layer 125; if the bias voltage is too high, If it is large, it is easy to cause over-etching of the sidewall layer 125, resulting in the height of the remaining sidewall layer 125 being too small. For this reason, in this embodiment, the bias voltage of the dry etching process is 80V to 250V.

Correspondingly, the etching power of the dry etching process should not be too small or too large. In this embodiment, the etching power of the dry etching process is 100W to 400W.

It should also be noted that the etching time of the dry etching process should not be too short or too long. If the etching time is too short, the etching amount of the sidewall layer 125 may be difficult to meet process requirements; if the etching time is too long, the sidewall layer 125 may be easily over-etched, and the etching amount of the sidewall layer 125 may be easily over-etched. Reduce production capacity. For this reason, in this embodiment, the etching time of the dry etching process is 10S to 200S.

In addition, the process pressure of the dry etching process should not be too low or too high. If the process pressure is too low, it is easy to reduce the etching rate, and accordingly the manufacturing efficiency is reduced; if the process pressure is too high, it is easy to reduce the process stability, and it is easy to reduce the etching uniformity of the dry etching process. In addition, , too high process pressure can easily lead to an increase in production costs. For this reason, in this embodiment, the process pressure of the dry etching process is 10 mtorr to 200 mtorr.

Referring to Figure 19, a top source-drain doped layer 132 is formed to cover the top and side walls of the bottom source-drain doped layer 131 exposed by the remaining sidewall layer 125. The top source-drain doped layer 132 and the bottom source-drain doped layer 132 are Layer 131 constitutes a source-drain doped layer 130, the top source-drain doped layer 132 has the same type of doping ions as the bottom source-drain doped layer 131, and the ions in the top source-drain doped layer 132 have the same type. The doping concentration is greater than the doping concentration of ions in the bottom source-drain doping layer 131 .

By making the ion doping concentration in the top source-drain doping layer 132 larger, it is beneficial to make the overall doping concentration of the source-drain doping layer 130 meet electrical requirements. Moreover, by making the doping concentration in the bottom source-drain doped layer 131 smaller, and the top source-drain doped layer 132 only covering the sidewalls of the bottom source-drain doped layer 131 exposed by the sidewall layer 125, the top source-drain doped layer 131 is The probability that the doped ions in the layer 132 will diffuse into the bottom of the fin portion 110 is low, which is conducive to making the formation method more effective in improving the leakage current and short channel effect at the bottom of the fin portion 110 .

In addition, compared with the solution of only forming the bottom source-drain doped layer, this embodiment increases the surface area of the source-drain doped layer 130 through the top source-drain doped layer 132, thereby increasing the subsequent connection with the source-drain doped layer. The contact area of the contact hole plug and the source-drain doped layer 130 that the doped layer 130 is electrically connected to, and the concentration of the top source-drain doped layer 132 is relatively large, which is beneficial to reducing the contact hole plug and the The contact resistance of the source-drain doped layer 130 improves the electrical performance of the semiconductor structure.

Specifically, the step of forming the top source-drain doped layer 132 includes: performing epitaxial growth on the surface of the bottom source-drain doped layer 131 where the remaining sidewall layer 125 is exposed, to form an epitaxial layer (not shown); Ions are doped into the layer to form a top source-drain doped layer 132.

By performing ion doping after forming the epitaxial layer, it is beneficial to accurately control the ion doping concentration in the top source-drain doping layer 132 .

In this embodiment, a solid-state source diffusion process is used to dope ions in the epitaxial layer. The solid-state source diffusion process causes less damage to the epitaxial layer, and is conducive to forming a higher doping concentration on the surface of the epitaxial layer, which is conducive to further reducing the contact resistance of subsequent contact hole plugs and the source-drain doped layer 130 .

In other embodiments, the step of forming the top source and drain doped layer may further include: performing epitaxial growth on the surface of the bottom source and drain doped layer where the remaining sidewall layer is exposed, forming an epitaxial layer, and forming the During the epitaxial layer process, in-situ self-doping ions form the top source and drain doped layer.

Therefore, in this embodiment, the semiconductor structure is used to form an NMOS transistor. The top source-drain doped layer 132 also includes an epitaxial layer doped with N-type ions. The material of the epitaxial layer can be Si or SiC, thereby forming an NMOS transistor. The channel region provides tensile stress, which is beneficial to improving the carrier mobility of the NMOS transistor, wherein the N-type ions are P ions, As ions or Sb ions. In other embodiments, when the semiconductor structure is used to form a PMOS transistor, the top source-drain doping layer includes an epitaxial layer doped with P-type ions. The material of the epitaxial layer can be Si or SiGe. The epitaxial layer is of the PMOS transistor. The channel region provides compressive stress, which is beneficial to improving the carrier mobility of the PMOS transistor, wherein the P-type ions are B ions, Ga ions or In ions.

It should be noted that the ion doping concentration in the top source-drain doped layer 132 should not be too low, nor should it be too high. If the ion doping concentration in the top source-drain doped layer 132 is too low, it is easy to make it difficult for the overall doping concentration of the source-drain doped layer 130 to meet the electrical requirements. For example, the carrier mobility of the semiconductor structure is too low, the contact The contact resistance between the hole plug and the source-drain doped layer 130 is too large; if the ion doping concentration in the top source-drain doped layer 132 is too high, the doped ions in the top source-drain doped layer 132 will move toward The probability of diffusion in the channel region is high, which is not conducive to improving the short channel effect of the semiconductor structure. To this end, in this embodiment, the semiconductor structure is used to form an NMOS transistor, and the top source-drain doping layer 132 is doped with N-type ions. The doping concentration of the N-type ions is 5.0E20 atoms per cubic cm to 1.0E22 atoms per cubic centimeter. In other embodiments, when the semiconductor structure is used to form a PMOS transistor, the top source-drain doping layer is doped with P-type ions, and the doping concentration of the P-type ions is 1.2E20 atoms per cubic centimeter to 8.0E21 atoms per cubic centimeter.

It should also be noted that the volume of the top source-drain doped layer 132 should not be too small, nor should it be too large. If the volume of the top source-drain doped layer 132 is too small, the stress in the source-drain doped layer 130 is too small, and the carrier mobility of the semiconductor structure is low; if the volume of the top source-drain doped layer 132 is too large, It is easy to cause the parasitic capacitance on the source-drain doped layer 130 to be too large. For this reason, in this embodiment, the thickness of the top source-drain doped layer 132 located on the top of the bottom source-drain doped layer 131 is 3 nm to 10 nm, and the top source-drain doped layer 132 located on the sidewall of the bottom source-drain doped layer 131 has a thickness of 3 nm to 10 nm. The thickness is 2 nm to 6 nm, so that the volume of the top source and drain doped layer 132 meets the process requirements.

Specifically, in this embodiment, the sidewalls of the top source-drain doped layer 132 are flush with the sidewalls of the remaining sidewall layers 125, which is conducive to precise control of the top source-drain doped layer 132 at the bottom. The thickness on the sidewalls of the source and drain doped layer 131 reduces process difficulty. The sidewalls of the top source-drain doped layer 132 refer to the sidewalls of the top source-drain doped layer 132 that are not in contact with the bottom source-drain doped layer 131 .

Referring to FIG. 20 , in this embodiment, after forming the top source-drain doped layer 132 , it also includes: removing the sidewall layer 125 ; after removing the sidewall layer 125 , forming an electrical connection with the source-drain doped layer 130 The contact hole plug 135 covers the top and side walls of the source and drain doped layer 130 .

In this embodiment, the source-drain doped layer 130 includes a bottom source-drain doped layer 131 and a top source-drain doped layer 132 covering its top and part of the sidewalls. The surface area of the source-drain doped layer 130 is large, so The contact area between the contact hole plug 135 and the source-drain doped layer 130 is also large, and the contact resistance between the two is small. Moreover, the ion doping concentration of the top source-drain doped layer 132 is large, which can further reduce The contact resistance between the source-drain doped layer 130 and the contact hole plug 135 optimizes the electrical performance of the semiconductor structure.

By removing the sidewall layer 125 , a process platform is provided for forming the contact hole plug 135 .

The contact hole plug 135 is used for electrical connection between the source and drain doped layer 130, the back-end metal layer, and external circuits. In this embodiment, the contact hole plug 135 is made of W and can be formed by chemical vapor deposition, sputtering or electroplating. In other embodiments, the material of the contact hole plug may also be a metal material such as Al, Cu, Ag, Au or Co.

Specifically, the steps of forming the contact hole plug 135 include: forming an interlayer dielectric layer 137 on the substrate 100 where the gate structure 114 is exposed; forming a contact hole (not shown) in the interlayer dielectric layer 137 , the contact hole exposes the top and sidewalls of the source-drain doped layer 130; the contact hole is filled with conductive material to form a contact hole plug 135.

It should be noted that in this embodiment, a silicide layer 136 is also formed between the contact hole plug 135 and the source and drain doped layer 130, which is beneficial to further reducing the contact hole plug 135 and the source and drain doped layer 130. The contact resistance between the source and drain doped layers 130.

Correspondingly, the present invention also provides a semiconductor structure. Referring to FIG. 20 , a schematic structural diagram of an embodiment of the semiconductor structure of the present invention is shown.

The semiconductor structure includes: a substrate 100; a fin portion 110 protruding from the substrate 100; a gate structure 114 (as shown in FIG. 14) spanning the fin portion 110 and covering the fin portion 110. Part of the top and part of the sidewall; the source-drain doped layer 130 is located in the fins 110 on both sides of the gate structure 114. The source-drain doped layer 130 includes a bottom source-drain doped layer 131 and covers the bottom. The top source-drain doped layer 132 on the top of the source-drain doped layer 131 and part of the sidewalls, the doping ion types in the top source-drain doped layer 132 and the bottom source-drain doped layer 131 are the same, and the top source-drain doped layer 132 The ion doping concentration in the drain doped layer 132 is greater than the ion doping concentration of the bottom source and drain doped layer 131 .

In this embodiment, the source-drain doped layer 130 includes a bottom source-drain doped layer 131 and a top source-drain doped layer 132 covering its top and part of the sidewalls. The doping concentration of ions in the top source-drain doped layer 132 is greater than that of the bottom one. The doping concentration of ions in the source-drain doped layer 131, in order to make the overall doping concentration of the source-drain doped layer 130 meet the electrical requirements, is different from only forming the bottom source-drain doped layer and doping the bottom source-drain layer. Compared with the solution with a higher ion doping concentration in the layer, this embodiment can appropriately reduce the ion doping concentration in the bottom source-drain doping layer 131, which is beneficial to reducing the doping in the bottom source-drain doping layer 131. The probability of ions diffusing to the channel region is beneficial to improving the short channel effect.

Moreover, the inversion layer is usually formed in an area close to the top of the fin 110 to form a conductive channel. The gate structure 114 has weak control over the bottom of the fin 110 and the probability of forming an inversion layer in the bottom of the fin 110 is low. , the probability of problems such as leakage current and short channel effect at the bottom of the fin 110 is relatively high. Compared with the solution in which all sidewalls of the bottom source-drain doped layer are covered by the top source-drain doped layer, this embodiment , the bottom of the bottom source-drain doped layer 131 is not covered by the top source-drain doped layer 132 , which is beneficial to further improving the short channel effect and reducing the probability of leakage current problems in the bottom of the fin 110 .

In addition, compared with the solution of only forming the bottom source-drain doped layer, this embodiment increases the surface area of the source-drain doped layer 130 through the top source-drain doped layer 132, thereby increasing the subsequent connection with the source-drain doped layer. The contact area of the contact hole plug and the source-drain doped layer 130 that is electrically connected to the doped layer 130, and the concentration of the top source-drain doped layer 132 is relatively large, which is beneficial to reducing the contact hole plug and the source-drain doped layer 130. The contact resistance of the doped layer 130 improves the electrical performance of the semiconductor structure.

The substrate 100 is used to provide a process platform for the formation of semiconductor structures.

In this embodiment, the substrate 100 is a silicon substrate. In other embodiments, the material of the substrate can also be other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium. The substrate can also be a silicon substrate on an insulator or an insulator. on germanium substrates and other types of substrates.

The fin portion 110 is used to provide a conductive channel of the fin field effect transistor.

In this embodiment, the fin portion 110 and the substrate 100 are obtained by etching the same semiconductor layer. In other embodiments, the fin portion may also be a semiconductor layer grown epitaxially on the substrate, thereby achieving the purpose of accurately controlling the height of the fin portion.

Therefore, in this embodiment, the material of the fin portion 110 is the same as the material of the substrate 100 , and the material of the fin portion 110 is silicon. In other embodiments, the material of the fins may also be germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium.

It should be noted that the semiconductor structure further includes an isolation layer 111 located on the substrate 100 where the fin 110 is exposed and covering part of the sidewall of the fin 110 . The isolation layer 111 is used to electrically isolate adjacent devices.

In this embodiment, the material of the isolation layer 111 is silicon oxide. In other embodiments, the material of the isolation layer may also be an insulating material such as silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, or silicon oxycarboxynitride.

The gate structure 114 includes a gate oxide layer 112 (shown in FIG. 14 ) and a gate layer 113 (shown in FIG. 14 ) located on the gate oxide layer 112 .

The material of the gate oxide layer 112 is silicon oxide or silicon oxynitride, and the material of the gate layer 113 is polysilicon, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon oxynitride or amorphous carbon. . In this embodiment, the material of the gate oxide layer 112 is silicon oxide, and the material of the gate layer 113 is polysilicon.

In other embodiments, the gate structure may also be a metal gate structure.

In this embodiment, the gate oxide layer 112 is only located at the bottom of the gate layer 113 . In other embodiments, the gate oxide layer may also cover the exposed fin surface of the gate layer.

In this embodiment, a pad oxide layer 115 (as shown in FIG. 14 ) and a gate mask layer 116 (as shown in FIG. 14 ) located on the pad oxide layer 115 are also formed on the top of the gate structure 114 . Show).

The gate mask layer 116 is used as an etching mask to form the gate layer 113. The gate mask layer 116 is also used to protect the top of the gate layer 113 during the formation process of the semiconductor structure. . In this embodiment, the gate mask layer 116 is made of silicon nitride.

The pad oxide layer 115 is used to play a stress buffering role when forming the gate mask layer 116 and using the gate mask layer 116 as a mask to form the gate layer 113, thereby improving the gate mask layer. The adhesion between the film layer 116 and the gate layer 113 avoids the problem of dislocation caused by direct contact between the gate mask layer 116 and the gate layer 113 . In this embodiment, the material of the pad oxide layer 115 is silicon oxide.

As shown in Figure 14, the semiconductor structure also includes: a first spacer 118 located on the sidewalls of the gate layer 113, the pad oxide layer 115 and the gate mask layer 116; a second spacer 119, Located on the side wall of the first side wall 118 .

The first spacers 118 are used to protect the sidewalls of the gate layer 113 during the formation process of the semiconductor structure. In this embodiment, the material of the first spacer 118 is silicon nitride. In other embodiments, the material of the first sidewall can also be silicon oxide, silicon oxynitride, silicon carbide, silicon oxycarbide or silicon oxynitride.

The second spacers 119 are also used to protect the sidewalls of the gate layer 113 during the formation of the semiconductor structure. The second spacers 119 are also used to define the formation area of the source and drain doped layers 130 along the extension direction of the fins 110 .

In this embodiment, the second spacer 119 and the sidewall layer 125 are made of the same material, and the second spacer 119 is made of silicon nitride. In other embodiments, the material of the second side wall can also be silicon oxide, silicon oxynitride, silicon carbide, silicon oxycarbon or silicon oxynitride.

In this embodiment, the semiconductor structure is used to form an NMOS transistor. The bottom source-drain doped layer 131 and the top source-drain doped layer 132 both include an epitaxial layer doped with N-type ions. The material of the epitaxial layer can be Si or SiC, thereby providing tensile stress to the channel region of the NMOS transistor, which is beneficial to improving the carrier mobility of the NMOS transistor. Among them, the N-type ions are P ions, As ions or Sb ions. In other embodiments, when the semiconductor structure is used to form a PMOS transistor, the bottom source-drain doping layer and the top source-drain doping layer include an epitaxial layer doped with P-type ions, and the material of the epitaxial layer can be Si or SiGe. , thereby providing compressive stress to the channel region of the PMOS transistor, which is beneficial to improving the carrier mobility of the PMOS transistor, where the P-type ions are B ions, Ga ions or In ions.

It should be noted that in this embodiment, the ion doping concentration in the bottom source-drain doped layer 131 should not be too low, nor should it be too high. If the ion doping concentration in the bottom source-drain doping layer 131 is too low, it is easy for the overall doping concentration of the source-drain doping layer 130 to meet the electrical requirements; if the ion doping concentration in the bottom source-drain doping layer 131 If it is too high, the probability of doping ions in the bottom source-drain doping layer 131 to diffuse to the channel region is high, which is not conducive to improving the short channel effect of the semiconductor structure. To this end, in this embodiment, the semiconductor structure is used to form an NMOS transistor, and the bottom source-drain doping layer 131 is doped with N-type ions. The doping concentration of the N-type ions is 3.0E20 atoms per cubic centimeter to 8.0E21 atoms per cubic centimeter. In other embodiments, when the semiconductor structure is used to form an NMOS transistor, the bottom source-drain doping layer is doped with P-type ions, and the doping concentration of the P-type ions is 1.0E20 atoms per cubic centimeter to 4.0E20 atoms per cubic centimeter.

It should also be noted that the ion doping concentration in the top source-drain doped layer 132 should not be too low or too high. If the ion doping concentration in the top source-drain doped layer 132 is too low, the overall doping concentration of the source-drain doped layer 130 is difficult to meet the electrical requirements. For example, the carrier mobility of the semiconductor structure is too low, the contact hole The contact resistance between the plug and the source-drain doped layer 130 is too large, etc.; if the ion doping concentration in the top source-drain doped layer 132 is too high, the doped ions in the top source-drain doped layer 132 will flow into the trench. The probability of spreading in the road area is relatively high. To this end, in this embodiment, the semiconductor structure is used to form an NMOS transistor, and the top source-drain doping layer 132 is doped with N-type ions. The doping concentration of the N-type ions is 5.0E20 atoms per cubic cm to 1.0E22 atoms per cubic centimeter. In other embodiments, when the semiconductor structure is used to form a PMOS transistor, the top source-drain doping layer is doped with P-type ions, and the doping concentration of the P-type ions is 1.2E20 atoms per cubic centimeter to 8.0E21 atoms per cubic centimeter.

In addition, the volume of the top source-drain doped layer 132 should not be too small or too large. If the volume of the top source-drain doped layer 132 is too small, the stress in the source-drain doped layer 130 is too small, and the carrier mobility of the semiconductor structure is low; if the top source-drain doped layer 132 If the volume of 132 is too large, the parasitic capacitance on the source-drain doped layer 130 may be too large. For this reason, in this embodiment, the thickness of the top source-drain doped layer 132 located on the top of the bottom source-drain doped layer 131 is 3 nm to 10 nm, and the top source-drain doped layer 132 located on the side wall of the bottom source-drain doped layer 131 has a thickness of 3 nm to 10 nm. The thickness of the doping layer 132 is 2nm to 6nm.

In this embodiment, the height of the bottom source-drain doped layer 131 exposed by the top source-drain doped layer 132 should not be too small, nor should it be too large. If the height is too small, the top source-drain doped layer 132 is too close to the bottom of the fin 110 , and the doping ions in the top source-drain doped layer 132 have a higher probability of diffusing into the bottom of the fin 110 , which is not conducive to Improve the short channel effect of the semiconductor structure; if the height is too large, the volume and surface area of the top source-drain doped layer 132 will be too small, which will easily cause the overall doping of the source-drain doped layer 130 to The concentration is difficult to meet the electrical requirements. For example, the contact area between the top source-drain doped layer 132 and subsequent contact hole plugs is too small, so that the contact resistance between the source-drain doped layer 130 and the contact hole plugs is too large, and so If the volume of the top source-drain doped layer 132 is too small, it will easily cause the stress in the source-drain doped layer 130 to be too small, which is not conducive to improving the carrier mobility of the semiconductor structure. For this reason, in this embodiment, the height of the bottom source-drain doped layer 131 exposed by the top source-drain doped layer 132 is 15 nm to 25 nm.

As shown in Figure 20, in this embodiment, the semiconductor structure further includes: a contact hole plug 135, which is electrically connected to the source and drain doped layer 130. The contact hole plug 135 covers the top and sides of the source and drain doped layer 130. wall.

In this embodiment, the source-drain doped layer 130 includes a bottom source-drain doped layer 131 and a top source-drain doped layer 132 covering its top and part of the sidewalls. The surface area of the source-drain doped layer 130 is relatively large. Therefore, the contact area between the contact hole plug 135 and the source-drain doped layer 130 is also larger, and the contact resistance between the two is smaller. Moreover, the ion doping concentration of the top source-drain doped layer 132 is larger, which can further reduce the The contact resistance between the source-drain doped layer 130 and the contact hole plug 135 is reduced, thereby optimizing the electrical performance of the semiconductor structure.

The contact hole plug 135 is used for electrical connection between the source and drain doped layer 130, the back-end metal layer, and external circuits. In this embodiment, the material of the contact hole plug 135 is W. In other embodiments, the material of the contact hole plug may also be a metal material such as Al, Cu, Ag, Au or Co.

It should be noted that in this embodiment, the semiconductor structure further includes: a silicide layer 136 located between the contact hole plug 135 and the source and drain doping layer 130 . The silicide layer 136 is used to further reduce the contact resistance between the contact hole plug 135 and the source-drain doped layer 130 .

In addition, the semiconductor structure further includes: an interlayer dielectric layer 137 located on the substrate 100 where the gate structure 114 is exposed.

The interlayer dielectric layer 137 is used to provide a process platform for the formation of the contact hole plug 135. The interlayer dielectric layer 137 is also used to isolate adjacent devices. The material of the interlayer dielectric layer 137 is an insulating material, such as silicon oxide, nitrogen. One or more of silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon oxynitride.

The semiconductor structure may be formed using the forming method described in the previous embodiment, or may be formed using other forming methods. For the specific description of the semiconductor structure described in this embodiment, reference may be made to the corresponding description in the foregoing embodiments, which will not be described again in this embodiment.

Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be subject to the scope defined by the claims.

Claims (18)

1. A method for forming a semiconductor structure, characterized by comprising: Forming a substrate, the substrate includes a substrate, a fin protruding from the substrate, and a gate structure spanning the fin, the gate structure covering part of the top and part of the sidewall of the fin; A sidewall layer is formed on the side of the fin exposed by the gate structure, and the sidewall layer is in contact with the entire side of the fin exposed by the gate structure; removing a portion of the thickness of the fin to form an opening surrounded by the sidewall layer and the remaining fin; A bottom source-drain doped layer is formed in the opening, and the top surface of the bottom source-drain doped layer is flush with the top surface of the sidewall layer; Remove part of the height of the sidewall layer in a direction perpendicular to the substrate surface so that the top surface of the sidewall layer is lower than the top surface of the bottom source and drain doped layer; Forming a top source-drain doping layer to cover the top and side walls of the bottom source-drain doping layer exposed by the remaining sidewall layer, the top source-drain doping layer and the bottom source-drain doping layer constitute a source-drain doping layer, The doping ions in the top source-drain doping layer and the bottom source-drain doping layer are of the same type, and the doping concentration of the ions in the top source-drain doping layer is greater than the doping concentration of the ions in the bottom source-drain doping layer. Doping concentration; the sidewalls of the top source-drain doped layer are flush with the sidewalls of the remaining sidewall layers; After the top source-drain doped layer is formed, the sidewall layer is removed to expose the bottom surface of the top source-drain doped layer and the side of the bottom source-drain doped layer exposed by the top source-drain doped layer. wall. 2. The method of forming a semiconductor structure according to claim 1, wherein after removing part of the height of the sidewall layer, the height of the remaining sidewall layer is 15 nm to 25 nm. 3. The method of forming a semiconductor structure according to claim 1, wherein a dry etching process is used to remove part of the thickness of the sidewall layer. 4. The method of forming a semiconductor structure according to claim 3, wherein the parameters of the dry etching process include: a bias voltage of 80V to 250V, a process pressure of 10mtorr to 200mtorr, and an etching power of 100W. to 400W, the etching time is 10S to 200S. 5. The method of forming a semiconductor structure according to claim 1, wherein the top source-drain doped layer is doped with N-type ions, and the doping concentration of the N-type ions is 5.0E20 atoms per cubic cm to 1.0E22 atoms per cubic centimeter; alternatively, the top source-drain doping layer is doped with P-type ions, and the doping concentration of the P-type ions is 1.2E20 atoms per cubic centimeter to 8.0E21 atoms per cubic centimeter. . 6. The method of forming a semiconductor structure according to claim 1, wherein the bottom source and drain doped layer is doped with N-type ions, and the doping concentration of the N-type ions is 3.0E20 atoms per cubic cm to 8.0E21 atoms per cubic centimeter; alternatively, the bottom source-drain doping layer is doped with P-type ions, and the doping concentration of the P-type ions is 1.0E20 atoms per cubic centimeter to 4.0E20 atoms per cubic centimeter. . 7. The method of forming a semiconductor structure according to claim 1, wherein the step of forming the top source-drain doped layer includes: performing epitaxial growth on the surface of the bottom source-drain doped layer exposed by the remaining sidewall layer, Form an epitaxial layer, and in-situ self-doping ions form the top source-drain doped layer during the formation of the epitaxial layer; or, perform epitaxial growth on the surface of the bottom source-drain doped layer where the remaining sidewall layer is exposed , forming an epitaxial layer; doping ions in the epitaxial layer to form a top source-drain doped layer. 8. The method of forming a semiconductor structure according to claim 7, wherein a solid-state source diffusion process is used to dope ions in the epitaxial layer. 9. The method of forming a semiconductor structure according to claim 1, wherein in the step of forming the top source-drain doped layer, the thickness of the top source-drain doped layer located on top of the bottom source-drain doped layer The thickness of the top source and drain doped layer located on the sidewall of the bottom source and drain doped layer is 2 nm to 6 nm. 10. The method of forming a semiconductor structure according to claim 1, wherein the process of forming the sidewall layer includes an atomic layer deposition process. 11. The method of forming a semiconductor structure according to claim 1, wherein the sidewall layer is made of silicon nitride, silicon carbonitride, boron silicon nitride carbon or silicon oxynitride carbon. 12. The method of forming a semiconductor structure according to claim 1, further comprising: after removing the sidewall layer, forming a contact hole plug electrically connected to the source and drain doped layer, the contact Hole plugs cover the top and sidewalls of the source and drain doped layers. 13. A semiconductor structure, characterized by comprising: substrate; fins protruding from the substrate; a gate structure spanning the fin and covering part of the top and part of the sidewall of the fin; A source-drain doping layer located in the fins on both sides of the gate structure. The source-drain doping layer includes a bottom source-drain doping layer and a top source covering the top and part of the sidewall of the bottom source-drain doping layer. Drain doping layer, the doping ion type in the top source and drain doping layer and the bottom source and drain doping layer are the same, and the ion doping concentration in the top source and drain doping layer is greater than the bottom source and drain doping layer ion doping concentration; the top surface of the bottom source-drain doped layer is flush with the top surface of the fin at the bottom of the gate structure; and the side walls of the top source-drain doped layer are flush with the side walls of the fin parallel to each other; Wherein, the step of forming the source-drain doped layer includes: after forming the top source-drain doped layer, removing the sidewall layer to expose the bottom surface of the top source-drain doped layer and the top source-drain doped layer. The sidewalls of the bottom source and drain doped layer are exposed by the layer. 14. The semiconductor structure of claim 13, wherein the height of the bottom source-drain doped layer exposed by the top source-drain doped layer is 15 nm to 25 nm. 15. The semiconductor structure of claim 13, wherein the top source-drain doping layer is doped with N-type ions, and the doping concentration of the N-type ions is 5.0E20 atoms per cubic centimeter to 1.0 E22 atoms per cubic centimeter; alternatively, the top source-drain doping layer is doped with P-type ions, and the doping concentration of the P-type ions is 1.2E20 atoms per cubic centimeter to 8.0E21 atoms per cubic centimeter. 16. The semiconductor structure of claim 13, wherein the bottom source and drain doped layer is doped with N-type ions, and the doping concentration of the N-type ions is 3.0E20 atoms per cubic centimeter to 8.0 E21 atoms per cubic centimeter; alternatively, the bottom source-drain doping layer is doped with P-type ions, and the doping concentration of the P-type ions is 1.0E20 atoms per cubic centimeter to 4.0E20 atoms per cubic centimeter. 17. The semiconductor structure of claim 13, wherein the thickness of the top source-drain doped layer located on top of the bottom source-drain doped layer is 3 nm to 10 nm, and the thickness of the top source-drain doped layer located on the side wall of the bottom source-drain doped layer The top source-drain doped layer thickness is 2nm to 6nm. 18. The semiconductor structure of claim 13, further comprising: a contact hole plug electrically connected to the source-drain doped layer, the contact hole plug covering the source-drain doped layer Top and side walls.