CN111406282A - A memory control circuit for a storage device - Google Patents
A memory control circuit for a storage device Download PDFInfo
- Publication number
- CN111406282A CN111406282A CN201880076748.6A CN201880076748A CN111406282A CN 111406282 A CN111406282 A CN 111406282A CN 201880076748 A CN201880076748 A CN 201880076748A CN 111406282 A CN111406282 A CN 111406282A
- Authority
- CN
- China
- Prior art keywords
- memory
- data blocks
- control circuit
- reading
- writing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
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Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
Landscapes
- Techniques For Improving Reliability Of Storages (AREA)
Abstract
A memory control circuit (400) relates to the field of digital circuits, and is used for reading and writing data in a nonvolatile memory (160), and comprises an exclusive-nor circuit (420) and a reading and writing control circuit (440). The exclusive-nor circuit (420) is used for carrying out bitwise exclusive-nor operation on a plurality of data blocks and generating redundant data blocks, and the read-write control circuit (440) is used for writing the data blocks and the redundant data blocks into the nonvolatile memory (160) and reading the data blocks from the nonvolatile memory (160), wherein the data blocks and the redundant data blocks are stored in one storage unit. Wherein the non-volatile memory (160) comprises a plurality of memory cells, each memory cell having a capacity of n bits and having a capacity of 2nAnd the number of the data blocks is n-1, and n is an integer greater than or equal to 2. Since there is only 2 in each memory celln‑1Since the memory states are used for storing data, the difference of the threshold voltages corresponding to the memory states is about twice that of the original threshold voltages, so that the overlapping degree of the memory states is reduced, and the probability of reading error data by the memory control circuit (400) is reduced.
Description
PCT国内申请,说明书已公开。PCT domestic application, the description has been published.
Claims (16)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| PCT/CN2018/084116 WO2019204967A1 (en) | 2018-04-23 | 2018-04-23 | Memory control circuit for use in storage device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN111406282A true CN111406282A (en) | 2020-07-10 |
| CN111406282B CN111406282B (en) | 2022-06-07 |
Family
ID=68293434
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201880076748.6A Active CN111406282B (en) | 2018-04-23 | 2018-04-23 | Memory control circuit for memory device |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN111406282B (en) |
| WO (1) | WO2019204967A1 (en) |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102063266A (en) * | 2009-11-18 | 2011-05-18 | 联发科技股份有限公司 | Non-volatile memory controller and method for writing current data into non-volatile memory |
| US20140029355A1 (en) * | 2012-07-24 | 2014-01-30 | Samsung Electronics Co., Ltd. | Memory device and method of determining read voltage of memory device |
| CN104679448A (en) * | 2015-02-05 | 2015-06-03 | 深圳市硅格半导体有限公司 | Data bit stream conversion method and device |
| US9281049B1 (en) * | 2014-10-28 | 2016-03-08 | Xilinx, Inc. | Read clock forwarding for multiple source-synchronous memory interfaces |
| CN105632558A (en) * | 2014-11-24 | 2016-06-01 | 三星电子株式会社 | Cross-point memory device including multi-level cells and operating method thereof |
| CN107027326A (en) * | 2015-11-25 | 2017-08-08 | 华为技术有限公司 | The method and device of data backup in storage system |
| CN107527645A (en) * | 2016-06-22 | 2017-12-29 | 爱思开海力士有限公司 | The interface circuit related to variable delay and include its semiconductor device and system |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8041886B2 (en) * | 2008-09-15 | 2011-10-18 | Seagate Technology Llc | System and method of managing memory |
| US8316175B2 (en) * | 2009-11-03 | 2012-11-20 | Inphi Corporation | High throughput flash memory system |
| CN101751334B (en) * | 2009-12-30 | 2012-03-21 | 中国人民解放军国防科学技术大学 | Hardware fault detection method based on reducing program |
| CN102855934B (en) * | 2012-08-23 | 2016-09-28 | 上海华虹宏力半导体制造有限公司 | Nonvolatile memory system and method for deleting thereof |
| WO2014109771A1 (en) * | 2013-01-14 | 2014-07-17 | Hewlett-Packard Development Company, L.P. | Nonvolatile memory array logic |
-
2018
- 2018-04-23 CN CN201880076748.6A patent/CN111406282B/en active Active
- 2018-04-23 WO PCT/CN2018/084116 patent/WO2019204967A1/en not_active Ceased
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102063266A (en) * | 2009-11-18 | 2011-05-18 | 联发科技股份有限公司 | Non-volatile memory controller and method for writing current data into non-volatile memory |
| US20140029355A1 (en) * | 2012-07-24 | 2014-01-30 | Samsung Electronics Co., Ltd. | Memory device and method of determining read voltage of memory device |
| US9281049B1 (en) * | 2014-10-28 | 2016-03-08 | Xilinx, Inc. | Read clock forwarding for multiple source-synchronous memory interfaces |
| CN105632558A (en) * | 2014-11-24 | 2016-06-01 | 三星电子株式会社 | Cross-point memory device including multi-level cells and operating method thereof |
| CN104679448A (en) * | 2015-02-05 | 2015-06-03 | 深圳市硅格半导体有限公司 | Data bit stream conversion method and device |
| CN107027326A (en) * | 2015-11-25 | 2017-08-08 | 华为技术有限公司 | The method and device of data backup in storage system |
| CN107527645A (en) * | 2016-06-22 | 2017-12-29 | 爱思开海力士有限公司 | The interface circuit related to variable delay and include its semiconductor device and system |
Also Published As
| Publication number | Publication date |
|---|---|
| CN111406282B (en) | 2022-06-07 |
| WO2019204967A1 (en) | 2019-10-31 |
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