CN111313703A - Pulse sequence controlled PCCM Buck converter - Google Patents

Abstract

The present application discloses a pulse sequence controlled PCCM Buck converter, comprising: a main circuit, a current detection circuit, a first voltage comparator, a second voltage comparator, a charge control circuit and a pulse selection circuit; an output end of the main circuit is coupled to To the reverse input terminal of the first voltage comparator, the forward input terminal of the first voltage comparator is connected to the reference voltage; the output terminal of the first voltage comparator is coupled to the input terminal of the pulse selection circuit, and the output terminal of the pulse selection circuit is coupled to the main circuit and the first input end of the logic control circuit; the input end of the current detection circuit is coupled to the main circuit, and the output end of the current detection circuit is coupled to the reverse input end of the second voltage comparator, and the forward direction of the second voltage comparator The input end is coupled to the output end of the charge control circuit, the output end of the second voltage comparator is coupled to the second input end of the logic control circuit; the output end of the logic control circuit is coupled to the current detection circuit; the charge control circuit is used for providing freewheeling value.

Description

Pulse Train Controlled PCCM Buck Converter

technical field

The present application relates to the technical field of integrated circuits, and in particular, to a PCCM Buck converter controlled by a pulse sequence.

Background technique

With the development of portable power electronic devices, switching power converters, such as DC-DC converters with high efficiency to provide large currents, have been widely used. Conventional linear control techniques, such as pulse-width modulation (PWM), including both voltage-mode and current-mode, struggle to meet expectations in terms of transient response and robustness. As a nonlinear technique, PT control has been proposed in recent years, which has the advantages of simple implementation, no complex compensation and fast transient response. PT control has been widely used in switching converters operating in discontinuous conduction mode (DCM) and continuous conduction mode (CCM).

CCM is suitable for medium and high power applications, but has poor transient performance. Compared to CCM, DCM uses a simple control scheme and avoids the output diode reverse recovery problem, but results in larger current ripple and more severe electromagnetic interference (EMI). Combining the advantages of CCM and DCM, pseudo continuous conduction mode (PCCM) has better transient response and better load capacity.

SUMMARY OF THE INVENTION

The technical problem to be solved by the embodiments of the present application is to provide a PCCM Buck converter with pulse sequence control with fast transient state, simple circuit structure and small current ripple.

In order to solve the above problem, an embodiment of the present application provides a PCCM Buck converter controlled by a pulse sequence, including:

a main circuit, a current detection circuit, a first voltage comparator, a second voltage comparator, a charge control circuit, a pulse selection circuit and a logic control circuit;

The main circuit includes a first switch tube, a second switch tube, a third switch tube, an inductor and a first capacitor;

The source stage of the first switch tube is connected to the first voltage input end of the main circuit, the drain stage of the first switch tube is connected to the drain stage of the second switch tube and one end of the inductor, so The source stage of the second switch tube is connected to the second voltage input terminal of the main circuit, the source stage of the third switch tube is connected to the drain stage of the first switch tube, and the drain stage of the third switch tube is connected. The stage is connected to one end of the first capacitor, and the other end of the first capacitor is connected to the source stage of the second switch;

The output terminal of the main circuit is coupled to the reverse input terminal of the first voltage comparator, and the forward input terminal of the first voltage comparator is connected to a reference voltage;

The output end of the first voltage comparator is coupled to the input end of the pulse selection circuit, and the output end of the pulse selection circuit is coupled to the first switch tube and the first input end of the logic control circuit;

The input terminal of the current detection circuit is coupled to the source and gate of the second switch tube, the voltage output terminal of the current detection circuit is coupled to the reverse input terminal of the second voltage comparator, the first The forward input terminal of the two voltage comparators is coupled to the output terminal of the charge control circuit, and the output terminal of the second voltage comparator is coupled to the second input terminal of the logic control circuit;

an output end of the logic control circuit is coupled to the second switch tube and the third switch tube;

The charge control circuit is used to provide a freewheeling value.

Further, the pulse selection circuit is configured to output a high duty cycle pulse signal at the beginning of any switching cycle when the output voltage of the main circuit is lower than the reference voltage; otherwise, output a low duty cycle pulse Signal.

Further, the current detection circuit further includes a first PMOS tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube, a sixth PMOS tube, a first NMOS tube, a second NMOS tube, The third NMOS tube and the fourth NMOS tube;

The first PMOS transistor, the second PMOS transistor and the third PMOS transistor are connected in a current mirror structure, the gate of the fourth PMOS transistor is connected to the drain of the third PMOS transistor, and the drain of the second NMOS transistor is the drain level is connected, the drain level of the fourth PMOS transistor is connected to the source level of the second NMOS transistor, and the drain level of the fourth NMOS transistor is connected;

The fifth PMOS transistor and the sixth PMOS transistor are connected by a current mirror structure, the gates of the fifth PMOS transistor and the sixth PMOS transistor, and the drain of the sixth PMOS transistor are connected to the sixth PMOS transistor. Source level connection of four PMOS tubes;

The first NMOS transistor and the second NMOS transistor are connected in a current mirror structure, the gates of the first NMOS transistor and the second NMOS transistor, and the drain of the second NMOS transistor are connected to the first NMOS transistor. Drain connection of two PMOS tubes;

The drain stage of the third NMOS transistor is connected to the source stage of the first NMOS transistor, the gate of the third NMOS transistor is connected to the gate of the second switch transistor, and the source of the third NMOS transistor The stage is connected to the drain stage of the second switch tube;

The gate of the fourth NMOS transistor is connected to the gate of the second switch transistor, and the source of the fourth NMOS transistor is grounded.

Further, the charge control circuit includes:

the fifth NMOS transistor, the sixth NMOS transistor, the seventh NMOS transistor, the eighth NMOS transistor, the seventh PMOS transistor, the eighth PMOS transistor, the ninth PMOS transistor, and the second capacitor;

The fifth NMOS transistor, the sixth NMOS transistor and the seventh NMOS transistor are connected in a current mirror structure, and the gates of the fifth NMOS transistor, the sixth NMOS transistor and the seventh NMOS transistor and The drain stage of the fifth NMOS transistor is connected to a current source, and the source stages of the fifth NMOS transistor, the sixth NMOS transistor and the seventh NMOS transistor are connected to a power supply;

The gate of the seventh PMOS transistor is connected to the drain stage, the seventh PMOS transistor is connected to the eighth PMOS transistor in a current mirror structure, and the gate of the seventh PMOS transistor is connected to the gate of the eighth PMOS transistor The pole is connected to the drain stage of the sixth NMOS transistor, and the source stage of the seventh PMOS transistor and the eighth PMOS transistor are connected to the power supply;

The gate of the eighth NMOS transistor is coupled to the second switch transistor to access the driving signal of the second switch transistor, and the source level of the eighth NMOS transistor is connected to the drain level of the seventh NMOS transistor;

The gate of the ninth PMOS transistor is coupled to the third switch transistor to access the driving signal of the third switch transistor, and the source stage of the ninth PMOS transistor is connected to the and eighth PMOS transistors the drain connection;

The eighth NMOS transistor is connected to the drain stage of the ninth PMOS gate, and one end of the second capacitor is connected to the output end of the charge control circuit, and the other end of the second capacitor is grounded.

Further, the pulse selection circuit includes a flip-flop, a first AND gate circuit, a second AND gate circuit and an OR gate circuit;

The input terminal of the flip-flop is connected to the output terminal of the first voltage comparator, the high-level output terminal of the flip-flop is connected to the input terminal of the first AND gate circuit, and the low-level output terminal of the flip-flop is connected to the input terminal of the first AND gate circuit. The flat output terminal is connected to the input terminal of the second AND gate circuit, the output terminals of the first AND gate circuit and the second AND gate circuit are connected to the OR gate circuit, and the output terminal of the OR gate circuit is coupled to The first switch tube and the first input end of the logic control circuit.

Further, the flip-flops include D-type flip-flops.

Further, the first switch transistor is a PMOS transistor, and the second switch transistor and the third switch transistor are NMOS transistors.

Compared with the prior art, this embodiment realizes the detection of the MOS tube current through the above connection method, so that the freewheeling value changes with the change of the load current, so that the circuit maintains the PCCM state when the load changes and realizes fast transient. And in the transient state, different freewheeling values can be output with the change of the load to reduce the current ripple and avoid the circuit exiting the PCCM state when the load changes.

Description of drawings

1 is a schematic structural diagram of a PCCM Buck converter controlled by a pulse sequence provided in Embodiment 1 of the present application;

Figure 2 is a simplified circuit diagram of a current detection circuit;

Figure 3 is the timing sequence when the circuit load changes;

4 is a simplified circuit diagram of a charge control circuit;

Fig. 5 Change process of the output voltage of the charge control circuit when the circuit load changes.

Detailed ways

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, but not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

With the development of portable power electronic devices, switching power converters, such as DC-DC converters with high efficiency to provide large currents, have been widely used. Conventional linear control techniques, such as pulse-width modulation (PWM), including both voltage-mode and current-mode, struggle to meet expectations in terms of transient response and robustness. As a nonlinear technique, PT control has been proposed in recent years, which has the advantages of simple implementation, no complex compensation and fast transient response. PT control has been widely used in switching converters operating in discontinuous conduction mode (DCM) and continuous conduction mode (CCM).

CCM is suitable for medium and high power applications, but has poor transient performance. Compared to CCM, DCM uses a simple control scheme and avoids the output diode reverse recovery problem, but results in larger current ripple and more severe electromagnetic interference (EMI). Combining the advantages of CCM and DCM, pseudo continuous conduction mode (PCCM) has better transient response and better load capacity. The current boost converter has not been implemented in an integrated circuit. In addition, the implementation of the circuit in an integrated circuit also faces the problem of how to design the NMOS current detection. Therefore, referring to FIG. 1 , it is a schematic structural diagram of a pulse sequence controlled PCCM Buck converter provided in Embodiment 1 of the present application, including: a main circuit 1 , a current detection circuit 2 , a first voltage comparator COMP1 , and a second voltage comparator COMP2, charge control circuit 3, pulse selection circuit 4 and logic control circuit 5.

The main circuit 1 includes a first switch S1, a second switch S2, a third switch S3, an inductance L and a first capacitor C1.

The source stage of the first switch tube S1 is connected to the first voltage input terminal of the main circuit 1, that is, the positive terminal of the external power supply, the drain stage of the first switch tube S1 and the drain stage of the second switch tube S2 and the inductance L are connected. One end is connected, the source stage of the second switch tube S2 is connected to the second voltage input terminal of the main circuit 1, that is, the negative terminal of the external power supply is connected, and the source stage of the third switch tube S3 is connected to the drain stage of the first switch tube S1. , the drain of the third switch S3 is connected to one end of the first capacitor C1, and the other end of the first capacitor C1 is connected to the source of the second switch S2. The first switch transistor S1 is a PMOS transistor, and the second switch transistor S2 and the third switch transistor S3 are NMOS transistors.

The output terminal of the main circuit 1 is coupled to the inverting input terminal of the first voltage comparator COMP1 to output the voltage Vo to the inverting input terminal of the first voltage comparator COMP1, and the non-directional input terminal of the voltage comparator COMP1 is connected to the reference voltage Vref.

The output terminal of the first voltage comparator COMP1 is coupled to the input terminal of the pulse selection circuit 4, and its output signal is used as the input signal of the pulse selection circuit 4. The output terminal of the pulse selection circuit 4 is coupled to the first switch tube S1, and the logic control The first input of circuit 5.

The input end of the current detection circuit 2 is coupled to the source electrode and the gate electrode of the second switch tube S2 to perform current detection of the main circuit. The voltage output terminal of the current detection circuit 2 is coupled to the inverting input terminal of the second voltage comparator COMP2 to output the current detection voltage Vsen to the inverting input terminal of the second voltage comparator COMP2, and the forward direction of the first voltage comparator COMP1 The input terminal is coupled to the output terminal of the charge control circuit 3 to receive the voltage Vdc provided by the charge control circuit, and the output terminal of the second voltage comparator COMP2 is coupled to the second input terminal of the logic control circuit 5 .

The output end of the logic control circuit is coupled to the second switch S2 and the third switch S3, so that the two output signals are used as control signals of the switches S2 and S3 respectively.

The charge control circuit 3 is used to provide the freewheeling value. When the charge control circuit 3 provides the freewheeling value, the converter enters the freewheeling stage. At this time, when the switch S3 is turned on, the capacitor of the charge control circuit is charged, and the freewheeling value increases; when the switch S2 is turned on, the charge control The module capacitor discharges and the freewheeling value decreases. This allows the freewheeling value to vary with load current changes, allowing the circuit to maintain a PCCM state as the load changes, enabling fast transients.

In this embodiment, the first voltage comparator COMP1 compares the voltage value Vo formed by dividing the output voltage of the main circuit 1 with the reference voltage value Vref at the start of any switching cycle. When the divided output voltage of the main circuit 1 is lower than the reference voltage, the pulse selection circuit 4 will output a high duty cycle pulse signal PH, that is, the high level is used as the driving signal of the first switch S1; otherwise, the pulse selection circuit 4 A low duty cycle pulse signal PL is output, that is, a low level is used as the driving signal of the first switch tube. At this time, the first switch S1 is turned on, the second switch S2 and the third switch S3 are turned off, and the inductor current increases. When the pulse PH or PL ends, the second switch S2 is turned on, the first switch S1 and the third switch S3 are turned off, and the inductor current drops at this stage. At this time, the current detection voltage Vsen at the output of the current detection circuit 2 passes through The second voltage comparator COMP2 is compared with the output voltage Vdc output of the charge control circuit 3 . When Vsen reaches the freewheeling value, the third switch S3 is turned on, the first switch S1 and the second switch S2 are turned off, and the freewheeling stage is entered, in which the inductor current remains unchanged.

In this embodiment, the pulse selection circuit includes a D-type flip-flop, a first AND gate circuit AND1, a second AND gate circuit AND2, and an OR gate circuit OR.

The input terminal of the flip-flop D is connected to the output terminal of the first voltage comparator COMP1, that is, the input terminal of the first voltage comparator COMP1 as the data selector is connected to the D flip-flop. The high-level output terminal Q of the flip-flop D is connected to the input terminal of the first AND gate circuit AND1, the low-level output terminal Q' of the flip-flop D is connected to the input terminal of the second AND gate circuit AND2, and the first AND gate circuit The output terminals of AND1 and the second AND gate circuit AND2 are connected to the OR gate circuit OR, and the output terminal of the OR gate circuit OR is coupled to the first switch S1 and the first input terminal of the logic control circuit 5 . When the output voltage Vo is lower than the reference voltage Vref, the Q terminal of the D flip-flop outputs a high level; otherwise, the Q' terminal outputs a low level. Each pulse signal is connected to an AND gate, and when the conditions are met, the corresponding pulse signal is output.

Further, as shown in FIG. 2, the current detection circuit 2 further includes a PMOS transistor M1, a PMOS transistor M2, a PMOS transistor M3, a PMOS transistor M6, a PMOS transistor M7, a PMOS transistor M8, an NMOS transistor M4, an NMOS transistor M5, and an NMOS transistor M9. and NMOS transistor M10. The PMOS transistor M1, the PMOS transistor M2, the PMOS transistor M3, the NMOS transistor M4 and the NMOS transistor M5 form an operational amplifier. The source of the NMOS transistor M5 is the non-inverting input terminal of the operational amplifier, and the source of the NMOS transistor M4 is the inverting input terminal of the operational amplifier.

PMOS transistor M1, PMOS transistor M2 and PMOS transistor M3 are connected by a current mirror structure, that is, the gates of PMOS transistor M1, PMOS transistor M2 and PMOS transistor M3 and the drain of PMOS transistor M1 are connected to a current source and lead to a current output terminal. The gate of the PMOS transistor M6 is connected to the drain of the PMOS transistor M3 and the drain of the NMOS transistor M5. The drain of the PMOS transistor M6 is connected to the source of the NMOS transistor M5 and the drain of the NMOS transistor M10, thereby forming an operational amplifier negative feedback loop.

The PMOS transistor M7 and the PMOS transistor M8 are connected by a current mirror structure. The gates of the PMOS transistor M7 and the PMOS transistor M8 and the drain of the PMOS transistor M8 are connected to the source level of the PMOS transistor M6 and lead to a current output terminal. The output current will pass through the resistor R in FIG. 2 to form the current sense voltage Vsen.

The NMOS transistor M4 and the NMOS transistor M5 are connected in a current mirror structure, and the gates of the NMOS transistor M4 and the NMOS transistor M5, and the drain of the NMOS transistor M5 are connected to the drain of the PMOS transistor M2.

The drain stage of the NMOS transistor M9 is connected to the source stage of the NMOS transistor M4, that is, the inverting input terminal of the operational amplifier is connected. The gate of the NMOS transistor M9 is connected to the gate of the second switch transistor to receive the control signal Vs2. The source level of the NMOS transistor M9 is connected to the drain level of the second switch transistor, that is, the voltage Vsw is connected. The gate of the NOMS tube M10 is connected to the gate of the second switch tube S2 to receive the control signal N provided by the second switch tube, and the source of the NOMS tube M10 is grounded. At this time, the op amp is equivalent to a follower, making the voltages of points A and B equal.

During the drop of the inductor current, that is, in the D2T period shown in FIG. 3 , the currents of the first switch S2 and the node Vsw are both negative. However, since the amplifier composed of M1-M5 provides a DC bias, the The negative voltage VB becomes a positive value. As the inductor current falls, VSW rises and VB and VA rise. As shown in FIG. 3, the drop of the induced current is detected and becomes the rise of Vsen. And once Vsen increases to Vdc, the converter enters the freewheeling stage at this moment. This current-sensing circuit, unlike PWM-controlled current-mode, is a current-sensing technique suitable for NMOS rather than PMOS.

But in this case, when the load current increases, the curve of Vsen shifts down, so it takes longer to reach Vdc. On the other hand, if Vdc is fixed, an increase in load current will shorten D2T. If the increase is large, the converter may go into CCM, which can cause low frequency oscillations. Therefore, Vdc should vary adaptively with the load.

In this regard, the present embodiment provides a charge control circuit, as indicated in FIG. 4 , including an NMOS transistor MA1, an NMOS transistor MA2, an NMOS transistor MA3, an NMOS transistor Mdch, a PMOS transistor MB1, a PMOS transistor MB2, a PMOS transistor Mch, and a second Capacitor C2.

NMOS transistor MA1, NMOS transistor MA2 and NMOS transistor MA3 are connected by a current mirror structure, the gates of NMOS transistor MA1, NMOS transistor MA2 and NMOS transistor MA3 and the drain of NMOS transistor MA1 are connected to a current source and lead to a current output terminal, NMOS transistor The source stages of the tube MA1, the NMOS tube MA2 and the NMOS tube MA3 are connected to the power supply.

The PMOS tube MB1 is connected in the form of a diode, that is, the gate and the drain are connected, the PMOS tube MB1 is connected to the PMOS tube MB2 in a current mirror structure, and the PMOS tube MB1 and the gate of the PMOS tube MB2 are connected to the drain of the NMOS tube MA2 and lead out A current output terminal is generated, and the source stages of the PMOS transistor MB1 and the PMOS transistor MB2 are connected to the power supply.

The gate of the NMOS transistor Mdch is coupled to the second switch transistor S2 to access the driving signal Vs2 of the second switch transistor S2, and the source level of the NMOS transistor Mdch is connected to the drain level of the NMOS transistor MA3.

The gate of the PMOS transistor Mch is coupled to the third switch transistor S3 to access the drive signal Vs3 of the third switch transistor S3, and the source level of the PMOS transistor Mch is connected to the drain level of the PMOS transistor MB2;

The NMOS transistor Mdch is connected to the drain of the ninth PMOS gate, and one end of the second capacitor C2 is connected to the output end of the charge control circuit to output the voltage Vdc, and the other end of the second capacitor C2 is grounded.

At this time, Mch is turned on during D3T, and Mdch is turned on during D2T. Vdc is charged by the constant sink current Ich during D3T and discharged by the constant source current Idch=mIch during D2T. In steady state, as shown in the implementation in Figure 5, Vdc remains constant, and due to feedback, a suitable D3T can be achieved.

It satisfies:

I _oh ×D ₃ T=I _doh ×D ₂ T

Assume that the charging and discharging power of the capacitor are Qin and Qout, respectively. Have:

If the load current increases, the corresponding charge and discharge cycles of the inductor currents D'1T and D'2T need to be extended to provide more power. D'3T decreases accordingly, resulting in Qin being smaller than Qout. Therefore, Vdc is reduced to V'dc, as shown by the dotted line corresponding to the bottom Vdc mark on the right in FIG. 5 . Likewise, when the load decreases, as shown by the dotted line corresponding to the uppermost Vdc mark on the right in Figure 5, the Vdc value will also increase. In this way, the PCCM control signal Vdc can be adjusted adaptively based on the load current, and then different freewheeling values can be output with the change of the load during transients, so as to reduce the current ripple and prevent the circuit from exiting the PCCM when the load changes. state.

The above are the preferred embodiments of the present application. It should be pointed out that for those skilled in the art, without departing from the principles of the present application, several improvements and modifications can also be made, and these improvements and modifications may also be regarded as The protection scope of this application.

Claims (7)

1. A pulse train controlled PCCM Buck converter, comprising: the circuit comprises a main circuit, a current detection circuit, a first voltage comparator, a second voltage comparator, a charge control circuit, a pulse selection circuit and a logic control circuit;

the main circuit comprises a first switching tube, a second switching tube, a third switching tube, an inductor and a first capacitor;

a source of the first switching tube is connected to a first voltage input end of the main circuit, a drain of the first switching tube is connected with a drain of the second switching tube and one end of the inductor, a source of the second switching tube is connected to a second voltage input end of the main circuit, a source of the third switching tube is connected with the drain of the first switching tube, the drain of the third switching tube is connected with one end of the first capacitor, and the other end of the first capacitor is connected with the source of the second switching tube;

the output end of the main circuit is coupled to the reverse input end of the first voltage comparator, and the forward input end of the first voltage comparator is connected with a reference voltage;

the output end of the first voltage comparator is coupled to the input end of the pulse selection circuit, the output end of the pulse selection circuit is coupled to the first switch tube, and the first input end of the logic control circuit;

an input end of the current detection circuit is coupled to a source electrode and a grid electrode of the second switch tube, a voltage output end of the current detection circuit is coupled to a reverse input end of the second voltage comparator, a positive input end of the second voltage comparator is coupled to an output end of the charge control circuit, and an output end of the second voltage comparator is coupled to a second input end of the logic control circuit;

the output end of the logic control circuit is coupled to the second switching tube and the third switching tube;

the charge control circuit is used for providing a freewheel value.

2. The pulse train controlled PCCM Buck converter according to claim 1, wherein the pulse selection circuit is configured to output a high duty cycle pulse signal when the output voltage of the main circuit is lower than the reference voltage at the start of any one switching cycle; otherwise, outputting a low duty ratio pulse signal.

3. The pulse train controlled PCCM Buck converter according to claim 1, wherein the current sensing circuit further comprises a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a fourth NMOS transistor;

the first PMOS tube, the second PMOS tube and the third PMOS tube are connected in a current mirror structure, the grid electrode of the fourth PMOS tube is connected with the drain electrode of the third PMOS tube and the drain electrode of the second NMOS tube, and the drain electrode of the fourth PMOS tube is connected with the source electrode of the second NMOS tube and the drain electrode of the fourth NMOS tube;

the fifth PMOS tube is connected with the sixth PMOS tube in a current mirror structure, and the grid electrodes of the fifth PMOS tube and the sixth PMOS tube, and the drain electrode of the sixth PMOS tube are connected with the source electrode of the fourth PMOS tube;

the first NMOS tube is connected with the second NMOS tube in a current mirror structure, and the grid electrodes of the first NMOS tube and the second NMOS tube, and the drain electrode of the second NMOS tube are connected with the drain electrode of the second PMOS tube;

the drain of the third NMOS tube is connected with the source of the first NMOS tube, the grid of the third NMOS tube is connected with the grid of the second switch tube, and the source of the third NMOS tube is connected with the drain of the second switch tube;

and the grid electrode of the fourth NMOS tube is connected with the grid electrode of the second switch tube, and the source stage of the fourth NMOS tube is grounded.

4. The pulse train controlled PCCM Buck converter according to claim 1, wherein the charge control circuit comprises:

a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor and a second capacitor;

the fifth NMOS transistor, the sixth NMOS transistor and the seventh NMOS transistor are connected in a current mirror structure, the grid electrodes of the fifth NMOS transistor, the sixth NMOS transistor and the seventh NMOS transistor and the drain electrode of the fifth NMOS transistor are connected with a current source, and the source electrodes of the fifth NMOS transistor, the sixth NMOS transistor and the seventh NMOS transistor are grounded;

the grid electrode of the seventh PMOS tube is connected with the drain electrode, the seventh PMOS tube is connected with the eighth PMOS tube in a current mirror structure, the grid electrode of the seventh PMOS tube and the grid electrode of the eighth PMOS tube are connected with the drain electrode of the sixth NMOS tube, and the source electrodes of the seventh PMOS tube and the eighth PMOS tube are connected with the power supply;

the grid electrode of the eighth NMOS tube is coupled to the second switch tube so as to access a driving signal of the second switch tube, and the source electrode of the eighth NMOS tube is connected with the drain electrode of the seventh NMOS tube;

the grid electrode of the ninth PMOS tube is coupled to the third switching tube so as to access a driving signal of the third switching tube, and the source electrode of the ninth PMOS tube is connected with the drain electrode of the eighth PMOS tube;

and the eighth NMOS tube is connected with a drain of the ninth PMOS switch, one end of a second capacitor is connected with the output end of the charge control circuit, and the other end of the second capacitor is grounded.

5. The pulse train controlled PCCM Buck converter according to claim 1 or 2, wherein the pulse selection circuit comprises a flip-flop, a first and gate circuit, a second and gate circuit, and an or gate circuit;

the input end of the trigger is connected with the output end of the first voltage comparator, the high level output end of the trigger is connected with the input end of the first AND gate circuit, the low level output end of the trigger is connected with the input end of the second AND gate circuit, the output ends of the first AND gate circuit and the second AND gate circuit are connected with the OR gate circuit, and the output end of the OR gate circuit is coupled to the first switch tube and the first input end of the logic control circuit.

6. The pulse train controlled PCCM Buck converter according to claim 5, wherein the flip-flop comprises a class D flip-flop.

7. The pulse train controlled PCCM Buck converter according to claim 1, wherein the first switch is a PMOS transistor, and the second and third switch are NMOS transistors.

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